stats: Update stats to match cache changes

67 files changed, 61092 insertions, 60699 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index 3b6b51422..a07783bfc 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -1,109 +1,109 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.906037                       # Number of seconds simulated
-sim_ticks                                1906037467000                       # Number of ticks simulated
-final_tick                               1906037467000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.906049                       # Number of seconds simulated
+sim_ticks                                1906048606500                       # Number of ticks simulated
+final_tick                               1906048606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 252781                       # Simulator instruction rate (inst/s)
-host_op_rate                                   252781                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8583432112                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 376892                       # Number of bytes of host memory used
-host_seconds                                   222.06                       # Real time elapsed on the host
-sim_insts                                    56132533                       # Number of instructions simulated
-sim_ops                                      56132533                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 269376                       # Simulator instruction rate (inst/s)
+host_op_rate                                   269376                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9144869235                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 376080                       # Number of bytes of host memory used
+host_seconds                                   208.43                       # Real time elapsed on the host
+sim_insts                                    56145568                       # Number of instructions simulated
+sim_ops                                      56145568                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst           1050496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24857984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1044672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24858752                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25909440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1050496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1050496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7561088                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7561088                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              16414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388406                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25904384                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1044672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1044672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7563136                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7563136                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              16323                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388418                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                404835                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          118142                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               118142                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               551141                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13041708                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                404756                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          118174                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               118174                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               548083                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13042035                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               504                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13593353                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          551141                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             551141                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3966915                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3966915                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3966915                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              551141                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13041708                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13590621                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          548083                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             548083                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3967966                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3967966                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3967966                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              548083                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13042035                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              504                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17560268                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        404835                       # Number of read requests accepted
-system.physmem.writeReqs                       118142                       # Number of write requests accepted
-system.physmem.readBursts                      404835                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     118142                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25902720                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7559680                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25909440                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7561088                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total               17558587                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        404756                       # Number of read requests accepted
+system.physmem.writeReqs                       118174                       # Number of write requests accepted
+system.physmem.readBursts                      404756                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     118174                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25897280                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7561536                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25904384                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7563136                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          41709                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25494                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25705                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25829                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25773                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25090                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25012                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24715                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24579                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25194                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25292                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25390                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24989                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24533                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25560                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25835                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25740                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7824                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7665                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8071                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7733                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7203                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7017                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6707                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6431                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7312                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6902                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7273                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6973                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7066                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8009                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7985                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7949                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         303809                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25477                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25704                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25816                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25780                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25083                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25011                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24709                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24576                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25197                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25297                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25389                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25021                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24535                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25530                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25795                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25725                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7822                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7672                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8075                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7744                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7196                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7016                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6702                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6427                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7310                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6908                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7272                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7002                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7086                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7981                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7993                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7943                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1906028705500                       # Total gap between requests
+system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1906039923500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  404835                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  404756                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 118142                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    402462                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2192                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        64                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 118174                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402408                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        63                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -148,122 +148,124 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5625                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6596                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6037                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8339                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8363                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7496                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5785                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5489                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      205                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       35                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64437                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      519.304127                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     318.318074                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     406.802576                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14872     23.08%     23.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11053     17.15%     40.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5024      7.80%     48.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3269      5.07%     53.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2580      4.00%     57.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1937      3.01%     60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4194      6.51%     66.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1317      2.04%     68.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20191     31.33%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64437                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5312                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        76.190700                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2898.366893                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5309     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1565                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6269                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7880                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6795                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       70                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        64393                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      519.603311                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     318.318586                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     407.156918                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14830     23.03%     23.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11097     17.23%     40.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4950      7.69%     47.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3246      5.04%     52.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2531      3.93%     56.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1970      3.06%     59.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4174      6.48%     66.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1358      2.11%     68.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20237     31.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64393                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5302                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        76.317050                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2899.726540                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5299     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5312                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5312                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.236446                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.912972                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.909399                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4665     87.82%     87.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              19      0.36%     88.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              18      0.34%     88.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             199      3.75%     92.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               5      0.09%     92.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              25      0.47%     92.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              40      0.75%     93.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               5      0.09%     93.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               6      0.11%     93.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              23      0.43%     94.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.11%     94.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.08%     94.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               9      0.17%     94.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.02%     94.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              20      0.38%     94.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              24      0.45%     95.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.04%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              32      0.60%     96.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.06%     96.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103           171      3.22%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             4      0.08%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.04%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             3      0.06%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.04%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             4      0.08%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.04%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             8      0.15%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             3      0.06%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             2      0.04%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5312                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2653633250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10242320750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2023650000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6556.55                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5302                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5302                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.283855                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.921998                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.156721                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4666     88.00%     88.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              22      0.41%     88.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              20      0.38%     88.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             187      3.53%     92.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               6      0.11%     92.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              25      0.47%     92.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              43      0.81%     93.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.11%     93.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               8      0.15%     93.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              18      0.34%     94.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.02%     94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               3      0.06%     94.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               6      0.11%     94.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.06%     94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              18      0.34%     94.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              25      0.47%     95.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.04%     95.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              27      0.51%     95.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.04%     95.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103           172      3.24%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.04%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.13%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.04%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.06%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             7      0.13%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.04%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             3      0.06%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             8      0.15%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::212-215             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5302                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2636864500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10223958250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2023225000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6516.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25306.55                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25266.49                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.59                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.97                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.59                       # Average system read bandwidth in MiByte/s
@@ -273,71 +275,71 @@ system.physmem.busUtil                           0.14                       # Da
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     362859                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95554                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.65                       # Row buffer hit rate for reads
+system.physmem.avgWrQLen                        26.35                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     362818                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95583                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.66                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  80.88                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3644574.63                       # Average gap between requests
-system.physmem.pageHitRate                      87.67                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  238049280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  129888000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1577136600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                380058480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           124492945200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            67941192465                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1084023651750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1278782921775                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.912502                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1803110214250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     63646700000                       # Time in different power states
+system.physmem.avgGap                      3644923.65                       # Average gap between requests
+system.physmem.pageHitRate                      87.68                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  237542760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  129611625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1576816800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                380077920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           124493453760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            67952834145                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1084018111500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1278788448510                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.912661                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1803102997000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     63646960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     39278414500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     39293158000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  249094440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  135914625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1579757400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                385359120                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           124492945200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            68603580630                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1083442617750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1278889269165                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.968292                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1802146960250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     63646700000                       # Time in different power states
+system.physmem_1.actEnergy                  249268320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  136009500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1579414200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                385527600                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           124493453760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            68401366290                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1083624670500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1278869710170                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.955290                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1802449451000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     63646960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     40241682250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     39946717750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                15005157                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          13016352                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            370563                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9544476                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5200630                       # Number of BTB hits
+system.cpu.branchPred.lookups                15009028                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          13018563                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            370758                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9666577                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5199223                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             54.488376                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  807259                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              30802                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             53.785564                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  807911                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              31459                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9242284                       # DTB read hits
-system.cpu.dtb.read_misses                      17197                       # DTB read misses
+system.cpu.dtb.read_hits                      9243045                       # DTB read hits
+system.cpu.dtb.read_misses                      17179                       # DTB read misses
 system.cpu.dtb.read_acv                           211                       # DTB read access violations
-system.cpu.dtb.read_accesses                   765766                       # DTB read accesses
-system.cpu.dtb.write_hits                     6387071                       # DTB write hits
-system.cpu.dtb.write_misses                      2294                       # DTB write misses
-system.cpu.dtb.write_acv                          160                       # DTB write access violations
-system.cpu.dtb.write_accesses                  298411                       # DTB write accesses
-system.cpu.dtb.data_hits                     15629355                       # DTB hits
-system.cpu.dtb.data_misses                      19491                       # DTB misses
-system.cpu.dtb.data_acv                           371                       # DTB access violations
-system.cpu.dtb.data_accesses                  1064177                       # DTB accesses
-system.cpu.itb.fetch_hits                     4015320                       # ITB hits
-system.cpu.itb.fetch_misses                      6841                       # ITB misses
-system.cpu.itb.fetch_acv                          659                       # ITB acv
-system.cpu.itb.fetch_accesses                 4022161                       # ITB accesses
+system.cpu.dtb.read_accesses                   765860                       # DTB read accesses
+system.cpu.dtb.write_hits                     6388437                       # DTB write hits
+system.cpu.dtb.write_misses                      2336                       # DTB write misses
+system.cpu.dtb.write_acv                          159                       # DTB write access violations
+system.cpu.dtb.write_accesses                  298458                       # DTB write accesses
+system.cpu.dtb.data_hits                     15631482                       # DTB hits
+system.cpu.dtb.data_misses                      19515                       # DTB misses
+system.cpu.dtb.data_acv                           370                       # DTB access violations
+system.cpu.dtb.data_accesses                  1064318                       # DTB accesses
+system.cpu.itb.fetch_hits                     4012772                       # ITB hits
+system.cpu.itb.fetch_misses                      6839                       # ITB misses
+system.cpu.itb.fetch_acv                          666                       # ITB acv
+system.cpu.itb.fetch_accesses                 4019611                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -350,39 +352,39 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        223168437                       # number of cpu cycles simulated
+system.cpu.numCycles                        221706697                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56132533                       # Number of instructions committed
-system.cpu.committedOps                      56132533                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2504504                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      5489                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   3590815720                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               3.975741                       # CPI: cycles per instruction
-system.cpu.ipc                               0.251525                       # IPC: instructions per cycle
+system.cpu.committedInsts                    56145568                       # Number of instructions committed
+system.cpu.committedOps                      56145568                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       2506376                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      5532                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   3590390516                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               3.948784                       # CPI: cycles per instruction
+system.cpu.ipc                               0.253243                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211546                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74811     40.93%     40.93% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     41.01% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211538                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74805     40.93%     40.93% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     133      0.07%     41.01% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1904      1.04%     42.05% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105910     57.95%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182756                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73444     49.32%     49.32% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  105906     57.95%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182748                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73438     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      133      0.09%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1904      1.28%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73444     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148923                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1837436986000     96.40%     96.40% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                81017000      0.00%     96.41% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               682412000      0.04%     96.44% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             67836062500      3.56%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1906036477500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981727                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31                    73439     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148914                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1837271257000     96.39%     96.39% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                83690500      0.00%     96.40% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               707098000      0.04%     96.43% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             67985555000      3.57%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1906047600500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981726                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.693457                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814873                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.693436                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814860                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -421,112 +423,112 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4174      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175591     91.23%     93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175581     91.22%     93.43% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6807      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5129      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5130      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192481                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5873                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1740                      
+system.cpu.kern.callpal::total                 192472                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5876                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2094                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1906                      
+system.cpu.kern.mode_good::user                  1737                      
 system.cpu.kern.mode_good::idle                   169                      
-system.cpu.kern.mode_switch_good::kernel     0.325047                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.324370                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080630                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.393243                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        38636753000      2.03%      2.03% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           4528404000      0.24%      2.26% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1862871310500     97.74%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080707                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392706                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        38721238500      2.03%      2.03% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           4530290000      0.24%      2.27% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1862796062000     97.73%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
-system.cpu.tickCycles                        86394668                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       136773769                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1395457                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.977331                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            13772866                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1395969                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              9.866169                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         121717500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.977331                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999956                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999956                       # Average percentage of cache occupancy
+system.cpu.tickCycles                        84511190                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       137195507                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1395430                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.976766                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            13774781                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1395942                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              9.867732                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         123981500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.976766                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999955                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          224                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63663599                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63663599                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7815159                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7815159                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5575814                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5575814                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182834                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182834                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199026                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199026                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13390973                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13390973                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13390973                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13390973                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1201770                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1201770                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       575091                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       575091                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17213                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17213                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1776861                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1776861                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1776861                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1776861                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  46961675000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  46961675000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  33993891500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  33993891500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    235176000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    235176000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  80955566500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  80955566500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  80955566500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  80955566500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9016929                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9016929                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6150905                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6150905                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200047                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200047                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199026                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199026                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15167834                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15167834                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15167834                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15167834                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133279                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.133279                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093497                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.093497                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.117147                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.117147                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.117147                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.117147                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39077.090458                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 39077.090458                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59110.456432                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59110.456432                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13662.696799                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13662.696799                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45561.001395                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45561.001395                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45561.001395                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45561.001395                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63671171                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63671171                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7816045                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7816045                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5576846                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5576846                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       182827                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       182827                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199029                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199029                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13392891                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13392891                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13392891                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13392891                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1201631                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1201631                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       575205                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       575205                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17224                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17224                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1776836                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1776836                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1776836                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1776836                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  46974936500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  46974936500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  33956179000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  33956179000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    234952500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    234952500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  80931115500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  80931115500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  80931115500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  80931115500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9017676                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9017676                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6152051                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152051                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200051                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200051                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199029                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199029                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15169727                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15169727                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15169727                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15169727                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.133253                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.133253                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.093498                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.093498                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086098                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086098                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.117130                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.117130                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.117130                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.117130                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45547.881459                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45547.881459                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -535,129 +537,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       838295                       # number of writebacks
-system.cpu.dcache.writebacks::total            838295                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127341                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       127341                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270722                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       270722                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       838232                       # number of writebacks
+system.cpu.dcache.writebacks::total            838232                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       127276                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       127276                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       270800                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       270800                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       398063                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       398063                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       398063                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       398063                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074429                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1074429                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304369                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304369                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17210                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17210                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1378798                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1378798                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1378798                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1378798                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9622                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total         9622                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16552                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        16552                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43805969000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43805969000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17294633000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17294633000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    217700500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    217700500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61100602000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  61100602000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61100602000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  61100602000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1450655500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1450655500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2042490500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2042490500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3493146000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3493146000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119157                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119157                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049484                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049484                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086030                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086030                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090903                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090903                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090903                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090903                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40771.394853                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40771.394853                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56821.269577                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56821.269577                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12649.651365                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.651365                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44314.397033                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44314.397033                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44314.397033                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44314.397033                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209329.797980                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209329.797980                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212272.968198                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212272.968198                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211040.720155                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211040.720155                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       398076                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       398076                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       398076                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       398076                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1074355                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1074355                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304405                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304405                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17221                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17221                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1378760                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1378760                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1378760                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1378760                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6934                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total         6934                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9624                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total         9624                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16558                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        16558                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43817588500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43817588500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17272399000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17272399000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    217466000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    217466000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61089987500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  61089987500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61089987500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  61089987500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1530266500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1530266500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2162508500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2162508500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3692775000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3692775000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119139                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119139                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049480                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049480                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086083                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086083                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090889                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090889                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090889                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090889                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40785.018453                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40785.018453                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.508845                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.508845                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.919797                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.919797                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.919797                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.919797                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220690.294202                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220690.294202                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224699.553200                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224699.553200                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223020.594275                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223020.594275                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1459812                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.108213                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18945545                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1460323                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             12.973531                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       50089035500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.108213                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.992399                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.992399                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1460396                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.105648                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            18947784                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1460907                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             12.969877                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       50119711500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.105648                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.992394                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.992394                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          405                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          406                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          21866544                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         21866544                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     18945548                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18945548                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      18945548                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18945548                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     18945548                       # number of overall hits
-system.cpu.icache.overall_hits::total        18945548                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1460498                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1460498                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1460498                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1460498                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1460498                       # number of overall misses
-system.cpu.icache.overall_misses::total       1460498                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  20983654500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  20983654500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  20983654500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  20983654500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  20983654500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  20983654500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20406046                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20406046                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20406046                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20406046                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20406046                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20406046                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071572                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.071572                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.071572                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.071572                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.071572                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.071572                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14367.465412                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14367.465412                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14367.465412                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14367.465412                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14367.465412                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14367.465412                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          21869953                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         21869953                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     18947787                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18947787                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18947787                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18947787                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18947787                       # number of overall hits
+system.cpu.icache.overall_hits::total        18947787                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1461083                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1461083                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1461083                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1461083                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1461083                       # number of overall misses
+system.cpu.icache.overall_misses::total       1461083                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  21009217000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  21009217000                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst     20408870                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071591                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.071591                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.071591                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.071591                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.071591                       # miss rate for overall accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.208436                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14379.208436                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.208436                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14379.208436                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.208436                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14379.208436                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -666,141 +668,147 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1460498                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1460498                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1460498                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1460498                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1460498                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1460498                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19523156500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  19523156500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19523156500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  19523156500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19523156500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  19523156500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071572                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071572                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total     0.071572                       # mshr miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13367.465412                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13367.465412                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13367.465412                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13367.465412                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13367.465412                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13367.465412                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.208436                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.208436                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.208436                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           339330                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65261.345003                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4998363                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           404492                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.357137                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       9675364000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53948.276768                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5807.945434                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5505.122802                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.total_refs            4999517                       # Total number of references to valid blocks.
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+system.cpu.l2cache.tags.warmup_cycle       9687465000                       # Cycle when the warmup percentage was hit.
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          223                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          863                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         5644                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2903                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55529                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         46387191                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        46387191                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       838295                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       838295                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         46396433                       # Number of tag accesses
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 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187729                       # number of ReadExReq hits
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 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       404000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       404000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14861542500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2151733500                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.Writeback_accesses::writebacks       838295                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       838295                       # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.809524                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23764.705882                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23764.705882                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127402.850407                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127402.850407                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131083.368870                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131083.368870                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123708.541218                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123708.541218                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131083.368870                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124816.826374                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 125070.657444                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131083.368870                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124816.826374                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 125070.657444                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14837528000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14837528000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2141943000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2141943000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33680651000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  33680651000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2141943000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  48518179000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  50660122000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2141943000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  48518179000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  50660122000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       838232                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       838232                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1459802                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1459802                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           22                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           22                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.ReadExReq_accesses::total       304414                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1461021                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1091545                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1091545                       # number of ReadSharedReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::cpu.data      1395959                       # number of overall (read+write) accesses
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+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.818182                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.818182                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383225                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383225                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.011173                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.011173                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.249378                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.249378                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.011173                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.278565                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.141825                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.011173                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.278565                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.141825                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -809,132 +817,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76630                       # number of writebacks
-system.cpu.l2cache.writebacks::total            76630                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          317                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          317                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           17                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           17                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116650                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116650                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16415                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16415                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       272186                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       272186                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16415                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388836                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16415                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388836                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       405251                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9622                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9622                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16552                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16552                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1214500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1214500                       # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  30951837500                       # number of ReadSharedReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44646880000                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1364010000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1364010000                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3295846500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3295846500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.809524                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809524                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383239                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383239                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.011240                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.011240                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.249344                       # mshr miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278538                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.141874                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71441.176471                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71441.176471                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117402.850407                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117402.850407                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121083.368870                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121083.368870                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113715.758709                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113715.758709                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121083.368870                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114821.878633                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115075.505057                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121083.368870                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114821.878633                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115075.505057                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196826.839827                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196826.839827                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200772.864269                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200772.864269                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199120.740696                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199120.740696                       # average overall mshr uncacheable latency
+system.cpu.l2cache.writebacks::writebacks        76662                       # number of writebacks
+system.cpu.l2cache.writebacks::total            76662                       # number of writebacks
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5711775                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2855459                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1981                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1240                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1240                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5712890                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2856017                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1979                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1248                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1248                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2559171                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9622                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9622                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       956450                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2277896                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           21                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       304379                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304379                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1460498                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091781                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq           6934                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2559702                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9624                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9624                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       956425                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1459802                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       818923                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           22                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           22                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       304414                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304414                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1461083                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1091718                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::BadAddressError           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4380147                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219373                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8599520                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93467712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143047028                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          236514740                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      422969                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      6151080                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000871                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.029504                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4381906                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4219310                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8601216                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    186932672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143041565                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          329974237                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      423215                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3296619                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001032                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.032108                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            6145721     99.91%     99.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               5359      0.09%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3293217     99.90%     99.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3402      0.10%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6151080                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3707269500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       284383                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3296619                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5168164000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2190955582                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2191892463                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2105716998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2105680997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -948,81 +953,81 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51174                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51174                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5100                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7107                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7107                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               51176                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51176                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5110                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33104                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116554                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20400                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116566                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20440                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        44340                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        44381                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2705948                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              4711000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2705989                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              5423500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               386000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              186500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14813500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy             2308500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5938000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              224500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy               98500                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy              142500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           215087245                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           215092991                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer30.occupancy               31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23482000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23492000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.290787                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.290814                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1748608829000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.290787                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.080674                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.080674                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1748612865000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.290814                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.080676                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.080676                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1036,14 +1041,14 @@ system.iocache.demand_misses::tsunami.ide          173                       # n
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21943883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21943883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5427163362                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5427163362                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21943883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21943883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21943883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21943883                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21944383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21944383                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5429292608                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5429292608                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21944383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21944383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21944383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21944383                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1060,19 +1065,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126843.254335                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126843.254335                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130611.363159                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130611.363159                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126843.254335                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126843.254335                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126843.254335                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126843.254335                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126846.144509                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126846.144509                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130662.606084                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130662.606084                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126846.144509                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126846.144509                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126846.144509                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126846.144509                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            77                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.833333                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1086,14 +1091,14 @@ system.iocache.demand_mshr_misses::tsunami.ide          173
 system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13293883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13293883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3349563362                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3349563362                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13293883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13293883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13293883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13293883                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13294383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13294383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3351692608                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3351692608                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     13294383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     13294383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     13294383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     13294383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1102,63 +1107,63 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76843.254335                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76843.254335                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80611.363159                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80611.363159                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76843.254335                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76843.254335                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76843.254335                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76843.254335                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76846.144509                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76846.144509                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80662.606084                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80662.606084                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76846.144509                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76846.144509                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76846.144509                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76846.144509                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295688                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9622                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9622                       # Transaction distribution
-system.membus.trans_dist::Writeback            118142                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262192                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              159                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             159                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            116508                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           116508                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        288774                       # Transaction distribution
+system.membus.trans_dist::ReadReq                6934                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295622                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9624                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9624                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       118174                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262081                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              178                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             178                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            116499                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           116499                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        288704                       # Transaction distribution
 system.membus.trans_dist::BadAddressError           16                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1149038                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33116                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1148839                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1182174                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1181987                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1306991                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44340                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30812800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30857140                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1306804                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44381                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30809792                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30854173                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33514868                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33511901                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              433                       # Total snoops (count)
-system.membus.snoop_fanout::samples            844052                       # Request fanout histogram
+system.membus.snoop_fanout::samples            843925                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  844052    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  843925    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              844052                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            29776500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              843925                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            29573500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1319401645                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1319381154                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               20500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               22500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2160603841                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2160247074                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           69882415                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           69858432                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index c3ff68c1f..4156232eb 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,123 +1,123 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.921764                       # Number of seconds simulated
-sim_ticks                                1921763645000                       # Number of ticks simulated
-final_tick                               1921763645000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.922762                       # Number of seconds simulated
+sim_ticks                                1922761887500                       # Number of ticks simulated
+final_tick                               1922761887500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133766                       # Simulator instruction rate (inst/s)
-host_op_rate                                   133766                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4532754153                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384052                       # Number of bytes of host memory used
-host_seconds                                   423.97                       # Real time elapsed on the host
-sim_insts                                    56713315                       # Number of instructions simulated
-sim_ops                                      56713315                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 132982                       # Simulator instruction rate (inst/s)
+host_op_rate                                   132982                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4507220686                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 384024                       # Number of bytes of host memory used
+host_seconds                                   426.60                       # Real time elapsed on the host
+sim_insts                                    56729467                       # Number of instructions simulated
+sim_ops                                      56729467                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           874240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24774144                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           869760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24778624                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst           103040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           514944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           515712                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26267328                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       874240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total             26268096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       869760                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu1.inst       103040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          977280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7875136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7875136                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13660                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            387096                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::total          972800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7882944                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7882944                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13590                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            387166                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.inst              1610                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8046                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8058                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                410427                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          123049                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123049                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              454915                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12891358                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               53617                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              267954                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               500                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13668345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         454915                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          53617                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             508533                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4097869                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4097869                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4097869                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             454915                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12891358                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              53617                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             267954                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              500                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17766214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        410427                       # Number of read requests accepted
-system.physmem.writeReqs                       123049                       # Number of write requests accepted
-system.physmem.readBursts                      410427                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     123049                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26259904                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7424                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7874176                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26267328                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7875136                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      116                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                410439                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          123171                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123171                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              452349                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12886996                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               53590                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              268214                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               499                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13661648                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         452349                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          53590                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             505939                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4099803                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4099803                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4099803                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             452349                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12886996                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              53590                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             268214                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              499                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17761450                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        410439                       # Number of read requests accepted
+system.physmem.writeReqs                       123171                       # Number of write requests accepted
+system.physmem.readBursts                      410439                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     123171                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26260800                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7881088                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26268096                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7882944                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          46661                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25500                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25969                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               26011                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25727                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25508                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25811                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25519                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25160                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25451                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25839                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25659                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25030                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26076                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25978                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25473                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25600                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8066                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8046                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8027                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7668                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7376                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7761                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7583                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6991                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7326                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         309493                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25497                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25956                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               26004                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25724                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25504                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25939                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25634                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25247                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25446                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25836                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25660                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25037                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              26054                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25864                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25329                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25594                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8072                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8040                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8032                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7672                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7388                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7843                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7702                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7083                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7329                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7600                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7532                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7413                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7962                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8267                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7722                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7538                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7420                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7961                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8153                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7615                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7694                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1921759329500                       # Total gap between requests
+system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1922757529500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  410427                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  410439                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 123049                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317921                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     38025                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29433                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     24818                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 123171                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    317968                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     37909                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29466                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     24871                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        87                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
@@ -158,199 +158,199 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4488                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5809                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8822                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6881                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6896                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      371                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      231                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       72                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65305                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      522.687084                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     319.252168                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     410.914363                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14928     22.86%     22.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11344     17.37%     40.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5465      8.37%     48.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2873      4.40%     53.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2572      3.94%     56.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1636      2.51%     59.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3782      5.79%     65.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1204      1.84%     67.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21501     32.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65305                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5548                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        73.956561                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2834.723442                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5545     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1967                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5831                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6890                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6805                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8579                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9709                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6829                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6926                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      325                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      174                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::39                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       45                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65327                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      522.630582                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     319.337054                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     410.684018                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14917     22.83%     22.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11339     17.36%     40.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5448      8.34%     48.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2879      4.41%     52.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2603      3.98%     56.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1650      2.53%     59.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3828      5.86%     65.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1203      1.84%     67.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21460     32.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65327                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5559                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        73.810757                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2831.423020                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5556     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5548                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5548                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.176280                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.947134                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       20.868875                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4772     86.01%     86.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             155      2.79%     88.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              19      0.34%     89.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             186      3.35%     92.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               8      0.14%     92.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              21      0.38%     93.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              41      0.74%     93.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               5      0.09%     93.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              18      0.32%     94.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              27      0.49%     94.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.02%     94.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.09%     94.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               9      0.16%     94.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.07%     95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              20      0.36%     95.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              24      0.43%     95.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.04%     95.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              29      0.52%     96.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103           158      2.85%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.04%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             3      0.05%     99.32% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5559                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5559                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.151826                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.921629                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       20.873132                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4760     85.63%     85.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             185      3.33%     88.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              26      0.47%     89.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             178      3.20%     92.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               6      0.11%     92.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              17      0.31%     93.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              45      0.81%     93.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               4      0.07%     93.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              15      0.27%     94.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              20      0.36%     94.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.02%     94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               5      0.09%     94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               9      0.16%     94.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.09%     94.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              23      0.41%     95.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              22      0.40%     95.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              34      0.61%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103           160      2.88%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.04%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             3      0.05%     99.32% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::132-135             1      0.02%     99.33% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::140-143             1      0.02%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             2      0.04%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.04%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.07%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             3      0.05%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             3      0.05%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183            14      0.25%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.04%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.04%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.05%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             3      0.05%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.05%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             3      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             2      0.04%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183            11      0.20%     99.91% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::188-191             2      0.04%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5548                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4465229000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               12158560250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2051555000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10882.55                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::220-223             1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::252-255             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5559                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4492977750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               12186571500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2051625000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10949.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29632.55                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29699.80                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.66                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.10                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.67                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.66                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        4.10                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         2.26                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.31                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     369445                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98595                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.04                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3602335.12                       # Average gap between requests
+system.physmem.avgWrQLen                        25.48                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     369433                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98707                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.03                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.14                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3603301.16                       # Average gap between requests
 system.physmem.pageHitRate                      87.75                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  245919240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  134182125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1600599000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                398636640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           125520236400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63180018945                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1097637063000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1288716655350                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.590642                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1825809460500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     64171900000                       # Time in different power states
+system.physmem_0.actEnergy                  247242240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  134904000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1602939000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                400671360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           125585332080                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            63449600445                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1097998572000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1289419261125                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.608464                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1826410636250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     64205180000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31782207000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32144391250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  247786560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  135201000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1599826800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                398623680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           125520236400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            62993858085                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1097800353750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1288695886275                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.579840                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1826084104500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     64171900000                       # Time in different power states
+system.physmem_1.actEnergy                  246629880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134569875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1597596000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                397288800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           125585332080                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            62800369875                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1098568064250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1289329850760                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.561968                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1827364141250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     64205180000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31507549250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     31190872500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu0.branchPred.lookups               16172722                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         14147320                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           315974                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            10263532                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                5327857                       # Number of BTB hits
+system.cpu0.branchPred.lookups               16164803                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         14134057                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           313974                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            10204663                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                5324382                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            51.910561                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 805529                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             17788                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            52.175971                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 806868                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             17359                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9178933                       # DTB read hits
-system.cpu0.dtb.read_misses                     32423                       # DTB read misses
-system.cpu0.dtb.read_acv                          530                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  683199                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5878949                       # DTB write hits
-system.cpu0.dtb.write_misses                     7260                       # DTB write misses
-system.cpu0.dtb.write_acv                         384                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 235377                       # DTB write accesses
-system.cpu0.dtb.data_hits                    15057882                       # DTB hits
-system.cpu0.dtb.data_misses                     39683                       # DTB misses
-system.cpu0.dtb.data_acv                          914                       # DTB access violations
-system.cpu0.dtb.data_accesses                  918576                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1433805                       # ITB hits
-system.cpu0.itb.fetch_misses                    20098                       # ITB misses
-system.cpu0.itb.fetch_acv                         602                       # ITB acv
-system.cpu0.itb.fetch_accesses                1453903                       # ITB accesses
+system.cpu0.dtb.read_hits                     9175640                       # DTB read hits
+system.cpu0.dtb.read_misses                     32141                       # DTB read misses
+system.cpu0.dtb.read_acv                          535                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  683139                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5880520                       # DTB write hits
+system.cpu0.dtb.write_misses                     7287                       # DTB write misses
+system.cpu0.dtb.write_acv                         388                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 235457                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15056160                       # DTB hits
+system.cpu0.dtb.data_misses                     39428                       # DTB misses
+system.cpu0.dtb.data_acv                          923                       # DTB access violations
+system.cpu0.dtb.data_accesses                  918596                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1432352                       # ITB hits
+system.cpu0.itb.fetch_misses                    20066                       # ITB misses
+system.cpu0.itb.fetch_acv                         603                       # ITB acv
+system.cpu0.itb.fetch_accesses                1452418                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -363,256 +363,255 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       146988157                       # number of cpu cycles simulated
+system.cpu0.numCycles                       147492353                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          26434329                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      70323281                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   16172722                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6133386                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    112438747                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1062414                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                       847                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               30229                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       925731                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       462393                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          403                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  8125656                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               231201                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         140823886                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.499370                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.736005                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          26474453                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      70295181                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   16164803                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6131250                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    112661982                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1056864                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                       660                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               29689                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       929577                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       461648                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          350                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  8123308                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               229144                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples         141086791                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.498241                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.734215                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               127673480     90.66%     90.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  835079      0.59%     91.25% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1817427      1.29%     92.55% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  778983      0.55%     93.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2600412      1.85%     94.95% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  568090      0.40%     95.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  652333      0.46%     95.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  824353      0.59%     96.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 5073729      3.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               127943316     90.68%     90.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  834789      0.59%     91.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1813592      1.29%     92.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  779670      0.55%     93.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2595829      1.84%     94.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  572321      0.41%     95.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  651682      0.46%     95.82% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  825551      0.59%     96.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 5070041      3.59%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           140823886                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.110027                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.478428                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                21407057                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            108692435                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  8462793                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1765937                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                495663                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              515138                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                35957                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              61540375                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               109013                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                495663                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                22243524                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               77757616                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      19856258                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9307175                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             11163648                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              59419645                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               199110                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2023904                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                235068                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               7176378                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           39704161                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             72277966                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        72138515                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           129817                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             34987460                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4716693                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1464722                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        211632                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 12540163                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             9262921                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6150917                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1355884                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          997025                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  52994830                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1876718                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 52216371                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            52644                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6477091                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2861227                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1292062                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    140823886                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.370792                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.088351                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           141086791                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.109598                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.476602                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                21397284                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            108971969                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  8457985                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1766417                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                493135                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              516601                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                35757                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              61523411                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               108836                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                493135                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                22231623                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               77943277                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      19950150                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9304003                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             11164601                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              59421423                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents               199471                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2023547                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                224739                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               7186522                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           39708138                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             72284773                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        72145342                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           129802                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             34979364                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4728766                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1463848                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        211077                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 12544775                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9257817                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6153108                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1360057                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1005705                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  53010072                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1876155                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 52220775                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            51551                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6501427                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      2875305                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1291728                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    141086791                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.370132                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.087511                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          119350315     84.75%     84.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9307127      6.61%     91.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3871720      2.75%     94.11% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2724493      1.93%     96.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2821208      2.00%     98.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1374944      0.98%     99.02% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             898986      0.64%     99.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             361887      0.26%     99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             113206      0.08%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          119618317     84.78%     84.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            9300566      6.59%     91.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3865351      2.74%     94.12% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2730572      1.94%     96.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2821391      2.00%     98.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1375833      0.98%     99.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             902269      0.64%     99.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             360488      0.26%     99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             112004      0.08%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      140823886                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      141086791                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 180499     18.19%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     1      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                473486     47.73%     65.92% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               338115     34.08%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 182068     18.38%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     2      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                471621     47.60%     65.98% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               337015     34.02%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             3780      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             35829212     68.62%     68.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               56563      0.11%     68.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.73% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              28580      0.05%     68.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             35835166     68.62%     68.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               56519      0.11%     68.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.74% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              28571      0.05%     68.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.79% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9526937     18.25%     87.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5949680     11.39%     98.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            819736      1.57%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.80% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9523186     18.24%     87.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5952100     11.40%     98.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            819570      1.57%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              52216371                       # Type of FU issued
-system.cpu0.iq.rate                          0.355242                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     992101                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019000                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         245730281                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         61098362                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     50826597                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             571091                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            267903                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       262355                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              52896880                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 307812                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          579556                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              52220775                       # Type of FU issued
+system.cpu0.iq.rate                          0.354058                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     990706                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.018971                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         245999962                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         61137242                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     50831283                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             570635                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            267757                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       262095                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              52900144                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 307557                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          581308                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1070231                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2809                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        17956                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       496898                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1065241                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         3900                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        17685                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       500436                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18718                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       406168                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18736                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       408208                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                495663                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               74229287                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1063310                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           58247929                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           119878                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              9262921                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6150917                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1658630                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 39535                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               822687                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         17956                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        156887                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       351474                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              508361                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             51713827                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9234499                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           502543                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                493135                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               74418027                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1058724                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           58259516                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           116557                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9257817                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6153108                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1657861                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 39988                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               817674                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         17685                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        153306                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       351909                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              505215                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             51717296                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9230924                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           503478                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3376381                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    15134335                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 8213447                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5899836                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.351823                       # Inst execution rate
-system.cpu0.iew.wb_sent                      51204042                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     51088952                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 26321891                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 36458900                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3373289                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    15132335                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8216790                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5901411                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.350644                       # Inst execution rate
+system.cpu0.iew.wb_sent                      51207379                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     51093378                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 26334207                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 36473944                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.347572                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.721961                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.346414                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.722001                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        6803374                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         584656                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           464905                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    139620670                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.367725                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.257359                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        6824839                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         584427                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           463110                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    139882457                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.366962                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.256012                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    121488072     87.01%     87.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7189020      5.15%     92.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      3942453      2.82%     94.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2051651      1.47%     96.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1610967      1.15%     97.61% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       576073      0.41%     98.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       437348      0.31%     98.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       435843      0.31%     98.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1889243      1.35%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    121750983     87.04%     87.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7187616      5.14%     92.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      3944064      2.82%     95.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2051217      1.47%     96.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1611428      1.15%     97.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       577022      0.41%     98.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       437359      0.31%     98.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       434985      0.31%     98.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1887783      1.35%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    139620670                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            51342045                       # Number of instructions committed
-system.cpu0.commit.committedOps              51342045                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    139882457                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            51331530                       # Number of instructions committed
+system.cpu0.commit.committedOps              51331530                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      13846709                       # Number of memory references committed
-system.cpu0.commit.loads                      8192690                       # Number of loads committed
-system.cpu0.commit.membars                     198882                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7762297                       # Number of branches committed
-system.cpu0.commit.fp_insts                    259271                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 47551840                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              657143                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass      2951360      5.75%      5.75% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        33433980     65.12%     70.87% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55376      0.11%     70.98% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.98% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd         28117      0.05%     71.03% # Class of committed instruction
+system.cpu0.commit.refs                      13845248                       # Number of memory references committed
+system.cpu0.commit.loads                      8192576                       # Number of loads committed
+system.cpu0.commit.membars                     198790                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7761926                       # Number of branches committed
+system.cpu0.commit.fp_insts                    259003                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 47542487                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              656882                       # Number of function calls committed.
+system.cpu0.commit.op_class_0::No_OpClass      2950502      5.75%      5.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        33426097     65.12%     70.87% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55327      0.11%     70.97% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     70.97% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd         28109      0.05%     71.03% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     71.03% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     71.03% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatMult            0      0.00%     71.03% # Class of committed instruction
@@ -638,324 +637,326 @@ system.cpu0.commit.op_class_0::SimdFloatMisc            0      0.00%     71.03%
 system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     71.03% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     71.03% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     71.03% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead        8391572     16.34%     87.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite       5660021     11.02%     98.40% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess       819736      1.60%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead        8391366     16.35%     87.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite       5658677     11.02%     98.40% # Class of committed instruction
+system.cpu0.commit.op_class_0::IprAccess       819569      1.60%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         51342045                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1889243                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   195675599                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  117488366                       # The number of ROB writes
-system.cpu0.timesIdled                         519286                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        6164271                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3696539134                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   48394452                       # Number of Instructions Simulated
-system.cpu0.committedOps                     48394452                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              3.037294                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        3.037294                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.329240                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.329240                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                67992315                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               36972661                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   128885                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  130381                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1712039                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                819549                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          1282830                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.258957                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           10531989                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1283342                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.206689                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         36097500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.258957                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988787                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.988787                       # Average percentage of cache occupancy
+system.cpu0.commit.op_class_0::total         51331530                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1887783                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   195950193                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  117511428                       # The number of ROB writes
+system.cpu0.timesIdled                         525574                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        6405562                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3698031423                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   48384795                       # Number of Instructions Simulated
+system.cpu0.committedOps                     48384795                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              3.048320                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        3.048320                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.328050                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.328050                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                67995096                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               36974255                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   128760                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  130249                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1711265                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                819270                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          1282737                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.160384                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10524244                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1283249                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             8.201249                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         36569500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.160384                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988595                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988595                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          219                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          218                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         56925383                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        56925383                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6490454                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6490454                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3680062                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3680062                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       162917                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       162917                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       187619                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       187619                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10170516                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10170516                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10170516                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10170516                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1594902                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1594902                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1768783                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1768783                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20957                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        20957                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2842                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         2842                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3363685                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3363685                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3363685                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3363685                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54779472000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  54779472000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114120076576                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 114120076576                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    388638000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    388638000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44723000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     44723000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 168899548576                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 168899548576                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 168899548576                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 168899548576                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8085356                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8085356                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5448845                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5448845                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183874                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       183874                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       190461                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       190461                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13534201                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     13534201                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13534201                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     13534201                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197258                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.197258                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.324616                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.324616                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.113975                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.113975                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.014922                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.014922                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248532                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.248532                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248532                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.248532                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34346.606876                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 34346.606876                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64518.980890                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 64518.980890                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18544.543589                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18544.543589                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15736.453202                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15736.453202                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50212.653259                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 50212.653259                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50212.653259                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 50212.653259                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      6977235                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        18493                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           119566                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            125                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    58.354674                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   147.944000                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         56891628                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        56891628                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6483780                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6483780                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3678701                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3678701                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       162607                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       162607                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       187520                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       187520                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10162481                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10162481                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10162481                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10162481                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1594725                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1594725                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1768883                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1768883                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21044                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21044                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2856                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         2856                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3363608                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3363608                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3363608                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3363608                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54837998000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  54837998000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114303059042                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 114303059042                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    389087500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    389087500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     45510000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     45510000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 169141057042                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 169141057042                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 169141057042                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 169141057042                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8078505                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8078505                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5447584                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5447584                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183651                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       183651                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       190376                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       190376                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13526089                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13526089                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13526089                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     13526089                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.197403                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.197403                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.324710                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.324710                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.114587                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.114587                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.015002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.015002                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248676                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.248676                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248676                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.248676                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34387.118782                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 34387.118782                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64618.778654                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 64618.778654                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50285.603151                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 50285.603151                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50285.603151                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 50285.603151                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      6995611                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        14546                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           119540                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            103                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    58.521089                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   141.223301                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       756224                       # number of writebacks
-system.cpu0.dcache.writebacks::total           756224                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       579464                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       579464                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1502811                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1502811                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5193                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5193                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      2082275                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      2082275                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      2082275                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      2082275                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1015438                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1015438                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       265972                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       265972                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15764                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15764                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2841                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         2841                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1281410                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1281410                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1281410                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1281410                       # number of overall MSHR misses
+system.cpu0.dcache.writebacks::writebacks       756067                       # number of writebacks
+system.cpu0.dcache.writebacks::total           756067                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       579442                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       579442                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1502906                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1502906                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5209                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5209                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2082348                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2082348                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2082348                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2082348                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1015283                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1015283                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       265977                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       265977                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        15835                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        15835                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2856                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         2856                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1281260                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1281260                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1281260                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1281260                       # number of overall MSHR misses
 system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7045                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7045                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10125                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10125                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17170                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17170                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43462270000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43462270000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  18192812239                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18192812239                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    186019000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    186019000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     41882000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     41882000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61655082239                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  61655082239                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  61655082239                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  61655082239                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1482526500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1482526500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2174117500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2174117500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3656644000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3656644000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.125590                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.125590                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048813                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048813                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.085733                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.085733                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.014916                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.014916                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094679                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.094679                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094679                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.094679                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42801.500436                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42801.500436                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68401.231103                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68401.231103                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11800.241056                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11800.241056                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14741.992256                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14741.992256                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48115.031285                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48115.031285                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48115.031285                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48115.031285                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210436.692690                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210436.692690                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214727.654321                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214727.654321                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212967.035527                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212967.035527                       # average overall mshr uncacheable latency
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10126                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10126                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17171                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17171                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43466083500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43466083500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  18236016784                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18236016784                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    187455000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    187455000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     42654000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     42654000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61702100284                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  61702100284                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  61702100284                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  61702100284                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1563410000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1563410000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2299016000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2299016000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3862426000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3862426000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.125677                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.125677                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048825                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.048825                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086223                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086223                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.015002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.015002                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094725                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.094725                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094725                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.094725                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.790900                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.790900                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.382401                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.382401                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48157.360945                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48157.360945                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48157.360945                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48157.360945                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221917.672108                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221917.672108                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224938.908625                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224938.908625                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           909478                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.072720                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            7170024                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           909987                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             7.879260                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      42291813500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.072720                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992330                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.992330                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           908501                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.069795                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            7168696                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           909010                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             7.886267                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      42372449500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.069795                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992324                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.992324                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          424                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          418                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          9035950                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         9035950                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      7170024                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7170024                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      7170024                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7170024                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      7170024                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7170024                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       955631                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       955631                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       955631                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        955631                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       955631                       # number of overall misses
-system.cpu0.icache.overall_misses::total       955631                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14538250986                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14538250986                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14538250986                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14538250986                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14538250986                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14538250986                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      8125655                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      8125655                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      8125655                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      8125655                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      8125655                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      8125655                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117607                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.117607                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117607                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.117607                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117607                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.117607                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15213.247567                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 15213.247567                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15213.247567                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 15213.247567                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15213.247567                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 15213.247567                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         8860                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses          9032627                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         9032627                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      7168696                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        7168696                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      7168696                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         7168696                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      7168696                       # number of overall hits
+system.cpu0.icache.overall_hits::total        7168696                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       954611                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       954611                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       954611                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        954611                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       954611                       # number of overall misses
+system.cpu0.icache.overall_misses::total       954611                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14636609987                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14636609987                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14636609987                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14636609987                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14636609987                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14636609987                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      8123307                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      8123307                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      8123307                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      8123307                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      8123307                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      8123307                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.117515                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.117515                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117515                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.117515                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117515                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.117515                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15332.538581                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 15332.538581                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15332.538581                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 15332.538581                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15332.538581                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 15332.538581                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         8572                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              285                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              278                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    31.087719                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    30.834532                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        45336                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        45336                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        45336                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        45336                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        45336                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        45336                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       910295                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       910295                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       910295                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       910295                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       910295                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       910295                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12844771491                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  12844771491                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12844771491                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  12844771491                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12844771491                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  12844771491                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.112027                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.112027                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.112027                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.112027                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.112027                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.112027                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14110.559204                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14110.559204                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14110.559204                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 14110.559204                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14110.559204                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 14110.559204                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       908501                       # number of writebacks
+system.cpu0.icache.writebacks::total           908501                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        45291                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        45291                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        45291                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        45291                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        45291                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        45291                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       909320                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       909320                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       909320                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       909320                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       909320                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       909320                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12934939493                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12934939493                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12934939493                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12934939493                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12934939493                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12934939493                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.111940                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.111940                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.111940                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14224.848780                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 14224.848780                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 14224.848780                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                3566695                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          3123821                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect            62988                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             1777720                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                 839763                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3578846                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          3133511                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect            63586                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2063930                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                 845641                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            47.238204                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 169438                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              5003                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            40.972368                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 169933                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              4992                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1880373                       # DTB read hits
-system.cpu1.dtb.read_misses                      9576                       # DTB read misses
-system.cpu1.dtb.read_acv                            6                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  286028                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1172828                       # DTB write hits
-system.cpu1.dtb.write_misses                     2034                       # DTB write misses
+system.cpu1.dtb.read_hits                     1885255                       # DTB read hits
+system.cpu1.dtb.read_misses                      9531                       # DTB read misses
+system.cpu1.dtb.read_acv                            5                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  285831                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1175917                       # DTB write hits
+system.cpu1.dtb.write_misses                     2028                       # DTB write misses
 system.cpu1.dtb.write_acv                          35                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 108538                       # DTB write accesses
-system.cpu1.dtb.data_hits                     3053201                       # DTB hits
-system.cpu1.dtb.data_misses                     11610                       # DTB misses
-system.cpu1.dtb.data_acv                           41                       # DTB access violations
-system.cpu1.dtb.data_accesses                  394566                       # DTB accesses
-system.cpu1.itb.fetch_hits                     516269                       # ITB hits
-system.cpu1.itb.fetch_misses                     4737                       # ITB misses
-system.cpu1.itb.fetch_acv                          64                       # ITB acv
-system.cpu1.itb.fetch_accesses                 521006                       # ITB accesses
+system.cpu1.dtb.write_accesses                 108552                       # DTB write accesses
+system.cpu1.dtb.data_hits                     3061172                       # DTB hits
+system.cpu1.dtb.data_misses                     11559                       # DTB misses
+system.cpu1.dtb.data_acv                           40                       # DTB access violations
+system.cpu1.dtb.data_accesses                  394383                       # DTB accesses
+system.cpu1.itb.fetch_hits                     516958                       # ITB hits
+system.cpu1.itb.fetch_misses                     4674                       # ITB misses
+system.cpu1.itb.fetch_acv                          66                       # ITB acv
+system.cpu1.itb.fetch_accesses                 521632                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -968,255 +969,255 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        14959639                       # number of cpu cycles simulated
+system.cpu1.numCycles                        15151136                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           6140426                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      13703075                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    3566695                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1009201                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      7602996                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 256204                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                       312                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               25106                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       176452                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        62292                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           36                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1530550                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                50498                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          14135722                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.969393                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.379564                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           6180932                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      13745317                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    3578846                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1015574                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      7699604                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 257606                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                        14                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               25107                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       173727                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        62622                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1537985                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                51060                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          14270827                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.963176                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.372632                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                11742806     83.07%     83.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  150793      1.07%     84.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  240174      1.70%     85.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  177797      1.26%     87.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  306821      2.17%     89.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  121463      0.86%     90.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  138409      0.98%     91.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  186182      1.32%     92.42% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1071277      7.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                11867377     83.16%     83.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  153441      1.08%     84.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  242213      1.70%     85.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  178756      1.25%     87.18% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  307848      2.16%     89.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  121777      0.85%     90.19% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  138851      0.97%     91.17% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  186713      1.31%     92.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1073851      7.52%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            14135722                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.238421                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.916003                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 5035823                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              7049483                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  1732735                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               195750                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                121930                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              104865                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 6244                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              11127162                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                19879                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                121930                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 5174702                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 499846                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       5538858                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  1790125                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              1010259                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              10570144                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 4276                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 68050                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 20115                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents                516529                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands            6943229                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             12595828                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        12537363                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            52773                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              5938747                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1004482                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            436817                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         40607                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  1800852                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             1926573                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1243636                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           225182                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          130261                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                   9311043                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             502453                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                  9112092                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            20417                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1494632                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       673391                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        369352                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     14135722                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.644615                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.367603                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            14270827                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.236210                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.907214                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 5071818                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              7138589                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  1741534                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               196274                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                122611                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              106199                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 6268                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              11163667                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                19967                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                122611                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 5211151                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 520290                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       5613443                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  1798962                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              1004368                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              10604371                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 4257                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 67823                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 18974                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents                511038                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands            6965041                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             12634725                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        12576141                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            52884                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              5956129                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1008912                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            437815                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         40748                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  1803693                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             1932664                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1246799                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           224198                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          128085                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                   9340268                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             503829                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                  9138713                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            20420                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1499424                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       677663                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        370337                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     14270827                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.640377                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.363961                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           10331729     73.09%     73.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            1677616     11.87%     84.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             710014      5.02%     89.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             492260      3.48%     93.46% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             443396      3.14%     96.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             237464      1.68%     98.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             151784      1.07%     99.35% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              65612      0.46%     99.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              25847      0.18%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           10455091     73.26%     73.26% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1683189     11.79%     85.06% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             712225      4.99%     90.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             493511      3.46%     93.51% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             444759      3.12%     96.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             238311      1.67%     98.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             152079      1.07%     99.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              65820      0.46%     99.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              25842      0.18%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       14135722                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       14270827                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  23101      9.34%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                135152     54.66%     64.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                89008     36.00%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  22910      9.24%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.24% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                135436     54.62%     63.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                89607     36.14%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass             3518      0.04%      0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              5665609     62.18%     62.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               16110      0.18%     62.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.39% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              10836      0.12%     62.51% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.51% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.51% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.51% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             1960524     21.52%     84.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1194738     13.11%     97.16% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            258998      2.84%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              5683316     62.19%     62.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               16216      0.18%     62.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              10845      0.12%     62.52% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.52% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.52% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.52% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             1965659     21.51%     84.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1197875     13.11%     97.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            259525      2.84%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total               9112092                       # Type of FU issued
-system.cpu1.iq.rate                          0.609112                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     247261                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.027135                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          32423377                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         11214835                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses      8782259                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             204207                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes             97217                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses        94699                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses               9246642                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 109193                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           94025                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total               9138713                       # Type of FU issued
+system.cpu1.iq.rate                          0.603170                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     247953                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.027132                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          32611679                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         11249940                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses      8808383                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             204947                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes             97488                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses        94992                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses               9273516                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 109632                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           94173                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       261324                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          502                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         4031                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       123982                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       262201                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          474                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         4003                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       124065                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads          413                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        65647                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.cacheBlocked        65383                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                121930                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 296920                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               166801                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           10329862                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            27466                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              1926573                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1243636                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            455903                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  4091                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               161850                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          4031                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         28253                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect        94223                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              122476                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts              8997942                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              1896570                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           114150                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                122611                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 306675                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               177978                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           10362316                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            27137                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              1932664                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1246799                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            457137                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  4115                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               173001                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          4003                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         29001                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        94231                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              123232                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts              9024161                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              1901420                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           114552                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       516366                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     3077114                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1335580                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1180544                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.601481                       # Inst execution rate
-system.cpu1.iew.wb_sent                       8905860                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                      8876958                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  4235192                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  6022422                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       518219                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     3085060                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1341299                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1183640                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.595610                       # Inst execution rate
+system.cpu1.iew.wb_sent                       8932335                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                      8903375                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  4245423                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  6036438                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.593394                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.703237                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.587637                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.703299                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        1521482                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         133101                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           111980                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     13855601                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.631015                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.609308                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        1526496                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         133492                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           112683                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     13989586                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.626917                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.604217                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     10693520     77.18%     77.18% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      1462734     10.56%     87.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       528018      3.81%     91.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       318233      2.30%     93.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       242012      1.75%     95.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       100894      0.73%     96.32% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6        90931      0.66%     96.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       102553      0.74%     97.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       316706      2.29%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     10816267     77.32%     77.32% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1467149     10.49%     87.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       531154      3.80%     91.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       320114      2.29%     93.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       241905      1.73%     95.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       101551      0.73%     96.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6        91287      0.65%     97.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       103861      0.74%     97.74% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       316298      2.26%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     13855601                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts             8743092                       # Number of instructions committed
-system.cpu1.commit.committedOps               8743092                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     13989586                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts             8770307                       # Number of instructions committed
+system.cpu1.commit.committedOps               8770307                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       2784903                       # Number of memory references committed
-system.cpu1.commit.loads                      1665249                       # Number of loads committed
-system.cpu1.commit.membars                      42287                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1247450                       # Number of branches committed
-system.cpu1.commit.fp_insts                     93039                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  8096711                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              139604                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass       427747      4.89%      4.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu         5200103     59.48%     64.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          15945      0.18%     64.55% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.55% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd         10829      0.12%     64.68% # Class of committed instruction
+system.cpu1.commit.refs                       2793197                       # Number of memory references committed
+system.cpu1.commit.loads                      1670463                       # Number of loads committed
+system.cpu1.commit.membars                      42427                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1252873                       # Number of branches committed
+system.cpu1.commit.fp_insts                     93374                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  8120952                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              139980                       # Number of function calls committed.
+system.cpu1.commit.op_class_0::No_OpClass       429153      4.89%      4.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu         5216835     59.48%     64.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          16050      0.18%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     64.56% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd         10839      0.12%     64.68% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     64.68% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     64.68% # Class of committed instruction
 system.cpu1.commit.op_class_0::FloatMult            0      0.00%     64.68% # Class of committed instruction
@@ -1242,290 +1243,292 @@ system.cpu1.commit.op_class_0::SimdFloatMisc            0      0.00%     64.70%
 system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     64.70% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.70% # Class of committed instruction
 system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.70% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        1707536     19.53%     84.23% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       1120175     12.81%     97.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess       258998      2.96%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        1712890     19.53%     84.23% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       1123256     12.81%     97.04% # Class of committed instruction
+system.cpu1.commit.op_class_0::IprAccess       259525      2.96%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total          8743092                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               316706                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    23719092                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   20805392                       # The number of ROB writes
-system.cpu1.timesIdled                         122607                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         823917                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3827854089                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    8318863                       # Number of Instructions Simulated
-system.cpu1.committedOps                      8318863                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.798279                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.798279                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.556087                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.556087                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                11586341                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                6325577                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    52057                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   51356                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 501983                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                207801                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements            98586                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          486.617617                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            2459541                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs            98896                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            24.869975                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      61777830500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.617617                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.950425                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.950425                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          310                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          310                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.605469                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         11508888                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        11508888                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1514240                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1514240                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       887339                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        887339                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        31145                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        31145                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        29838                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        29838                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      2401579                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         2401579                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      2401579                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        2401579                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       186104                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       186104                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       193582                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       193582                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4934                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         4934                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2994                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         2994                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       379686                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        379686                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       379686                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       379686                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2502679500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2502679500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9084892318                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   9084892318                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     46731500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     46731500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     48320000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     48320000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  11587571818                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  11587571818                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  11587571818                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  11587571818                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1700344                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1700344                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1080921                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1080921                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        36079                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        36079                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        32832                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        32832                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      2781265                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      2781265                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      2781265                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      2781265                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.109451                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.109451                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.179090                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.179090                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.136755                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.136755                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.091192                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.091192                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.136516                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.136516                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.136516                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.136516                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13447.746959                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13447.746959                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46930.460053                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 46930.460053                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9471.321443                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9471.321443                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16138.944556                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16138.944556                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30518.828237                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 30518.828237                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30518.828237                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 30518.828237                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       537858                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets         1114                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs            16003                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              9                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    33.609823                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets   123.777778                       # average number of cycles each access was blocked
+system.cpu1.commit.op_class_0::total          8770307                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               316298                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    23885701                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   20870962                       # The number of ROB writes
+system.cpu1.timesIdled                         125875                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         880309                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3829642661                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    8344672                       # Number of Instructions Simulated
+system.cpu1.committedOps                      8344672                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.815666                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.815666                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.550762                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.550762                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                11618114                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                6343189                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    52190                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   51516                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 503472                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                210349                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements            98962                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          486.970751                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            2466427                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs            99271                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            24.845393                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     1048837181500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.970751                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.951115                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.951115                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          309                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.603516                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         11541624                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        11541624                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1517477                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1517477                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       889696                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        889696                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        32286                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        32286                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        29965                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        29965                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      2407173                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         2407173                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      2407173                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        2407173                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       186675                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       186675                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       194181                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       194181                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4996                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         4996                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2988                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         2988                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       380856                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        380856                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       380856                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       380856                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2524860000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2524860000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   9140210329                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   9140210329                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     47601500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     47601500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     47681500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     47681500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  11665070329                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  11665070329                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  11665070329                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  11665070329                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1704152                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1704152                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1083877                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1083877                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        37282                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        37282                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        32953                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        32953                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      2788029                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      2788029                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      2788029                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      2788029                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.109541                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.109541                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.179154                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.179154                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.134006                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.134006                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.090675                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.090675                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.136604                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.136604                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.136604                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.136604                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13525.431900                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13525.431900                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47070.569876                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 47070.569876                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9527.922338                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9527.922338                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15957.663989                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15957.663989                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30628.558639                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 30628.558639                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30628.558639                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 30628.558639                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       543818                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets         1735                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs            16052                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets             10                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    33.878520                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets   173.500000                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        63787                       # number of writebacks
-system.cpu1.dcache.writebacks::total            63787                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       112960                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       112960                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       158580                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       158580                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          454                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          454                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       271540                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       271540                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       271540                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       271540                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        73144                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        73144                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        35002                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        35002                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4480                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4480                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2993                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         2993                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       108146                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       108146                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       108146                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       108146                       # number of overall MSHR misses
+system.cpu1.dcache.writebacks::writebacks        64059                       # number of writebacks
+system.cpu1.dcache.writebacks::total            64059                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       113306                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       113306                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       159042                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       159042                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          473                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          473                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       272348                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       272348                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       272348                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       272348                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        73369                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        73369                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        35139                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        35139                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4523                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4523                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2988                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         2988                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       108508                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       108508                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       108508                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       108508                       # number of overall MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          150                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.ReadReq_mshr_uncacheable::total          150                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2930                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2930                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3080                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3080                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    925590000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total    925590000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1553309551                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1553309551                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     37834000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     37834000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     45327000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     45327000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2478899551                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2478899551                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2478899551                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2478899551                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     28469500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     28469500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    648479500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    648479500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    676949000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    676949000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.043017                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.043017                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032382                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032382                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.124172                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.124172                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.091161                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.091161                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.038884                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.038884                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.038884                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.038884                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12654.353057                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12654.353057                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44377.737015                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44377.737015                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8445.089286                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8445.089286                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15144.336786                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15144.336786                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22921.786760                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22921.786760                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22921.786760                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22921.786760                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189796.666667                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189796.666667                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221324.061433                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 221324.061433                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 219788.636364                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 219788.636364                       # average overall mshr uncacheable latency
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2931                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2931                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3081                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3081                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    931066500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total    931066500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1566203053                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1566203053                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     38495000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     38495000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     44693500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     44693500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2497269553                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   2497269553                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2497269553                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   2497269553                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     30161500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     30161500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    685230000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    685230000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    715391500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    715391500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.043053                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.043053                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032420                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032420                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.121319                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.121319                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.090675                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.090675                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.038919                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.038919                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.038919                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.038919                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12690.189317                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12690.189317                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44571.645551                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44571.645551                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8510.944064                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8510.944064                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14957.663989                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14957.663989                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23014.612314                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23014.612314                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23014.612314                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23014.612314                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201076.666667                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201076.666667                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 233787.103378                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 233787.103378                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 232194.579682                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 232194.579682                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           222828                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          467.348174                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1300089                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           223338                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             5.821172                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1895764140500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   467.348174                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.912789                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.912789                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           223833                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          467.351638                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1306354                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           224343                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             5.823021                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1896743746500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   467.351638                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.912796                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.912796                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          510                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          1753949                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         1753949                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1300089                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1300089                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1300089                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1300089                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1300089                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1300089                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       230461                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       230461                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       230461                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        230461                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       230461                       # number of overall misses
-system.cpu1.icache.overall_misses::total       230461                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3280299500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   3280299500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   3280299500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   3280299500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   3280299500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   3280299500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1530550                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1530550                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1530550                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1530550                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1530550                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1530550                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.150574                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.150574                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.150574                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.150574                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.150574                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.150574                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.642569                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14233.642569                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14233.642569                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14233.642569                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14233.642569                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14233.642569                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs          780                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses          1762389                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         1762389                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1306354                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1306354                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1306354                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1306354                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1306354                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1306354                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       231631                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       231631                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       231631                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        231631                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       231631                       # number of overall misses
+system.cpu1.icache.overall_misses::total       231631                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3331435000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   3331435000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   3331435000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   3331435000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   3331435000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   3331435000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1537985                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1537985                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1537985                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1537985                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1537985                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1537985                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.150607                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.150607                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.150607                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.150607                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.150607                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.150607                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14382.509250                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14382.509250                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14382.509250                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14382.509250                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14382.509250                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14382.509250                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs          764                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               42                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               38                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    18.571429                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    20.105263                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         7062                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         7062                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         7062                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         7062                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         7062                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         7062                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       223399                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       223399                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       223399                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       223399                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       223399                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       223399                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2948315500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   2948315500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2948315500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   2948315500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2948315500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   2948315500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.145960                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.145960                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.145960                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.145960                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.145960                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.145960                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13197.532218                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13197.532218                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13197.532218                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13197.532218                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13197.532218                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13197.532218                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks       223833                       # number of writebacks
+system.cpu1.icache.writebacks::total           223833                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         7227                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total         7227                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst         7227                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total         7227                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst         7227                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total         7227                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       224404                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       224404                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       224404                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       224404                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       224404                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       224404                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2997413500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   2997413500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2997413500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   2997413500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2997413500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   2997413500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.145908                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.145908                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.145908                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.145908                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.145908                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.145908                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.219568                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.219568                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.219568                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.219568                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.219568                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.219568                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1541,9 +1544,9 @@ system.disk2.dma_write_bytes                     8192                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.iobus.trans_dist::ReadReq                 7371                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7371                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               54607                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              54607                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11900                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               54609                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              54609                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1555,11 +1558,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        40500                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        40504                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83456                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83456                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  123956                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47600                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  123960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1571,49 +1574,49 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        73826                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        73842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661632                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661632                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2735458                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             11255000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2735474                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             12353500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               356000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               448000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              177000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13505000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14420500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy             2829000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5954500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              217500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy               87000                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy              131500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           215099741                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           215061495                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer30.occupancy               30500                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            27445000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            27447000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41952000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41696                       # number of replacements
-system.iocache.tags.tagsinuse                0.507802                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.507724                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41712                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1725999022000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.507802                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.031738                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.031738                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1726981783000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.507724                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.031733                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.031733                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1627,14 +1630,14 @@ system.iocache.demand_misses::tsunami.ide          176                       # n
 system.iocache.demand_misses::total               176                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          176                       # number of overall misses
 system.iocache.overall_misses::total              176                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     22249883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     22249883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5427997858                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5427997858                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     22249883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     22249883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     22249883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     22249883                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     22155383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     22155383                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5431231112                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5431231112                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     22155383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     22155383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     22155383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     22155383                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1651,19 +1654,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126419.789773                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126419.789773                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.446332                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130631.446332                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126419.789773                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126419.789773                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126419.789773                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126419.789773                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            31                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125882.857955                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125882.857955                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130709.258568                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130709.258568                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 125882.857955                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125882.857955                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 125882.857955                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125882.857955                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           126                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   17                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    15.500000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.411765                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1677,14 +1680,14 @@ system.iocache.demand_mshr_misses::tsunami.ide          176
 system.iocache.demand_mshr_misses::total          176                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          176                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          176                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13449883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13449883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3350397858                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3350397858                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13449883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13449883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13449883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13449883                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13355383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13355383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3353631112                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3353631112                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     13355383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     13355383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     13355383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     13355383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1693,195 +1696,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76419.789773                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76419.789773                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.446332                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.446332                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76419.789773                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76419.789773                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76419.789773                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76419.789773                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75882.857955                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75882.857955                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80709.258568                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80709.258568                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75882.857955                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75882.857955                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75882.857955                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   344948                       # number of replacements
-system.l2c.tags.tagsinuse                65190.787367                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3990905                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   410112                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.731256                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              11174884000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53006.163408                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5332.464187                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6575.010887                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      209.732945                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       67.415939                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.808810                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.081367                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.100327                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003200                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.001029                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.994732                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                   345304                       # number of replacements
+system.l2c.tags.tagsinuse                65190.216948                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3990482                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   410468                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.721786                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle              11177481000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   53120.456427                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5260.305215                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6531.960123                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      208.754945                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       68.740237                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.810554                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.080266                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.099670                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.003185                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.001049                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.994724                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65164                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          217                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1750                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         6246                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5661                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51290                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          216                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         1730                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6285                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6556                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        50377                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994324                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38374495                       # Number of tag accesses
-system.l2c.tags.data_accesses                38374495                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          820011                       # number of Writeback hits
-system.l2c.Writeback_hits::total               820011                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             181                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             256                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 437                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            49                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            26                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                75                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           155441                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            22735                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               178176                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        896343                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        221742                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1118085                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       736901                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        66152                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           803053                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              896343                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              892342                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              221742                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               88887                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2099314                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             896343                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             892342                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             221742                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              88887                       # number of overall hits
-system.l2c.overall_hits::total                2099314                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          2756                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1092                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3848                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          412                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          449                       # number of SCUpgradeReq misses
+system.l2c.tags.tag_accesses                 38372212                       # Number of tag accesses
+system.l2c.tags.data_accesses                38372212                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks       820126                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          820126                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks       859282                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          859282                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data             172                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             249                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 421                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            51                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            25                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                76                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           155330                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            22838                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               178168                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        895446                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        222750                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1118196                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       736882                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data        66420                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           803302                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.inst              895446                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              892212                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              222750                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               89258                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2099666                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             895446                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             892212                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             222750                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              89258                       # number of overall hits
+system.l2c.overall_hits::total                2099666                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data          2766                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1119                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3885                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          420                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          441                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total             861                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         114759                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           7322                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122081                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        13662                       # number of ReadCleanReq misses
+system.l2c.ReadExReq_misses::cpu0.data         114874                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           7330                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             122204                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        13592                       # number of ReadCleanReq misses
 system.l2c.ReadCleanReq_misses::cpu1.inst         1628                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           15290                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       272997                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data          824                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         273821                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst             13662                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            387756                       # number of demand (read+write) misses
+system.l2c.ReadCleanReq_misses::total           15220                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       272976                       # number of ReadSharedReq misses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1890,8 +1897,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           18                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           19                       # number of ReadCleanReq MSHR hits
@@ -1901,244 +1908,245 @@ system.l2c.demand_mshr_hits::total                 19                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            18                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks          355                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total          355                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2756                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1092                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3848                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          412                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          449                       # number of SCUpgradeReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks           11                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total           11                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2766                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1119                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3885                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          420                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          441                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total          861                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       114759                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         7322                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122081                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        13661                       # number of ReadCleanReq MSHR misses
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+system.l2c.ReadExReq_mshr_misses::cpu1.data         7330                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        122204                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        13591                       # number of ReadCleanReq MSHR misses
 system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1610                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        15271                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272997                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data          824                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       273821                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        13661                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       387756                       # number of demand (read+write) MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        15201                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu0.data       272976                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data          829                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       273805                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        13591                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       387850                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.inst         1610                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         8146                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           411173                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        13661                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       387756                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         8159                       # number of demand (read+write) MSHR misses
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+system.l2c.overall_mshr_misses::cpu0.data       387850                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.inst         1610                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         8146                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          411173                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         8159                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          411210                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7045                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::cpu1.data          150                       # number of ReadReq MSHR uncacheable
 system.l2c.ReadReq_mshr_uncacheable::total         7195                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10125                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2930                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        13055                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17170                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3080                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        20250                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    197825500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     78287000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    276112500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29369500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     32234000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     61603500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  14851696000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1085370000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  15937066000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1694708500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    202919000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1897627500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  31174991500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    107807500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  31282799000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1694708500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  46026687500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    202919000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1193177500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  49117492500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1694708500                       # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu1.data   1193177500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  49117492500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1394464000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     26594500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1421058500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2057508000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    612939000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2670447000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3451972000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    639533500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4091505500                       # number of overall MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_misses::total        20252                       # number of overall MSHR uncacheable misses
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     80293500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    278688500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29951500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     31656500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     61608000                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    201578500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1882100500                       # number of ReadCleanReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    108527000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  31282096000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1680522000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  46065656500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    201578500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1201944500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  49149701500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1680522000                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.data   1201944500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  49149701500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1475287500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     28274500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1503562000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2182363000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    649671500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2832034500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3657650500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    677946000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4335596500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.938372                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.810089                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.898016                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.893709                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.945263                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.919872                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.424719                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.243604                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.406588                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.015012                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007208                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013474                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.270321                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.012303                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254274                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015012                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.302911                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007208                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.083951                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.163781                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015012                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.302911                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007208                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.083951                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.163781                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71779.934688                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71691.391941                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71754.807692                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71285.194175                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71790.645880                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71548.780488                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129416.394357                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 148234.089047                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 130545.015195                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124054.498207                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126036.645963                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124263.473250                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114195.362953                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130834.344660                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114245.434061                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124054.498207                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118700.129721                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126036.645963                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 146474.036337                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 119456.998636                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124054.498207                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118700.129721                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126036.645963                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 146474.036337                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 119456.998636                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197936.692690                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177296.666667                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197506.393329                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203210.666667                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209194.197952                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204553.581003                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201046.709377                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 207640.746753                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 202049.654321                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941457                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.817982                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.902229                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.891720                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.946352                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.918890                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.425138                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.242973                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.406842                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.014951                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007175                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013412                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.270311                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.012327                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.254204                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014951                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.302993                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007175                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.083753                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.163770                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014951                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.302993                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007175                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.083753                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.163770                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71726.319595                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71754.691689                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129638.451695                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.998036                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123814.255641                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114198.936903                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114249.542558                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118771.835761                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 119524.577467                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118771.835761                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 119524.577467                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209409.155429                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208973.175817                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213013.249083                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 214082.386925                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7195                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296388                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13055                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13055                       # Transaction distribution
-system.membus.trans_dist::Writeback            123049                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262884                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            10279                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           5759                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            5112                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            122086                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           121678                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289268                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           75                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296301                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13057                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13057                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       123171                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           262771                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            10335                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           5768                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            5173                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            122191                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           121777                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289182                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           76                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40500                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1187062                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          150                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1227712                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40504                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1187227                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          152                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1227883                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124828                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124828                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1352540                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73826                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31484224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31558050                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1352711                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        73842                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31492800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31566642                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                34216290                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                            11781                       # Total snoops (count)
-system.membus.snoop_fanout::samples            875308                       # Request fanout histogram
+system.membus.pkt_size::total                34224882                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            11791                       # Total snoops (count)
+system.membus.snoop_fanout::samples            875399                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  875308    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  875399    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              875308                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            36599000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              875399                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            36670000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1356119148                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1357207403                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               92500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               98500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2187698407                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2187694355                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           69909650                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           69834733                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests      5063061                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2531463                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       338644                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1334                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1266                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5063738                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2531809                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       339719                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1340                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1272                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops           68                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadReq               7195                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2238892                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13055                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13055                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           943078                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1635745                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           10313                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          5834                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          16147                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           301580                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          301580                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1133694                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1098094                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           75                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2239104                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13057                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13057                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       943311                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       859282                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          775827                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           10329                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          5844                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          16173                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           301707                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          301707                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1133724                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1098277                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           76                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2554026                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3861302                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       573119                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       309440                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7297887                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     58240320                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    130381048                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     14295680                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     10315306                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              213232354                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          462162                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          5511701                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.123436                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.329209                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2546826                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3860959                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       579596                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       310532                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7297913                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    104800384                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    130368640                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     22732288                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     10357298                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              268258610                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          462469                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          2998699                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.119628                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.324813                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4831850     87.67%     87.67% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 679365     12.33%     99.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    482      0.01%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      4      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2640250     88.05%     88.05% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 358173     11.94%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    274      0.01%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            5511701                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3368234918                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            2998699                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4501023919                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           297385                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1366825726                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1365634171                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1954242307                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1954807358                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         335428339                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         338746615                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         167784154                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         168528157                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -2172,32 +2180,32 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6535                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    184475                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   65083     40.50%     40.50% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.08%     40.59% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1927      1.20%     41.79% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce                    6529                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    184433                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   65060     40.50%     40.50% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.08%     40.58% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1928      1.20%     41.78% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::30                    186      0.12%     41.90% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  93355     58.10%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              160682                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    64077     49.21%     49.21% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::31                  93335     58.10%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              160640                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    64056     49.21%     49.21% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     131      0.10%     49.31% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1927      1.48%     50.79% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1928      1.48%     50.79% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::30                     186      0.14%     50.93% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   63891     49.07%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               130212                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1864797723000     97.04%     97.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               61900500      0.00%     97.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              553477500      0.03%     97.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               85562000      0.00%     97.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            56264153500      2.93%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1921762816500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.984543                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::31                   63870     49.07%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               130171                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1865607975500     97.03%     97.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               63996500      0.00%     97.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              577908500      0.03%     97.06% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               88293000      0.00%     97.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            56422873000      2.93%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1922761046500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.984568                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.684388                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.810371                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.684309                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.810327                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.51%      3.51% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.33%     11.84% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.75%     13.60% # number of syscalls executed
@@ -2233,56 +2241,56 @@ system.cpu0.kern.callpal::wripir                  284      0.17%      0.17% # nu
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.17% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.17% # number of callpals executed
 system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.17% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3533      2.09%      2.26% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3530      2.09%      2.26% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      50      0.03%      2.29% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.29% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               153850     90.93%     93.22% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6345      3.75%     96.97% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               153808     90.93%     93.22% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6346      3.75%     96.97% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.97% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     3      0.00%     96.97% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.01%     96.98% # number of callpals executed
 system.cpu0.kern.callpal::whami                     2      0.00%     96.98% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4587      2.71%     99.69% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4586      2.71%     99.69% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 386      0.23%     99.92% # number of callpals executed
 system.cpu0.kern.callpal::imb                     138      0.08%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                169199                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7137                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1347                       # number of protection mode switches
+system.cpu0.kern.callpal::total                169154                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7135                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1348                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1346                      
-system.cpu0.kern.mode_good::user                 1347                      
+system.cpu0.kern.mode_good::kernel               1347                      
+system.cpu0.kern.mode_good::user                 1348                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.188595                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.188788                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.317421                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1919561135500     99.89%     99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2201673000      0.11%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.317694                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1920558467500     99.89%     99.89% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2202571000      0.11%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3534                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3531                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                    2548                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     55164                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   17245     36.53%     36.53% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1925      4.08%     40.61% # number of times we switched to this ipl
+system.cpu1.kern.inst.hwrei                     55289                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   17293     36.54%     36.54% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1926      4.07%     40.61% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count::30                    284      0.60%     41.21% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  27750     58.79%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               47204                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    16874     47.30%     47.30% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1925      5.40%     52.70% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     284      0.80%     53.49% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   16590     46.51%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                35673                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1874997277000     97.58%     97.58% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              538569500      0.03%     97.61% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              135298500      0.01%     97.62% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            45735704500      2.38%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1921406849500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.978487                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_count::31                  27821     58.79%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               47324                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    16920     47.31%     47.31% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1926      5.39%     52.69% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     284      0.79%     53.49% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   16636     46.51%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                35766                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1875921374000     97.58%     97.58% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              562894500      0.03%     97.61% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              139598000      0.01%     97.62% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            45773010000      2.38%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1922396876500                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.978431                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.597838                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.755720                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.597966                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.755769                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        11     11.22%     11.22% # number of syscalls executed
 system.cpu1.kern.syscall::6                         9      9.18%     20.41% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      1.02%     21.43% # number of syscalls executed
@@ -2301,32 +2309,32 @@ system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # nu
 system.cpu1.kern.callpal::wripir                  186      0.38%      0.38% # number of callpals executed
 system.cpu1.kern.callpal::wrmces                    1      0.00%      0.38% # number of callpals executed
 system.cpu1.kern.callpal::wrfen                     1      0.00%      0.39% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1056      2.16%      2.55% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1060      2.16%      2.55% # number of callpals executed
 system.cpu1.kern.callpal::tbi                       3      0.01%      2.56% # number of callpals executed
 system.cpu1.kern.callpal::wrent                     7      0.01%      2.57% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                42024     86.04%     88.61% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2414      4.94%     93.55% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.55% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     93.56% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     93.57% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2970      6.08%     99.65% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                42140     86.06%     88.63% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2415      4.93%     93.56% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.56% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     93.57% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.58% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2973      6.07%     99.65% # number of callpals executed
 system.cpu1.kern.callpal::callsys                 129      0.26%     99.91% # number of callpals executed
 system.cpu1.kern.callpal::imb                      42      0.09%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 48843                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1253                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                392                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2414                       # number of protection mode switches
+system.cpu1.kern.callpal::total                 48967                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1257                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                391                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2415                       # number of protection mode switches
 system.cpu1.kern.mode_good::kernel                600                      
-system.cpu1.kern.mode_good::user                  392                      
-system.cpu1.kern.mode_good::idle                  208                      
-system.cpu1.kern.mode_switch_good::kernel     0.478851                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::user                  391                      
+system.cpu1.kern.mode_good::idle                  209                      
+system.cpu1.kern.mode_switch_good::kernel     0.477327                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.086164                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.295639                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        4354098000      0.23%      0.23% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           702561000      0.04%      0.26% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1916032066000     99.74%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1057                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.086542                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.295348                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        4412319000      0.23%      0.23% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           702202000      0.04%      0.27% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1916962357500     99.73%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1061                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 3a598fe00..30a63d50f 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,112 +1,112 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.875745                       # Number of seconds simulated
-sim_ticks                                1875745192000                       # Number of ticks simulated
-final_tick                               1875745192000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.875760                       # Number of seconds simulated
+sim_ticks                                1875760362000                       # Number of ticks simulated
+final_tick                               1875760362000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131976                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131976                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4672432142                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378172                       # Number of bytes of host memory used
-host_seconds                                   401.45                       # Real time elapsed on the host
-sim_insts                                    52981683                       # Number of instructions simulated
-sim_ops                                      52981683                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 133605                       # Simulator instruction rate (inst/s)
+host_op_rate                                   133605                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4730094094                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 378388                       # Number of bytes of host memory used
+host_seconds                                   396.56                       # Real time elapsed on the host
+sim_insts                                    52982087                       # Number of instructions simulated
+sim_ops                                      52982087                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            962112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24881536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            958208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24881088                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25844608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       962112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          962112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7523648                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7523648                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15033                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388774                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25840256                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       958208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          958208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7524736                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7524736                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              14972                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388767                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                403822                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117557                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117557                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               512923                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13264881                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                403754                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117574                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117574                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               510837                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13264534                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               512                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13778315                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          512923                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             512923                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4011018                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4011018                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4011018                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              512923                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13264881                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13775883                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          510837                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             510837                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4011566                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4011566                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4011566                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              510837                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13264534                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17789333                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        403822                       # Number of read requests accepted
-system.physmem.writeReqs                       117557                       # Number of write requests accepted
-system.physmem.readBursts                      403822                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117557                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 25836864                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7744                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7522176                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  25844608                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7523648                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      121                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total               17787449                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        403754                       # Number of read requests accepted
+system.physmem.writeReqs                       117574                       # Number of write requests accepted
+system.physmem.readBursts                      403754                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117574                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 25832192                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8064                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7523264                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  25840256                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7524736                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      126                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          41890                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25633                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25421                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25565                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25492                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25387                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               24737                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24937                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25080                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24933                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25019                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25561                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24878                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              24487                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25242                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25745                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25584                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7946                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7515                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7960                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7517                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7330                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6676                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6762                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         303613                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25610                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25424                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25555                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               25501                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25379                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               24724                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24941                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25082                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               24938                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25020                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25562                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24881                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              24459                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25275                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25708                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25569                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7930                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7523                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7959                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7525                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7322                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6662                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6770                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                6719                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7146                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6702                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7407                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6970                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7148                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7861                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8061                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7814                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7147                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6703                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7409                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6974                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7145                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7893                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8063                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7807                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1875739913500                       # Total gap between requests
+system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1875755162500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  403822                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  403754                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117557                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    315399                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     36013                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28212                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     23984                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        76                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         8                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117574                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    315453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     35937                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     28173                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     23971                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        71                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -148,123 +148,126 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1915                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3287                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6026                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9376                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7819                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6510                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      355                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1903                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6002                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6433                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8316                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8577                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7869                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8334                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5661                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      396                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      237                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       51                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       71                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62141                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      536.822002                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     331.292900                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     411.615573                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13686     22.02%     22.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10474     16.86%     38.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4974      8.00%     46.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2759      4.44%     51.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2428      3.91%     55.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1656      2.66%     57.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3743      6.02%     63.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1149      1.85%     65.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21272     34.23%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62141                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5219                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        77.350259                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2906.647984                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5216     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5219                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5219                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.520406                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.103659                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.296995                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4441     85.09%     85.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             172      3.30%     88.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              18      0.34%     88.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             180      3.45%     92.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               4      0.08%     92.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              21      0.40%     92.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              36      0.69%     93.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               2      0.04%     93.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              12      0.23%     93.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              25      0.48%     94.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.06%     94.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.08%     94.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              11      0.21%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.08%     94.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              20      0.38%     94.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              29      0.56%     95.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.02%     95.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              29      0.56%     96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103           164      3.14%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             5      0.10%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             3      0.06%     99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.02%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             6      0.11%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             4      0.08%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             4      0.08%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183            11      0.21%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5219                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4201414500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11770808250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2018505000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10407.24                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::63                       78                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        62202                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      536.237934                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     330.496904                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     411.905259                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13738     22.09%     22.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10541     16.95%     39.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4957      7.97%     47.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2730      4.39%     51.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2467      3.97%     55.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1593      2.56%     57.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3726      5.99%     63.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1160      1.86%     65.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21290     34.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62202                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5203                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        77.574092                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2240.859567                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095           5198     99.90%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191            1      0.02%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-45055            1      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::73728-77823            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::122880-126975            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5203                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5203                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.592927                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.087485                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.896632                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4449     85.51%     85.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             153      2.94%     88.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              15      0.29%     88.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             183      3.52%     92.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               7      0.13%     92.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              21      0.40%     92.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              39      0.75%     93.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               1      0.02%     93.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              10      0.19%     93.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              17      0.33%     94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.12%     94.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.04%     94.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               8      0.15%     94.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.04%     94.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              19      0.37%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              27      0.52%     95.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              31      0.60%     95.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.06%     95.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103           162      3.11%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             7      0.13%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.04%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             4      0.08%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.06%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.04%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             4      0.08%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             4      0.08%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183            10      0.19%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             2      0.04%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             3      0.06%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5203                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4177241750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11745266750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2018140000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10349.24                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29157.24                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29099.24                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.77                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.01                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.78                       # Average system read bandwidth in MiByte/s
@@ -273,72 +276,72 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.06                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.95                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363834                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95259                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         2.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.14                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363742                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95234                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   90.12                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  81.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3597651.45                       # Average gap between requests
-system.physmem.pageHitRate                      88.07                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  233286480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  127289250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1577565600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                378594000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           122514138240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            61659983700                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1071355704750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1257846562020                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.587193                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1782093997750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     62635040000                       # Time in different power states
+system.physmem.writeRowHitRate                  81.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3598032.64                       # Average gap between requests
+system.physmem.pageHitRate                      88.06                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  232553160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  126889125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1577284800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                378496800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           122515155360                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            61473435525                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1071528687000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1257832501770                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.574130                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1782381530500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     62635560000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31009992250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     30737512000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  236499480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  129042375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1571255400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                383026320                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           122514138240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61488464715                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1071506168250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1257828594780                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.577609                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1782344410500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     62635040000                       # Time in different power states
+system.physmem_1.actEnergy                  237693960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  129694125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1570966800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                383233680                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           122515155360                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            61441070355                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1071557085750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1257834900030                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.575404                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1782427454500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     62635560000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30760024500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30691601750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17977610                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          15676073                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            370677                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11479744                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5859077                       # Number of BTB hits
+system.cpu.branchPred.lookups                17943789                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          15652252                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            367731                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11526734                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5853564                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             51.038394                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  912903                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              21206                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             50.782503                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  912127                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              21143                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     10250294                       # DTB read hits
-system.cpu.dtb.read_misses                      41452                       # DTB read misses
-system.cpu.dtb.read_acv                           531                       # DTB read access violations
-system.cpu.dtb.read_accesses                   965916                       # DTB read accesses
-system.cpu.dtb.write_hits                     6642949                       # DTB write hits
-system.cpu.dtb.write_misses                      9723                       # DTB write misses
-system.cpu.dtb.write_acv                          398                       # DTB write access violations
-system.cpu.dtb.write_accesses                  342082                       # DTB write accesses
-system.cpu.dtb.data_hits                     16893243                       # DTB hits
-system.cpu.dtb.data_misses                      51175                       # DTB misses
-system.cpu.dtb.data_acv                           929                       # DTB access violations
-system.cpu.dtb.data_accesses                  1307998                       # DTB accesses
-system.cpu.itb.fetch_hits                     1771116                       # ITB hits
-system.cpu.itb.fetch_misses                     27251                       # ITB misses
-system.cpu.itb.fetch_acv                          655                       # ITB acv
-system.cpu.itb.fetch_accesses                 1798367                       # ITB accesses
+system.cpu.dtb.read_hits                     10250861                       # DTB read hits
+system.cpu.dtb.read_misses                      41155                       # DTB read misses
+system.cpu.dtb.read_acv                           533                       # DTB read access violations
+system.cpu.dtb.read_accesses                   965519                       # DTB read accesses
+system.cpu.dtb.write_hits                     6643163                       # DTB write hits
+system.cpu.dtb.write_misses                      9679                       # DTB write misses
+system.cpu.dtb.write_acv                          405                       # DTB write access violations
+system.cpu.dtb.write_accesses                  341919                       # DTB write accesses
+system.cpu.dtb.data_hits                     16894024                       # DTB hits
+system.cpu.dtb.data_misses                      50834                       # DTB misses
+system.cpu.dtb.data_acv                           938                       # DTB access violations
+system.cpu.dtb.data_accesses                  1307438                       # DTB accesses
+system.cpu.itb.fetch_hits                     1771509                       # ITB hits
+system.cpu.itb.fetch_misses                     27218                       # ITB misses
+system.cpu.itb.fetch_acv                          651                       # ITB acv
+system.cpu.itb.fetch_accesses                 1798727                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -351,136 +354,136 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        153807945                       # number of cpu cycles simulated
+system.cpu.numCycles                        154312476                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29589963                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       78082078                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17977610                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6771980                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     115315004                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1233982                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                       2306                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                29550                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       1247451                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       470617                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          460                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8997640                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                271780                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       2                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          147272342                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.530188                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.786973                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29589684                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       78040473                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17943789                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6765691                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     115537778                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1228012                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1868                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                28793                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       1263154                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       470523                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          558                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8990852                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                270749                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          147506364                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.529065                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.785295                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                132738967     90.13%     90.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   930397      0.63%     90.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1956016      1.33%     92.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   907001      0.62%     92.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2772714      1.88%     94.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   615474      0.42%     95.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   727209      0.49%     95.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1009346      0.69%     96.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  5615218      3.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                132982346     90.15%     90.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   927735      0.63%     90.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1956667      1.33%     92.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   905254      0.61%     92.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2772061      1.88%     94.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   613974      0.42%     95.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   725766      0.49%     95.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1009556      0.68%     96.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  5613005      3.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            147272342                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.116883                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.507660                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 24002291                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             111345789                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                   9440793                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1908530                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 574938                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               581140                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42414                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               68062016                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                132549                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 574938                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24926396                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                78168566                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       21593766                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  10339140                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              11669534                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65637228                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                204564                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2092706                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 229144                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7400964                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            43743792                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79597549                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79416724                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            168373                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38181235                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5562549                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1689699                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         239435                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13568621                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10378795                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6951631                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1513940                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1098335                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58473138                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2139162                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57493462                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             57057                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7630612                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3411321                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1477941                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     147272342                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.390389                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.114131                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            147506364                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.116282                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.505730                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 23997501                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             111590886                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                   9436404                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1909016                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 572556                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               581578                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 41802                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               68051611                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                132447                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 572556                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 24921357                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                78408678                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       21682628                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  10334897                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              11586246                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65629261                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                204540                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2094496                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 230878                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7314004                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            43742271                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79592757                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79412100                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            168205                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38181578                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  5560685                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1689598                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         239417                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13566674                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10375081                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6952014                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1510108                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1095838                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58467931                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2138048                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57495227                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             57340                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7623887                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3407756                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1476848                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     147506364                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.389781                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.113625                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           123663895     83.97%     83.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10186331      6.92%     90.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4292878      2.91%     93.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3019293      2.05%     95.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3081041      2.09%     97.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1488323      1.01%     98.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1011420      0.69%     99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              404091      0.27%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              125070      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           123908569     84.00%     84.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10178941      6.90%     90.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4283785      2.90%     93.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3020720      2.05%     95.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3080791      2.09%     97.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1492273      1.01%     98.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1011784      0.69%     99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              404685      0.27%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              124816      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       147272342                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       147506364                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  210189     18.68%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 539111     47.92%     66.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                375615     33.39%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  210138     18.65%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 541379     48.04%     66.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                375311     33.31%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39049173     67.92%     67.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61879      0.11%     68.04% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass              7282      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39050505     67.92%     67.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61871      0.11%     68.04% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.04% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd               38553      0.07%     68.11% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.11% # Type of FU issued
@@ -508,97 +511,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.11% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.11% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.11% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10660314     18.54%     86.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6723536     11.69%     98.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             949085      1.65%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10660993     18.54%     86.66% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6723341     11.69%     98.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             949046      1.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57493462                       # Type of FU issued
-system.cpu.iq.rate                           0.373800                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1124915                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019566                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          262728196                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          67925320                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55850502                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              713041                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             336604                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       329051                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               58228243                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  382848                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           635438                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57495227                       # Type of FU issued
+system.cpu.iq.rate                           0.372590                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1126828                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.019599                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          262968198                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          67912529                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55849103                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              712787                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             336322                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       328951                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               58232052                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  382721                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           635480                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1285740                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3115                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        19427                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       573353                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1282102                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3336                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        19413                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       573763                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18203                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        457581                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18204                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        460620                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 574938                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                74485816                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1122121                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64302959                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            140159                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10378795                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6951631                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1891041                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  44126                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                874685                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          19427                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         179710                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       409314                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               589024                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56907888                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10319427                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            585573                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 572556                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                74664170                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1189821                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64295080                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            139940                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10375081                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6952014                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1890560                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  43853                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                943025                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          19413                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         177030                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       409389                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               586419                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56909008                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10319700                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            586218                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3690659                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16987198                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8973802                       # Number of branches executed
-system.cpu.iew.exec_stores                    6667771                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.369993                       # Inst execution rate
-system.cpu.iew.wb_sent                       56315493                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56179553                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28757989                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  39945326                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3689101                       # number of nop insts executed
+system.cpu.iew.exec_refs                     16987647                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8974026                       # Number of branches executed
+system.cpu.iew.exec_stores                    6667947                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.368791                       # Inst execution rate
+system.cpu.iew.wb_sent                       56315336                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56178054                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28756989                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  39942344                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.365258                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.719934                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.364054                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.719962                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8014233                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          661221                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            539644                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    145865842                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.385097                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.287358                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         8005033                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          661200                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            537292                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    146103821                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.384473                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.286210                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    126089885     86.44%     86.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7851403      5.38%     91.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4272179      2.93%     94.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2235192      1.53%     96.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1747101      1.20%     97.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       615790      0.42%     97.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       475839      0.33%     98.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       478833      0.33%     98.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2099620      1.44%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    126321778     86.46%     86.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7855301      5.38%     91.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4275066      2.93%     94.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2236699      1.53%     96.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1745226      1.19%     97.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       615725      0.42%     97.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       478401      0.33%     98.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       477554      0.33%     98.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2098071      1.44%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    145865842                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56172516                       # Number of instructions committed
-system.cpu.commit.committedOps               56172516                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    146103821                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56172911                       # Number of instructions committed
+system.cpu.commit.committedOps               56172911                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15471333                       # Number of memory references committed
-system.cpu.commit.loads                       9093055                       # Number of loads committed
-system.cpu.commit.membars                      226352                       # Number of memory barriers committed
-system.cpu.commit.branches                    8440752                       # Number of branches committed
+system.cpu.commit.refs                       15471230                       # Number of memory references committed
+system.cpu.commit.loads                       9092979                       # Number of loads committed
+system.cpu.commit.membars                      226353                       # Number of memory barriers committed
+system.cpu.commit.branches                    8440862                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52021823                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740586                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass      3198106      5.69%      5.69% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         36219281     64.48%     70.17% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult           60683      0.11%     70.28% # Class of committed instruction
+system.cpu.commit.int_insts                  52022252                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740590                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass      3198097      5.69%      5.69% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         36219833     64.48%     70.17% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult           60677      0.11%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     70.28% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd          38085      0.07%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     70.35% # Class of committed instruction
@@ -626,36 +629,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     70.35% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     70.35% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     70.35% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead         9319407     16.59%     86.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        6384233     11.37%     98.31% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess        949085      1.69%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead         9319332     16.59%     86.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        6384206     11.37%     98.31% # Class of committed instruction
+system.cpu.commit.op_class_0::IprAccess        949045      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total          56172516                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2099620                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    207703277                       # The number of ROB reads
-system.cpu.rob.rob_writes                   129775597                       # The number of ROB writes
-system.cpu.timesIdled                          576321                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6535603                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3597682440                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52981683                       # Number of Instructions Simulated
-system.cpu.committedOps                      52981683                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.903040                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.903040                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.344466                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.344466                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74566924                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40527176                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    167101                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167535                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 1985778                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 939467                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1402095                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.992786                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11832212                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1402607                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.435871                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          36097500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.992786                       # Average occupied blocks per requestor
+system.cpu.commit.op_class_0::total          56172911                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               2098071                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    207934044                       # The number of ROB reads
+system.cpu.rob.rob_writes                   129754094                       # The number of ROB writes
+system.cpu.timesIdled                          581359                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6806112                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3597208249                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52982087                       # Number of Instructions Simulated
+system.cpu.committedOps                      52982087                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.912541                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.912541                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.343343                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.343343                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74569026                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40527111                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166982                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167538                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 1985520                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 939432                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1401817                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.992665                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            11831384                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1402329                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.436953                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          36569500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.992665                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999986                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999986                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -663,380 +666,386 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          415
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63847952                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63847952                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7239475                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7239475                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4190405                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4190405                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       186164                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       186164                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215734                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215734                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11429880                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11429880                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11429880                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11429880                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1798792                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1798792                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1957410                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1957410                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23330                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23330                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           26                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           26                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3756202                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3756202                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3756202                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3756202                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57198715500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57198715500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 116967363039                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 116967363039                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    446591500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    446591500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       850000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       850000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 174166078539                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 174166078539                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 174166078539                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 174166078539                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9038267                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9038267                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6147815                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6147815                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209494                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       209494                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215760                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215760                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15186082                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15186082                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15186082                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15186082                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.199020                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.199020                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318391                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.318391                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.111364                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.111364                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000121                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000121                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.247345                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.247345                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.247345                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.247345                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31798.404429                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31798.404429                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59756.189577                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59756.189577                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19142.370339                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19142.370339                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 32692.307692                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 32692.307692                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46367.601779                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46367.601779                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46367.601779                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46367.601779                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      7156530                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         5457                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            133923                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              29                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.437647                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   188.172414                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses          63839342                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63839342                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7238802                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7238802                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4190242                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4190242                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       186215                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       186215                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215725                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215725                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11429044                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11429044                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11429044                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11429044                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1797438                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1797438                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1957552                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1957552                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23250                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23250                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           29                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           29                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3754990                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3754990                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3754990                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3754990                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57215692000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57215692000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 116805325608                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 116805325608                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    447608000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    447608000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       892500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       892500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 174021017608                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 174021017608                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 174021017608                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 174021017608                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9036240                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9036240                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6147794                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6147794                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209465                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       209465                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215754                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215754                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15184034                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15184034                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15184034                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15184034                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.198914                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.198914                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.318415                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.318415                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.110997                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.110997                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000134                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000134                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.247299                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.247299                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.247299                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.247299                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.802822                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.802822                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59669.079344                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59669.079344                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.936364                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46343.936364                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.936364                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46343.936364                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      7142845                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         5288                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            134029                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              28                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.293280                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   188.857143                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       841276                       # number of writebacks
-system.cpu.dcache.writebacks::total            841276                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       704782                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       704782                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1666649                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1666649                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5284                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5284                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2371431                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2371431                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2371431                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2371431                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1094010                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1094010                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290761                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290761                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18046                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        18046                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           26                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           26                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1384771                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1384771                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1384771                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1384771                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       841132                       # number of writebacks
+system.cpu.dcache.writebacks::total            841132                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       703605                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       703605                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1666863                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1666863                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5233                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5233                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2370468                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2370468                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2370468                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2370468                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1093833                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1093833                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290689                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       290689                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18017                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        18017                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           29                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           29                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1384522                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1384522                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1384522                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1384522                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9598                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  44554526500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  44554526500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18468782348                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  18468782348                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    228783500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    228783500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       824000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       824000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63023308848                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  63023308848                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63023308848                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  63023308848                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1450570000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1450570000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2036143500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2036143500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3486713500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3486713500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.121042                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.121042                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047295                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047295                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086141                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086141                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000121                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000121                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091187                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091187                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091187                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091187                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40725.885961                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40725.885961                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63518.774347                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63518.774347                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12677.795633                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12677.795633                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 31692.307692                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 31692.307692                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45511.719156                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45511.719156                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45511.719156                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45511.719156                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209317.460317                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209317.460317                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.477599                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.477599                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210957.980397                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210957.980397                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  44560858000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  44560858000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18438060220                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  18438060220                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    229318500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    229318500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       863500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       863500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62998918220                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  62998918220                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62998918220                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  62998918220                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1529906000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1529906000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2154205500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2154205500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3684111500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3684111500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.121050                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.121050                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047283                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047283                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086014                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086014                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000134                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000134                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091183                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091183                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091183                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091183                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.264433                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.264433                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.819873                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.819873                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12727.895876                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12727.895876                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29775.862069                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29775.862069                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.287591                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.287591                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.287591                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.287591                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220765.656566                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220765.656566                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224443.165243                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224443.165243                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222901.228219                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222901.228219                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1038950                       # number of replacements
-system.cpu.icache.tags.tagsinuse           507.834309                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7904301                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1039458                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.604252                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42289841500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   507.834309                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.991864                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.991864                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1036098                       # number of replacements
+system.cpu.icache.tags.tagsinuse           507.835115                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7900594                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1036606                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.621598                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       42318910500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   507.835115                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.991865                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.991865                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           82                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          354                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10037466                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10037466                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7904302                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7904302                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7904302                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7904302                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7904302                       # number of overall hits
-system.cpu.icache.overall_hits::total         7904302                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1093336                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1093336                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1093336                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1093336                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1093336                       # number of overall misses
-system.cpu.icache.overall_misses::total       1093336                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16294267486                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16294267486                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16294267486                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16294267486                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16294267486                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16294267486                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8997638                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8997638                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8997638                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8997638                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8997638                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8997638                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121514                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.121514                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.121514                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.121514                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.121514                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.121514                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.257083                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14903.257083                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.257083                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14903.257083                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.257083                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14903.257083                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        10533                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          10027828                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10027828                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7900595                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7900595                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7900595                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7900595                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7900595                       # number of overall hits
+system.cpu.icache.overall_hits::total         7900595                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1090254                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1090254                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1090254                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1090254                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1090254                       # number of overall misses
+system.cpu.icache.overall_misses::total       1090254                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16373491482                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16373491482                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16373491482                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16373491482                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16373491482                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16373491482                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8990849                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8990849                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8990849                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8990849                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8990849                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8990849                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121263                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.121263                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.121263                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.121263                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.121263                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.121263                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.052199                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15018.052199                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.052199                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15018.052199                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.052199                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15018.052199                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        11165                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               301                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               304                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    34.993355                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    36.726974                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53508                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        53508                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        53508                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        53508                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        53508                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        53508                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1039828                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1039828                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1039828                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1039828                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1039828                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1039828                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14359854493                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  14359854493                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14359854493                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  14359854493                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14359854493                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  14359854493                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115567                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115567                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115567                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.115567                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115567                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.115567                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13809.836332                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13809.836332                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13809.836332                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13809.836332                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13809.836332                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13809.836332                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks      1036098                       # number of writebacks
+system.cpu.icache.writebacks::total           1036098                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53275                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        53275                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        53275                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        53275                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        53275                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        53275                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1036979                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1036979                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1036979                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1036979                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1036979                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1036979                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14441674990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  14441674990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14441674990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  14441674990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14441674990                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  14441674990                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115337                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115337                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115337                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.115337                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115337                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.115337                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.680280                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.680280                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.680280                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.680280                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.680280                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.680280                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338309                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65280.236813                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4173910                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403476                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.344878                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       9183094000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53277.296150                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5308.937838                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6694.002825                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.812947                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081008                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.102142                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996097                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements           338547                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65279.196063                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4167773                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           403714                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.323578                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       9186443000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 53290.316378                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5240.255410                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6748.624275                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.813146                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.079960                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.102976                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996081                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          493                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3483                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3330                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2415                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55446                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3482                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3334                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2423                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55435                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         39757210                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        39757210                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       841276                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       841276                       # number of Writeback hits
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 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286                       # average SCUpgradeReq miss latency
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1045,147 +1054,144 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        76045                       # number of writebacks
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 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          304                       # number of CleanEvict MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            7                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            7                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115511                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       115511                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        14973                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        14973                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       273860                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       273860                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        14973                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389371                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404344                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        14973                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389371                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404344                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total         6930                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data         9598                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      7022000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      7022000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       499500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       499500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14977801000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14977801000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1868614000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1868614000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31274184500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31274184500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1868614000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46251985500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  48120599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1868614000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46251985500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  48120599500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1363945000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1363945000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1925742500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1925742500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3289687500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3289687500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.765625                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.765625                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.269231                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.269231                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383087                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383087                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014463                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014463                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248696                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248696                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014463                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277585                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.165588                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014463                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277585                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.165588                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71653.061224                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71653.061224                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71357.142857                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71357.142857                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129665.581633                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129665.581633                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124292.536916                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124292.536916                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114199.793686                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114199.793686                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124292.536916                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118787.941166                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118992.580366                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124292.536916                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118787.941166                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118992.580366                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196817.460317                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196817.460317                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.977079                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.977079                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199037.239835                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199037.239835                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      7246500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      7246500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       500000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       500000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14946254500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14946254500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1866612000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1866612000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31277372000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31277372000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1866612000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46223626500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  48090238500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1866612000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46223626500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  48090238500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1443206500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1443206500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2043789000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2043789000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3486995500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3486995500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.776923                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.776923                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.241379                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.241379                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383169                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383169                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.014443                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014443                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.248749                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248749                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014443                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277644                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.165778                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014443                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277644                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.165778                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71747.524752                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71747.524752                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71428.571429                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71428.571429                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.477773                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.477773                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124665.197355                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124665.197355                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114209.347842                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114209.347842                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124665.197355                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118713.582932                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118933.973300                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124665.197355                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118713.582932                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118933.973300                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208254.906205                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208254.906205                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210975.042352                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210975.042352                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4883718                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2441508                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2168                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4877464                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2438379                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2185                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1198                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1198                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2147995                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2144933                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9598                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       958852                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1860290                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          128                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           26                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          154                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       301527                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       301527                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1039828                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1101337                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           83                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       958726                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1035547                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       821965                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          130                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           29                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          159                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       301462                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       301462                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1036979                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1101122                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           81                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3117755                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4239617                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7357372                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     66528832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143662708                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          210191540                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      422209                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5321984                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001086                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.032932                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3109189                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4238791                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7347980                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    132621440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143635700                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          276257140                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      422449                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2878054                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001305                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.036107                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5316206     99.89%     99.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               5778      0.11%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2874297     99.87%     99.87% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3757      0.13%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5321984                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3296198000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2878054                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4329025000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1561216545                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1556715501                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2115809899                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2115441305                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1235,45 +1241,45 @@ system.iobus.pkt_size_system.bridge.master::total        44148
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2705756                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              4663000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy              5360000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               444000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              155000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              180000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13484000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            14342000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy             1887000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy             2178000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5944500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              219000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               76000                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy               88000                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy              132500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           215079498                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           215036503                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer30.occupancy               30500                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23458000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.249403                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.249428                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1725991887000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.249403                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078088                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078088                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1725995793000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.249428                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078089                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078089                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1287,14 +1293,14 @@ system.iocache.demand_misses::tsunami.ide          173                       # n
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21903883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21903883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5427983615                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5427983615                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     21903883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     21903883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     21903883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     21903883                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21806383                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21806383                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5430705120                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5430705120                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21806383                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21806383                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21806383                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21806383                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1311,19 +1317,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126612.040462                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126612.040462                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.103557                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130631.103557                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 126612.040462                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126612.040462                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 126612.040462                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126612.040462                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126048.456647                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130696.599923                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130696.599923                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126048.456647                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126048.456647                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           216                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   17                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.705882                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1337,14 +1343,14 @@ system.iocache.demand_mshr_misses::tsunami.ide          173
 system.iocache.demand_mshr_misses::total          173                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide          173                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          173                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13253883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13253883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3350383615                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3350383615                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13253883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13253883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13253883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13253883                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13156383                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13156383                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3353105120                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3353105120                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     13156383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     13156383                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     13156383                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     13156383                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1353,64 +1359,64 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76612.040462                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76612.040462                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.103557                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.103557                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76612.040462                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76612.040462                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76612.040462                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76612.040462                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80696.599923                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80696.599923                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76048.456647                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76048.456647                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                6930                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295909                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295855                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9598                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9598                       # Transaction distribution
-system.membus.trans_dist::Writeback            117557                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261789                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              334                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117574                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261706                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              351                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              7                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             341                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115275                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115275                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        289062                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           83                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             358                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115261                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115261                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        289006                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           81                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1146388                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          166                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179610                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1146220                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          162                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1179438                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124817                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1304427                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1304255                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30710528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30754676                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30707264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     30751412                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2657728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2657728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33412404                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33409140                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              435                       # Total snoops (count)
-system.membus.snoop_fanout::samples            842283                       # Request fanout histogram
+system.membus.snoop_fanout::samples            842165                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  842283    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  842165    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              842283                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            28662500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              842165                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            28939500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1313672631                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1314315898                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              106500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              106000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2139416664                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2139099889                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           69895667                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           69817453                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -1444,28 +1450,28 @@ system.tsunami.ethernet.coalescedTotal            nan                       # av
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6443                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211020                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74668     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6439                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211011                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74664     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1880      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105572     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182251                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73301     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  105567     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182242                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73297     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1880      1.27%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73301     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148613                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1818203066500     96.93%     96.93% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                62700500      0.00%     96.94% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               538036000      0.03%     96.96% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             56940563000      3.04%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1875744366000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981692                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31                    73297     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148605                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1818035067000     96.92%     96.92% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                64907500      0.00%     96.93% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               561478000      0.03%     96.96% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             57098083500      3.04%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1875759536000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694322                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815430                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694317                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815427                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1504,7 +1510,7 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175134     91.23%     93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175125     91.23%     93.43% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
@@ -1513,20 +1519,20 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.98% # nu
 system.cpu.kern.callpal::rti                     5105      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191979                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5850                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1739                      
+system.cpu.kern.callpal::total                 191970                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5852                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1908                      
+system.cpu.kern.mode_good::user                  1738                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326325                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326042                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081068                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394177                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29901576500      1.59%      1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2896080000      0.15%      1.75% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1842946701500     98.25%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.394011                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29997949500      1.60%      1.60% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2897677500      0.15%      1.75% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1842863901000     98.25%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index 8f58e32e6..54688b406 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,131 +1,131 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.841615                       # Number of seconds simulated
-sim_ticks                                1841615117500                       # Number of ticks simulated
-final_tick                               1841615117500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.843590                       # Number of seconds simulated
+sim_ticks                                1843589966000                       # Number of ticks simulated
+final_tick                               1843589966000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 220643                       # Simulator instruction rate (inst/s)
-host_op_rate                                   220643                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5550131764                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 377148                       # Number of bytes of host memory used
-host_seconds                                   331.81                       # Real time elapsed on the host
-sim_insts                                    73212541                       # Number of instructions simulated
-sim_ops                                      73212541                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 220463                       # Simulator instruction rate (inst/s)
+host_op_rate                                   220463                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5656183181                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 378132                       # Number of bytes of host memory used
+host_seconds                                   325.94                       # Real time elapsed on the host
+sim_insts                                    71858146                       # Number of instructions simulated
+sim_ops                                      71858146                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           495296                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20794752                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           141504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1560960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           279936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2513472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           498752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20812864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           142016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1542016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           270784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2513856                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25786880                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       495296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       141504                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       279936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          916736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7468864                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7468864                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7739                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            324918                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2211                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             24390                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4374                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             39273                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             25781248                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       498752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       142016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       270784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          911552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7470272                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7470272                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7793                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            325201                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2219                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             24094                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4231                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             39279                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                402920                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116701                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116701                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              268947                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            11291584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               76837                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              847604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              152006                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1364819                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                402832                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116723                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116723                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              270533                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            11289313                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               77032                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              836420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              146879                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1363566                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14002318                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         268947                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          76837                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         152006                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             497789                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4055605                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4055605                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4055605                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             268947                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           11291584                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              76837                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             847604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             152006                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1364819                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                13984264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         270533                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          77032                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         146879                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             494444                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4052025                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4052025                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4052025                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             270533                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           11289313                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              77032                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             836420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             146879                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1363566                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::tsunami.ide              521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18057923                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         70263                       # Number of read requests accepted
-system.physmem.writeReqs                        43985                       # Number of write requests accepted
-system.physmem.readBursts                       70263                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      43985                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  4495872                       # Total number of bytes read from DRAM
+system.physmem.bw_total::total               18036288                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         69838                       # Number of read requests accepted
+system.physmem.writeReqs                        42816                       # Number of write requests accepted
+system.physmem.readBursts                       69838                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      42816                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  4468672                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       960                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2813888                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   4496832                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2815040                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   2738752                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   4469632                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                2740224                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                       15                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          17213                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                4359                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4121                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4307                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                4650                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                3946                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4779                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                4258                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                4152                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                4721                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4422                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               4675                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               4103                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4083                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               4580                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               4738                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               4354                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2794                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2415                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2758                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3153                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                2458                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                2922                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                2626                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2424                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3273                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2590                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               2930                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2458                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2433                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               2833                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               3042                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2858                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          59609                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                4348                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4129                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                4337                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                4598                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                3888                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                4661                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                4236                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                4148                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                4711                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                4417                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               4595                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               4084                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               4057                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               4571                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               4705                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               4338                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2799                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2436                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2776                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                2976                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                2273                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                2670                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                2480                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2289                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                3133                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2510                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               2861                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2441                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               2439                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               2832                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               3033                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2845                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1840603135000                       # Total gap between requests
+system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1842578089000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   70263                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   69838                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  43985                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     50096                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      8386                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6407                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      5333                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        16                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  42816                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     49694                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      8424                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      6349                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      5331                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -153,195 +153,199 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        53                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        44                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::4                        43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2094                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2320                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     2129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     2264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     2949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     3610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     3273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     1911                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       74                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::38                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        47                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::28                     2702                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     2602                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     2195                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::39                       46                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::41                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        20266                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      360.690812                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     203.028180                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     371.433574                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7252     35.78%     35.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4628     22.84%     58.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1637      8.08%     66.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          935      4.61%     71.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          704      3.47%     74.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          532      2.63%     77.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          447      2.21%     79.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          402      1.98%     81.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3729     18.40%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          20266                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          1889                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        37.186342                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      837.829732                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           1887     99.89%     99.89% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::40                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       69                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        20066                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      359.185887                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     202.348650                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     370.654869                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7177     35.77%     35.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4604     22.94%     58.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1640      8.17%     66.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          939      4.68%     71.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          711      3.54%     75.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          484      2.41%     77.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          449      2.24%     79.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          396      1.97%     81.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3666     18.27%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          20066                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          1852                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        37.694924                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      845.707060                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           1850     99.89%     99.89% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::34816-36863            1      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            1889                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          1889                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        23.275278                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.746797                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       22.833114                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                34      1.80%      1.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 9      0.48%      2.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                2      0.11%      2.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               2      0.11%      2.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            1521     80.52%     83.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              51      2.70%     85.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27               9      0.48%     86.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              92      4.87%     91.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               2      0.11%     91.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               5      0.26%     91.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              17      0.90%     92.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              12      0.64%     92.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.42%     93.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.05%     93.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.11%     93.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               3      0.16%     93.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.11%     93.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.21%     94.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              10      0.53%     94.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              16      0.85%     95.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103            73      3.86%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             1      0.05%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.05%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.11%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.05%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             6      0.32%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             2      0.11%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            1889                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      866118250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2183268250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    351240000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12329.44                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            1852                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          1852                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.106371                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.632339                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       22.643623                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                34      1.84%      1.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 7      0.38%      2.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                4      0.22%      2.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               3      0.16%      2.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            1503     81.16%     83.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              52      2.81%     86.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              11      0.59%     87.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              74      4.00%     91.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               4      0.22%     91.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               8      0.43%     91.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              17      0.92%     92.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               8      0.43%     93.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               7      0.38%     93.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.05%     93.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               3      0.16%     93.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               8      0.43%     94.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               8      0.43%     94.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.05%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              15      0.81%     95.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.05%     95.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103            66      3.56%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.05%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             2      0.11%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.11%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.05%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.05%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.05%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.11%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.11%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.05%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             3      0.16%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             1      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            1852                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      871326250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2180507500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    349115000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12479.07                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31079.44                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.44                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.44                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.53                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31229.07                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.49                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.42                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.49                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         4.98                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      59265                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     34684                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.37                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.85                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16110593.93                       # Average gap between requests
-system.physmem.pageHitRate                      82.24                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   75993120                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   41365500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 269661600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                139644000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            89061061440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            36119290320                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           800836482750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             926543498730                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.762999                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1308404512000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     45532240000                       # Time in different power states
+system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         4.08                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      58948                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     33602                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.42                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.48                       # Row buffer hit rate for writes
+system.physmem.avgGap                     16356082.24                       # Average gap between requests
+system.physmem.pageHitRate                      82.17                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   75161520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   40936500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 267891000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                134129520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            89190744240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            36125026515                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           799629184500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             925463073795                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.948938                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1310373436000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     45598540000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9805597500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      9753765000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   77217840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   41955375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 278272800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                145262160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            89061061440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            35704397295                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           801349556250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             926657723160                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.725709                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1308993682000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     45532240000                       # Time in different power states
+system.physmem_1.actEnergy                   76537440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   41650125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 276728400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                143169120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            89190744240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            35621035650                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           799049139750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             924399004725                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.002289                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1311095993000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     45598540000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9217388750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9016803000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4860395                       # DTB read hits
-system.cpu0.dtb.read_misses                      6162                       # DTB read misses
+system.cpu0.dtb.read_hits                     4864865                       # DTB read hits
+system.cpu0.dtb.read_misses                      6190                       # DTB read misses
 system.cpu0.dtb.read_acv                          126                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  428546                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3431856                       # DTB write hits
-system.cpu0.dtb.write_misses                      685                       # DTB write misses
+system.cpu0.dtb.read_accesses                  429298                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3435007                       # DTB write hits
+system.cpu0.dtb.write_misses                      688                       # DTB write misses
 system.cpu0.dtb.write_acv                          84                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 164529                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8292251                       # DTB hits
-system.cpu0.dtb.data_misses                      6847                       # DTB misses
+system.cpu0.dtb.write_accesses                 165213                       # DTB write accesses
+system.cpu0.dtb.data_hits                     8299872                       # DTB hits
+system.cpu0.dtb.data_misses                      6878                       # DTB misses
 system.cpu0.dtb.data_acv                          210                       # DTB access violations
-system.cpu0.dtb.data_accesses                  593075                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2736971                       # ITB hits
-system.cpu0.itb.fetch_misses                     3081                       # ITB misses
+system.cpu0.dtb.data_accesses                  594511                       # DTB accesses
+system.cpu0.itb.fetch_hits                    2740787                       # ITB hits
+system.cpu0.itb.fetch_misses                     3088                       # ITB misses
 system.cpu0.itb.fetch_acv                         104                       # ITB acv
-system.cpu0.itb.fetch_accesses                2740052                       # ITB accesses
+system.cpu0.itb.fetch_accesses                2743875                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -354,87 +358,32 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       927057463                       # number of cpu cycles simulated
+system.cpu0.numCycles                       928566651                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31701170                       # Number of instructions committed
-system.cpu0.committedOps                     31701170                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             29591762                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                163845                       # Number of float alu accesses
-system.cpu0.num_func_calls                     797475                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4044448                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    29591762                       # number of integer instructions
-system.cpu0.num_fp_insts                       163845                       # number of float instructions
-system.cpu0.num_int_register_reads           41150829                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          21753171                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               84843                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              86199                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8322031                       # number of memory refs
-system.cpu0.num_load_insts                    4881580                       # Number of load instructions
-system.cpu0.num_store_insts                   3440451                       # Number of store instructions
-system.cpu0.num_idle_cycles              904905994.152015                       # Number of idle cycles
-system.cpu0.num_busy_cycles              22151468.847985                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023894                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976106                       # Percentage of idle cycles
-system.cpu0.Branches                          5099323                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1600258      5.05%      5.05% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 21086062     66.50%     71.55% # Class of executed instruction
-system.cpu0.op_class::IntMult                   31841      0.10%     71.65% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.65% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12946      0.04%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1618      0.01%     71.69% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.69% # Class of executed instruction
-system.cpu0.op_class::MemRead                 5012305     15.81%     87.50% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3443548     10.86%     98.36% # Class of executed instruction
-system.cpu0.op_class::IprAccess                519649      1.64%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  31708227                       # Class of executed instruction
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6423                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211399                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   74794     40.97%     40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce                    6425                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211440                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   74803     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1878      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105678     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182553                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    73427     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::22                   1880      1.03%     42.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 105703     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182589                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    73436     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1878      1.26%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   73427     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               148935                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1818498105000     98.74%     98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               39129500      0.00%     98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              356633500      0.02%     98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22720515500      1.23%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1841614383500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981723                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22                    1880      1.26%     50.70% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   73436     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               148955                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1820420159000     98.74%     98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               39420000      0.00%     98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              369089000      0.02%     98.77% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22760564000      1.23%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1843589232000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981725                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694818                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815845                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694739                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815794                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -473,451 +422,508 @@ system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175296     91.20%     93.41% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6782      3.53%     96.94% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175328     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6784      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti                    5175      2.69%     99.64% # number of callpals executed
+system.cpu0.kern.callpal::rti                    5177      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192207                       # number of callpals executed
+system.cpu0.kern.callpal::total                192243                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5921                       # number of protection mode switches
 system.cpu0.kern.mode_switch::user               1739                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle               2094                       # number of protection mode switches
+system.cpu0.kern.mode_switch::idle               2096                       # number of protection mode switches
 system.cpu0.kern.mode_good::kernel               1908                      
 system.cpu0.kern.mode_good::user                 1739                      
 system.cpu0.kern.mode_good::idle                  169                      
 system.cpu0.kern.mode_switch_good::kernel     0.322243                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      0.080707                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.391224                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29940410000      1.63%      1.63% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2625898500      0.14%      1.77% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1809048073000     98.23%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::idle      0.080630                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.391144                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel       29996442500      1.63%      1.63% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2592008500      0.14%      1.77% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1811000779000     98.23%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
-system.cpu0.dcache.tags.replacements          1393243                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997811                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13232435                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1393755                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.494090                       # Average number of references to valid blocks.
+system.cpu0.committedInsts                   32582067                       # Number of instructions committed
+system.cpu0.committedOps                     32582067                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             30467910                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                163902                       # Number of float alu accesses
+system.cpu0.num_func_calls                     798063                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4326151                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    30467910                       # number of integer instructions
+system.cpu0.num_fp_insts                       163902                       # number of float instructions
+system.cpu0.num_int_register_reads           42599897                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          22343202                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               84869                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              86282                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8329685                       # number of memory refs
+system.cpu0.num_load_insts                    4886081                       # Number of load instructions
+system.cpu0.num_store_insts                   3443604                       # Number of store instructions
+system.cpu0.num_idle_cycles              904742998.483282                       # Number of idle cycles
+system.cpu0.num_busy_cycles              23823652.516718                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.025656                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.974344                       # Percentage of idle cycles
+system.cpu0.Branches                          5381713                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              1604740      4.92%      4.92% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 21953707     67.37%     72.29% # Class of executed instruction
+system.cpu0.op_class::IntMult                   32143      0.10%     72.39% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     72.39% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  13006      0.04%     72.43% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1630      0.01%     72.43% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     72.43% # Class of executed instruction
+system.cpu0.op_class::MemRead                 5016903     15.39%     87.83% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3446713     10.58%     98.40% # Class of executed instruction
+system.cpu0.op_class::IprAccess                520313      1.60%    100.00% # Class of executed instruction
+system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu0.op_class::total                  32589155                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          1393262                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.997813                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           13241810                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1393774                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.500687                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   242.565333                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    83.938780                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   185.493697                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.473760                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.163943                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.362292                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   254.746834                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   121.216845                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   136.034134                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.497552                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.236752                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.265692                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63378181                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63378181                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4021743                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1010855                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2545337                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7577935                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3142602                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       763669                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1364636                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5270907                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114486                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        18184                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51520                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184190                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123337                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        20114                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55874                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199325                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7164345                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1774524                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3909973                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12848842                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7164345                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1774524                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3909973                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12848842                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       725431                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        86189                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       553303                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1364923                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       164575                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        38232                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       676790                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       879597                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9407                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2049                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7768                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19224                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses         63387052                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63387052                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4025112                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1019452                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2537983                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7582547                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3145682                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       772489                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1357389                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5275560                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       114073                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19050                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        51169                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       184292                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122917                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21014                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55400                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199331                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7170794                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1791941                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      3895372                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12858107                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7170794                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1791941                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      3895372                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12858107                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       726690                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        86798                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total      1362098                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       165054                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        38388                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       671853                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       875295                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9398                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2090                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7704                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        19192                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data            4                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       890006                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       124421                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1230093                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2244520                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       890006                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       124421                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1230093                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2244520                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2328658500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8887314500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11215973000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2137506500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  29622827624                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  31760334124                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27247000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    151557500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    178804500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       125000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       125000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   4466165000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  38510142124                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  42976307124                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   4466165000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  38510142124                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  42976307124                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4747174                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1097044                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      3098640                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8942858                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3307177                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       801901                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2041426                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6150504                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123893                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        20233                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        59288                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       203414                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        20114                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55878                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199330                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8054351                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      1898945                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      5140066                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15093362                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8054351                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      1898945                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      5140066                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15093362                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.152813                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.078565                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.178563                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.152627                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049763                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.047677                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.331528                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.143012                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075928                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.101270                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.131021                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094507                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data            3                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
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+system.cpu0.dcache.overall_misses::cpu0.data       891744                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       125186                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1220463                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2237393                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2310299500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8894370000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11204669500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2132273000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  29520003133                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  31652276133                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     27861500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    150264500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    178126000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       111000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       111000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   4442572500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  38414373133                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  42856945633                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   4442572500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  38414373133                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  42856945633                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4751802                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1106250                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      3086593                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8944645                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3310736                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       810877                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2029242                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6150855                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21140                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        58873                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       203484                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       122918                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21014                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55403                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199335                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8062538                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      1917127                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      5115835                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15095500                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8062538                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      1917127                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      5115835                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15095500                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.152929                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.078461                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.177740                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.152281                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049854                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.047341                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.331086                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.142305                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076115                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.098865                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.130858                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094317                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000072                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000025                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.110500                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.065521                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.239315                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.148709                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.110500                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.065521                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.239315                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.148709                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 27018.047547                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16062.292270                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  8217.293576                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55908.832915                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43769.600059                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 36107.824520                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13297.706198                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19510.491761                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9301.107990                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        31250                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        25000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35895.588365                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31306.691546                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19147.215050                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35895.588365                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31306.691546                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19147.215050                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1653965                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2392                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            59941                       # number of cycles access was blocked
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000054                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000020                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.110603                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.065299                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.238566                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.148216                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.110603                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.065299                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.238566                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.148216                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26616.966981                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16212.555367                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  8226.037701                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55545.300615                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43938.187569                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 36161.838161                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13330.861244                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19504.737799                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9281.263026                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        37000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        27750                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35487.774192                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31475.245979                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19154.858191                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35487.774192                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31475.245979                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 19154.858191                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1652146                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         2580                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            59796                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets             12                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    27.593217                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   199.333333                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    27.629708                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets          215                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       835815                       # number of writebacks
-system.cpu0.dcache.writebacks::total           835815                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       291179                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       291179                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       576940                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       576940                       # number of WriteReq MSHR hits
+system.cpu0.dcache.writebacks::writebacks       835859                       # number of writebacks
+system.cpu0.dcache.writebacks::total           835859                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       288357                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       288357                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       572581                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       572581                       # number of WriteReq MSHR hits
 system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1582                       # number of LoadLockedReq MSHR hits
 system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1582                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       868119                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       868119                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       868119                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       868119                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        86189                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       262124                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       348313                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        38232                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        99850                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       138082                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2049                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6186                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8235                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            4                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       124421                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       361974                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       486395                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       124421                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       361974                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       486395                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1341                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1578                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2919                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1620                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         1904                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3524                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2961                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3482                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6443                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2242469500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4680386500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6922856000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2099274500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4628925917                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6728200417                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     25198000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     77699000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    102897000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       121000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       121000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4341744000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9309312417                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  13651056417                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4341744000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   9309312417                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13651056417                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    280410000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    323287500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    603697500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    352231500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    401647500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    753879000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    632641500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    724935000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1357576500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.078565                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.084593                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.038949                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.047677                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.048912                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022451                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.101270                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.104338                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040484                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000072                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.065521                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070422                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032226                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.065521                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070422                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032226                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 26018.047547                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17855.619859                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19875.387941                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54908.832915                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46358.797366                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.122282                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12297.706198                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12560.459101                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12495.081967                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        30250                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        30250                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34895.588365                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25718.179806                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28065.782784                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34895.588365                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25718.179806                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28065.782784                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 209105.145414                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 204871.673004                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206816.546763                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 217426.851852                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 210949.317227                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213927.071510                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 213658.054711                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 208195.002872                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210705.649542                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       860938                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       860938                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       860938                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       860938                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        86798                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       260253                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       347051                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        38388                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        99272                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       137660                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2090                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         6122                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8212                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            3                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       125186                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       359525                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       484711                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       125186                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       359525                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       484711                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1329                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1323                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2652                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1618                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         1898                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3516                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2947                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3221                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6168                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2223501500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4676661000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6900162500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2093885000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   4616741882                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6710626882                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     25771500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     77436000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103207500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       108000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       108000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4317386500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   9293402882                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  13610789382                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4317386500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   9293402882                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13610789382                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    293417500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    298094000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    591511500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    372514000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    424017500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    796531500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    665931500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    722111500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1388043000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.078461                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.084317                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.038800                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.047341                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.048921                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022381                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.098865                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.103987                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.040357                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000054                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.065299                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070277                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032110                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.065299                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070277                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032110                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25616.966981                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17969.671819                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19882.272346                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54545.300615                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46505.982372                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48747.834389                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.807579                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.888456                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        36000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        36000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34487.774192                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25849.114476                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28080.215597                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34487.774192                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25849.114476                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28080.215597                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230231.149567                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226544.795222                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225969.290804                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.396887                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           964359                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.170929                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           40638696                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           964870                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            42.118312                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10553576500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   255.050326                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    76.933985                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   179.186618                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.498145                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.150262                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.349974                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998381                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           963474                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.175730                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           41537475                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           963985                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            43.089337                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10558559500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   261.250464                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    81.956509                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   167.968757                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.510255                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.160071                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.328064                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998390                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         42585531                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        42585531                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     31196035                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7004527                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2438134                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       40638696                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     31196035                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7004527                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2438134                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        40638696                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     31196035                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7004527                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2438134                       # number of overall hits
-system.cpu0.icache.overall_hits::total       40638696                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       512192                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       123075                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       346520                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       981787                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       512192                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       123075                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       346520                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        981787                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       512192                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       123075                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       346520                       # number of overall misses
-system.cpu0.icache.overall_misses::total       981787                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1869616000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5082111473                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6951727473                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1869616000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5082111473                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6951727473                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1869616000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5082111473                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6951727473                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     31708227                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7127602                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      2784654                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     41620483                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     31708227                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7127602                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      2784654                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     41620483                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     31708227                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7127602                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      2784654                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     41620483                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016153                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.017267                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.124439                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.023589                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016153                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.017267                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.124439                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.023589                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016153                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.017267                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.124439                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.023589                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15190.867357                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14666.141848                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  7080.688044                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15190.867357                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14666.141848                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  7080.688044                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15190.867357                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14666.141848                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  7080.688044                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         7863                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         43482483                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        43482483                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     32077013                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      7031290                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2429172                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       41537475                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     32077013                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      7031290                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2429172                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        41537475                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     32077013                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      7031290                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2429172                       # number of overall hits
+system.cpu0.icache.overall_hits::total       41537475                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       512142                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       125208                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       343493                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       980843                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       512142                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       125208                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       343493                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        980843                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       512142                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       125208                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       343493                       # number of overall misses
+system.cpu0.icache.overall_misses::total       980843                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1899043000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5060933969                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6959976969                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1899043000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   5060933969                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6959976969                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1899043000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   5060933969                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6959976969                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     32589155                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      7156498                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2772665                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     42518318                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     32589155                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      7156498                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      2772665                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     42518318                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     32589155                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      7156498                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      2772665                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     42518318                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015715                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.017496                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.123886                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.023069                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015715                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.017496                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.123886                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.023069                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015715                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.017496                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.123886                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.023069                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15167.105936                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14733.732475                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  7095.913382                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15167.105936                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14733.732475                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  7095.913382                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15167.105936                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14733.732475                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  7095.913382                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         8552                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              341                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              357                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.058651                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.955182                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16739                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        16739                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        16739                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        16739                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        16739                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        16739                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       123075                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       329781                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       452856                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       123075                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       329781                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       452856                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       123075                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       329781                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       452856                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1746541000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4501465478                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6248006478                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1746541000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4501465478                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6248006478                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1746541000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4501465478                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6248006478                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.017267                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.118428                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010881                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.017267                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.118428                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.010881                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.017267                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.118428                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.010881                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14190.867357                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13649.863024                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13796.894549                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14190.867357                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13649.863024                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13796.894549                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14190.867357                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13649.863024                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13796.894549                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       963474                       # number of writebacks
+system.cpu0.icache.writebacks::total           963474                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16678                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        16678                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        16678                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        16678                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        16678                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        16678                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       125208                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       326815                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       452023                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       125208                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       326815                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       452023                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       125208                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       326815                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       452023                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1773835000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4488659473                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6262494473                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1773835000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4488659473                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6262494473                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1773835000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4488659473                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6262494473                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.017496                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.117870                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010631                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.017496                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.117870                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.010631                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.017496                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.117870                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.010631                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14167.105936                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13734.557695                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13854.371289                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14167.105936                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13734.557695                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13854.371289                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14167.105936                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13734.557695                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13854.371289                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1115382                       # DTB read hits
-system.cpu1.dtb.read_misses                      1270                       # DTB read misses
-system.cpu1.dtb.read_acv                           33                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  123322                       # DTB read accesses
-system.cpu1.dtb.write_hits                     822469                       # DTB write hits
+system.cpu1.dtb.read_hits                     1125427                       # DTB read hits
+system.cpu1.dtb.read_misses                      1262                       # DTB read misses
+system.cpu1.dtb.read_acv                           31                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  117717                       # DTB read accesses
+system.cpu1.dtb.write_hits                     832316                       # DTB write hits
 system.cpu1.dtb.write_misses                      154                       # DTB write misses
 system.cpu1.dtb.write_acv                          18                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  50514                       # DTB write accesses
-system.cpu1.dtb.data_hits                     1937851                       # DTB hits
-system.cpu1.dtb.data_misses                      1424                       # DTB misses
-system.cpu1.dtb.data_acv                           51                       # DTB access violations
-system.cpu1.dtb.data_accesses                  173836                       # DTB accesses
-system.cpu1.itb.fetch_hits                     768661                       # ITB hits
+system.cpu1.dtb.write_accesses                  48434                       # DTB write accesses
+system.cpu1.dtb.data_hits                     1957743                       # DTB hits
+system.cpu1.dtb.data_misses                      1416                       # DTB misses
+system.cpu1.dtb.data_acv                           49                       # DTB access violations
+system.cpu1.dtb.data_accesses                  166151                       # DTB accesses
+system.cpu1.itb.fetch_hits                     753702                       # ITB hits
 system.cpu1.itb.fetch_misses                      636                       # ITB misses
 system.cpu1.itb.fetch_acv                          28                       # ITB acv
-system.cpu1.itb.fetch_accesses                 769297                       # ITB accesses
+system.cpu1.itb.fetch_accesses                 754338                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -930,64 +936,9 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953409174                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953452897                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7126126                       # Number of instructions committed
-system.cpu1.committedOps                      7126126                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              6614481                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 39892                       # Number of float alu accesses
-system.cpu1.num_func_calls                     202987                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       849967                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     6614481                       # number of integer instructions
-system.cpu1.num_fp_insts                        39892                       # number of float instructions
-system.cpu1.num_int_register_reads            9205425                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           4843983                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               21026                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              21409                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      1944596                       # number of memory refs
-system.cpu1.num_load_insts                    1119921                       # Number of load instructions
-system.cpu1.num_store_insts                    824675                       # Number of store instructions
-system.cpu1.num_idle_cycles              926242764.786654                       # Number of idle cycles
-system.cpu1.num_busy_cycles              27166409.213346                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.028494                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.971506                       # Percentage of idle cycles
-system.cpu1.Branches                          1116663                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               388723      5.45%      5.45% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  4626654     64.91%     70.37% # Class of executed instruction
-system.cpu1.op_class::IntMult                    7726      0.11%     70.47% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     70.47% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   3756      0.05%     70.53% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                    538      0.01%     70.53% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.53% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1147644     16.10%     86.64% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 825879     11.59%     98.22% # Class of executed instruction
-system.cpu1.op_class::IprAccess                126681      1.78%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7127601                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
@@ -1005,35 +956,90 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu2.branchPred.lookups               11557403                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         10821969                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           122344                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             9245404                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                7393469                       # Number of BTB hits
+system.cpu1.committedInsts                    7155032                       # Number of instructions committed
+system.cpu1.committedOps                      7155032                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              6639972                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 39507                       # Number of float alu accesses
+system.cpu1.num_func_calls                     205327                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       849342                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     6639972                       # number of integer instructions
+system.cpu1.num_fp_insts                        39507                       # number of float instructions
+system.cpu1.num_int_register_reads            9236476                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           4860513                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               20546                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              21005                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      1964570                       # number of memory refs
+system.cpu1.num_load_insts                    1130012                       # Number of load instructions
+system.cpu1.num_store_insts                    834558                       # Number of store instructions
+system.cpu1.num_idle_cycles              924897585.359422                       # Number of idle cycles
+system.cpu1.num_busy_cycles              28555311.640577                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.029949                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.970051                       # Percentage of idle cycles
+system.cpu1.Branches                          1119214                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               390317      5.45%      5.45% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  4631234     64.71%     70.17% # Class of executed instruction
+system.cpu1.op_class::IntMult                    7711      0.11%     70.28% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     70.28% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                   3307      0.05%     70.32% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     70.32% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     70.32% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     70.32% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                    440      0.01%     70.33% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.33% # Class of executed instruction
+system.cpu1.op_class::MemRead                 1158585     16.19%     86.52% # Class of executed instruction
+system.cpu1.op_class::MemWrite                 835763     11.68%     98.20% # Class of executed instruction
+system.cpu1.op_class::IprAccess                129140      1.80%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                   7156497                       # Class of executed instruction
+system.cpu2.branchPred.lookups               10791906                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         10058996                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           121698                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             8434906                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                6656118                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            79.969128                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 299976                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect              7838                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            78.911585                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 298697                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect              7721                       # Number of incorrect RAS predictions.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3543723                       # DTB read hits
-system.cpu2.dtb.read_misses                     12250                       # DTB read misses
-system.cpu2.dtb.read_acv                          123                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  249931                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2185333                       # DTB write hits
-system.cpu2.dtb.write_misses                     2753                       # DTB write misses
-system.cpu2.dtb.write_acv                         125                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  92110                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5729056                       # DTB hits
-system.cpu2.dtb.data_misses                     15003                       # DTB misses
-system.cpu2.dtb.data_acv                          248                       # DTB access violations
-system.cpu2.dtb.data_accesses                  342041                       # DTB accesses
-system.cpu2.itb.fetch_hits                     552866                       # ITB hits
-system.cpu2.itb.fetch_misses                     5354                       # ITB misses
-system.cpu2.itb.fetch_acv                         182                       # ITB acv
-system.cpu2.itb.fetch_accesses                 558220                       # ITB accesses
+system.cpu2.dtb.read_hits                     3520448                       # DTB read hits
+system.cpu2.dtb.read_misses                     12146                       # DTB read misses
+system.cpu2.dtb.read_acv                          125                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  256305                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2173477                       # DTB write hits
+system.cpu2.dtb.write_misses                     2690                       # DTB write misses
+system.cpu2.dtb.write_acv                         124                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  93625                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5693925                       # DTB hits
+system.cpu2.dtb.data_misses                     14836                       # DTB misses
+system.cpu2.dtb.data_acv                          249                       # DTB access violations
+system.cpu2.dtb.data_accesses                  349930                       # DTB accesses
+system.cpu2.itb.fetch_hits                     553155                       # ITB hits
+system.cpu2.itb.fetch_misses                     5226                       # ITB misses
+system.cpu2.itb.fetch_acv                         187                       # ITB acv
+system.cpu2.itb.fetch_accesses                 558381                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1046,304 +1052,305 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        33083271                       # number of cpu cycles simulated
+system.cpu2.numCycles                        32236279                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9301099                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      42932048                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   11557403                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           7693445                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     21583805                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 404638                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                       962                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles               10456                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1990                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles       197395                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        92170                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          829                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2784665                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                90858                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          31390787                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.367664                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.311444                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9243840                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      40617547                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   10791906                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           6954815                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     20753592                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 401538                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                       916                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles               10212                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             2008                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles       193151                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        89388                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles         1068                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2772679                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                90084                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                      1                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          30494706                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.331954                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.325119                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                21183291     67.48%     67.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  297740      0.95%     68.43% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  468841      1.49%     69.92% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 5764163     18.36%     88.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  882544      2.81%     91.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  193394      0.62%     91.71% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  232558      0.74%     92.46% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  434405      1.38%     93.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1933851      6.16%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                21037778     68.99%     68.99% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  294298      0.97%     69.95% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  469114      1.54%     71.49% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 5033169     16.51%     88.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  879924      2.89%     90.88% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  194801      0.64%     91.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  230028      0.75%     92.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  433107      1.42%     93.70% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1922487      6.30%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            31390787                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.349343                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.297697                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 7618981                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             14231209                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  8576643                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               528584                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                189420                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              174742                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                13252                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              39552027                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                41601                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                189420                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 7898470                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4727919                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       6647041                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  8797977                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              2884017                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              38737545                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                58522                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                372966                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 93481                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               1809588                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           25849349                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             48570643                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        48506980                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            59488                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             23977354                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1871995                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            535640                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         63418                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3866497                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3518835                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2279192                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           461417                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          331685                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  36218811                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             686292                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 35933838                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            15798                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2519858                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1130776                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        490718                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     31390787                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.144726                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.617565                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            30494706                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.334775                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.259995                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 7573321                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             14126025                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  7836977                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               524605                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                187915                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              174630                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                13216                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              37265458                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                41467                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                187915                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 7850244                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                4676437                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       6613578                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  8057400                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              2863279                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              36458401                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                57802                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                368784                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 93789                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               1799072                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands           24336413                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             45554095                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        45489801                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            60051                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             22465786                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1870627                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            531021                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         62908                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3828322                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3503706                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2266582                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           453499                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          325031                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  33954893                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             679527                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 33661057                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            16143                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2513373                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1127788                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        486024                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     30494706                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.103833                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.612725                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           18577248     59.18%     59.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2723782      8.68%     67.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1358088      4.33%     72.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            6489843     20.67%     92.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1045865      3.33%     96.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             589790      1.88%     98.07% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             396015      1.26%     99.33% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             165397      0.53%     99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              44759      0.14%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           18452821     60.51%     60.51% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            2702851      8.86%     69.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1349809      4.43%     73.80% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            5753089     18.87%     92.67% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            1041578      3.42%     96.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             588420      1.93%     98.01% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             396893      1.30%     99.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             164409      0.54%     99.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              44836      0.15%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       31390787                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       30494706                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  81235     20.78%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     20.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                183347     46.90%     67.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               126357     32.32%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  81527     21.02%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     21.02% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                179819     46.37%     67.39% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               126481     32.61%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             2960      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             29699192     82.65%     82.66% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               21615      0.06%     82.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd              21814      0.06%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1480      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.78% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3672081     10.22%     93.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2209398      6.15%     99.15% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            305298      0.85%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass             3131      0.01%      0.01% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             27465013     81.59%     81.60% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               21327      0.06%     81.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     81.67% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd              22209      0.07%     81.73% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     81.73% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     81.73% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     81.73% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1566      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     81.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3648084     10.84%     92.57% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2197360      6.53%     99.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            302367      0.90%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              35933838                       # Type of FU issued
-system.cpu2.iq.rate                          1.086163                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     390939                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.010879                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         103401518                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         39305388                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     35307106                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             263682                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            125410                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       122335                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              36181025                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 140792                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          202971                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              33661057                       # Type of FU issued
+system.cpu2.iq.rate                          1.044198                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     387827                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.011522                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          97956454                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         37027606                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     33043548                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             264336                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            125822                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       122705                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              33904668                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 141085                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          200240                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       432355                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1077                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         5954                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       178558                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       431120                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1112                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5749                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       178621                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         4490                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       225000                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         4239                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       217381                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                189420                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                4054480                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               208473                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           38277538                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            51152                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3518835                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2279192                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            610930                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 12812                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               160010                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          5954                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         60508                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       134714                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              195222                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             35737943                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3564708                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           195895                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                187915                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                4008679                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               205535                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           35998675                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            51747                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3503706                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2266582                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            605109                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 12931                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents               157162                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5749                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         59808                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       134012                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              193820                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             33465262                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3541255                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           195795                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1372435                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5757521                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 8471480                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2192813                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.080242                       # Inst execution rate
-system.cpu2.iew.wb_sent                      35472276                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     35429441                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 20887132                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 24638595                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                      1364255                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5722116                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 7732316                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2180861                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.038124                       # Inst execution rate
+system.cpu2.iew.wb_sent                      33208664                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     33166253                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 19395256                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 23138933                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.070917                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.847740                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.028849                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.838209                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        2638965                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         195574                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           178349                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     30927462                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.150843                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.846358                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        2630446                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         193503                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           177071                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     30033551                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.109504                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.847540                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     19331784     62.51%     62.51% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2240622      7.24%     69.75% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1164134      3.76%     73.52% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      6211408     20.08%     93.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       591221      1.91%     95.51% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       197085      0.64%     96.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       163594      0.53%     96.68% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       163249      0.53%     97.21% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       864365      2.79%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     19200071     63.93%     63.93% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2226295      7.41%     71.34% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1158853      3.86%     75.20% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      5473619     18.23%     93.42% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       589521      1.96%     95.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       197097      0.66%     96.04% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       164200      0.55%     96.59% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       162437      0.54%     97.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       861458      2.87%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     30927462                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            35592650                       # Number of instructions committed
-system.cpu2.commit.committedOps              35592650                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     30033551                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            33322350                       # Number of instructions committed
+system.cpu2.commit.committedOps              33322350                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       5187114                       # Number of memory references committed
-system.cpu2.commit.loads                      3086480                       # Number of loads committed
-system.cpu2.commit.membars                      68869                       # Number of memory barriers committed
-system.cpu2.commit.branches                   8299152                       # Number of branches committed
-system.cpu2.commit.fp_insts                    120520                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 34085086                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              241488                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1210365      3.40%      3.40% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        28775352     80.85%     84.25% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          21144      0.06%     84.31% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     84.31% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd         21379      0.06%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv          1480      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     84.37% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3155349      8.87%     93.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2102283      5.91%     99.14% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       305298      0.86%    100.00% # Class of committed instruction
+system.cpu2.commit.refs                       5160547                       # Number of memory references committed
+system.cpu2.commit.loads                      3072586                       # Number of loads committed
+system.cpu2.commit.membars                      67946                       # Number of memory barriers committed
+system.cpu2.commit.branches                   7560075                       # Number of branches committed
+system.cpu2.commit.fp_insts                    120848                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 31822701                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              240099                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass      1204434      3.61%      3.61% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu        26541208     79.65%     83.26% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          20874      0.06%     83.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv               0      0.00%     83.33% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd         21768      0.07%     83.39% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     83.39% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     83.39% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     83.39% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv          1566      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     83.40% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        3140532      9.42%     92.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       2089601      6.27%     99.09% # Class of committed instruction
+system.cpu2.commit.op_class_0::IprAccess       302367      0.91%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         35592650                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               864365                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                    68219321                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   76925100                       # The number of ROB writes
-system.cpu2.timesIdled                         177793                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1692484                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1742724515                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   34385245                       # Number of Instructions Simulated
-system.cpu2.committedOps                     34385245                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              0.962136                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.962136                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.039354                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.039354                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                46956630                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               24762728                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    74199                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   74347                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                6109617                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                275370                       # number of misc regfile writes
+system.cpu2.commit.op_class_0::total         33322350                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events               861458                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                    65049813                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   72365341                       # The number of ROB writes
+system.cpu2.timesIdled                         178213                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1741573                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1747477665                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   32121047                       # Number of Instructions Simulated
+system.cpu2.committedOps                     32121047                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.003587                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.003587                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.996425                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.996425                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                43934131                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               23251716                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    74710                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   74652                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                5374912                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                272966                       # number of misc regfile writes
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -1358,9 +1365,9 @@ system.disk2.dma_write_bytes                     8192                       # Nu
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
 system.iobus.trans_dist::ReadReq                 7317                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7317                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51362                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51362                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5192                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51364                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51364                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5196                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1372,11 +1379,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33908                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33912                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  117358                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20768                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  117362                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20784                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1388,37 +1395,37 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        45568                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total        45584                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2707176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2206000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2707192                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2564500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               116500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy               48000                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy               55500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5525000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6287500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             2084000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             2121000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy                2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy            88878376                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy            84230549                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             9362000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             8820000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17358000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            16458000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.254039                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.261273                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1693946387000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.254039                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078377                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078377                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1694926918000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.261273                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078830                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078830                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1432,14 +1439,14 @@ system.iocache.demand_misses::tsunami.ide          173                       # n
 system.iocache.demand_misses::total               173                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide          173                       # number of overall misses
 system.iocache.overall_misses::total              173                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide      9722962                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total      9722962                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   2243179414                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   2243179414                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide      9722962                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total      9722962                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide      9722962                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total      9722962                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide      9458962                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total      9458962                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   2126843587                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   2126843587                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide      9458962                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total      9458962                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide      9458962                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total      9458962                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
@@ -1456,266 +1463,270 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56202.092486                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 56202.092486                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 53984.872305                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 53984.872305                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 56202.092486                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 56202.092486                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 56202.092486                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 56202.092486                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54676.080925                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 54676.080925                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 51185.107504                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 51185.107504                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 54676.080925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 54676.080925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 54676.080925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 54676.080925                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            31                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     5.166667                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41512                       # number of writebacks
 system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide           71                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total           71                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        17168                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        17168                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide           71                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total           71                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide           71                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total           71                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      6172962                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      6172962                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1384779414                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1384779414                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide      6172962                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total      6172962                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide      6172962                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total      6172962                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.410405                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.410405                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.413169                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.413169                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide     0.410405                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.410405                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide     0.410405                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.410405                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86943.126761                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 86943.126761                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80660.497088                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80660.497088                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86943.126761                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 86943.126761                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86943.126761                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 86943.126761                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::tsunami.ide           69                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::tsunami.ide        16272                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        16272                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide           69                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total           69                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide           69                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total           69                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      6008962                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total      6008962                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1313243587                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1313243587                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide      6008962                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total      6008962                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide      6008962                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total      6008962                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.391606                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.391606                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.398844                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.398844                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87086.405797                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 87086.405797                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80705.726831                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80705.726831                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 87086.405797                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 87086.405797                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 87086.405797                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 87086.405797                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   337421                       # number of replacements
-system.l2c.tags.tagsinuse                65422.020035                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4006967                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402583                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.953145                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   337614                       # number of replacements
+system.l2c.tags.tagsinuse                65425.004009                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4005267                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402776                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.944155                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54749.853403                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2632.785518                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2879.050483                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      437.699618                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      567.874446                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2112.962465                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     2041.794102                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.835416                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.040173                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.043931                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.006679                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.008665                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.032241                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.031155                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998261                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   54894.973613                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2664.591905                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2878.625445                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      441.912379                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      553.808439                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2003.360689                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     1987.731539                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.837631                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.040658                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.043924                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.006743                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.008450                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.030569                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.030330                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998306                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          717                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         6187                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2728                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55352                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          713                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6136                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2779                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55356                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38426412                       # Number of tag accesses
-system.l2c.tags.data_accesses                38426412                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          835815                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835815                       # number of Writeback hits
+system.l2c.tags.tag_accesses                 38412750                       # Number of tag accesses
+system.l2c.tags.data_accesses                38412750                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks       835859                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          835859                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks       963177                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          963177                       # number of WritebackClean hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data               8                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  12                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             3                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            90170                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            24197                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            72759                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               187126                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        504433                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        120864                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        325383                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            950680                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       484059                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        77838                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       255762                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           817659                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              504433                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              574229                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              120864                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              102035                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              325383                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              328521                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1955465                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             504433                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             574229                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             120864                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             102035                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             325383                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             328521                       # number of overall hits
-system.l2c.overall_hits::total                1955465                       # number of overall hits
+system.l2c.UpgradeReq_hits::cpu2.data               9                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  13                       # number of UpgradeReq hits
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 system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data        80500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        40250                       # average SCUpgradeReq miss latency
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+system.l2c.overall_avg_miss_latency::total 22725.314884                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1724,228 +1735,225 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.writebacks::total                    75189                       # number of writebacks
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 system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        70500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total        70500                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::total   8500316500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    276798000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    281540000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    558338000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    353898000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    402187000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total    756085000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    630696000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    683727000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1314423000                       # number of overall MSHR uncacheable cycles
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.608696                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.333333                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.363456                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.273358                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.135832                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.017723                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.012947                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006690                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.114594                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.046721                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.020732                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017723                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.189652                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.012947                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.108381                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.029775                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017723                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.189652                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.012947                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.108381                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.029775                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        71750                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total        71750                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        70500                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117392.867322                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125466.345449                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 122724.652761                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122264.586160                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123139.689072                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122845.861807                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116726.778846                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117147.104153                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116954.769447                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122264.586160                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117109.355816                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123139.689072                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122877.763756                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 120879.499993                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122264.586160                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117109.355816                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123139.689072                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122877.763756                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 120879.499993                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196605.145414                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 192371.673004                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 194316.546763                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 205926.851852                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 199449.317227                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 202427.071510                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 201705.167173                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 196241.815049                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 198752.599721                       # average overall mshr uncacheable latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117532.325115                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125700.959841                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 122930.961987                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122011.266336                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123863.625620                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123226.356589                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116441.046534                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117536.509851                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117043.234163                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122011.266336                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117071.816223                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123863.625620                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123138.945668                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 121061.261839                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122011.266336                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117071.816223                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123863.625620                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123138.945668                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 121061.261839                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208275.395034                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 212804.232804                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210534.690799                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218725.587145                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211900.421496                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215041.240046                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214012.894469                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212271.654766                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 213103.599222                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7144                       # Transaction distribution
-system.membus.trans_dist::ReadResp             294893                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9810                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9810                       # Transaction distribution
-system.membus.trans_dist::Writeback            116701                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261800                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              141                       # Transaction distribution
+system.membus.trans_dist::ReadResp             294754                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9812                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9812                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       116723                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261691                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              160                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             143                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115600                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115600                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        288004                       # Transaction distribution
-system.membus.trans_dist::BadAddressError          255                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             162                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            115651                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           115651                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        287866                       # Transaction distribution
+system.membus.trans_dist::BadAddressError          256                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1143509                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          510                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1177927                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124919                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124919                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1302846                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30608832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     30654400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2664256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33318656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              161                       # Total snoops (count)
-system.membus.snoop_fanout::samples            840917                       # Request fanout histogram
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1143284                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          512                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1177708                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124921                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124921                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1302629                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30604608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     30650192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2664384                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33314576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              159                       # Total snoops (count)
+system.membus.snoop_fanout::samples            840768                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  840917    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  840768    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              840917                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            11282500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              840768                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            11147000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           355534840                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           348692458                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              348500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              315000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          377985955                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          375048955                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           28782491                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           27286702                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests      4716700                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2358029                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1601                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1128                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1128                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      4714972                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2357166                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1609                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1129                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1129                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadReq               7144                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2063159                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              9810                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             9810                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           879803                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1563697                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              33                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             5                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             38                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302846                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302846                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        965048                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1091237                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError          255                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq        17168                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2894139                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4214034                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7108173                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     61761536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142741760                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              204503296                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          421014                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          5154488                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.000869                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.029472                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadResp           2062235                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              9812                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             9812                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       878682                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       963177                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          599628                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              35                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp             39                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           302904                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          302904                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        964165                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1091197                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError          256                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        16272                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2891480                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4214095                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7105575                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    123348160                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142745680                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              266093840                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          421214                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4208473                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.000983                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.031334                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5150007     99.91%     99.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                   4481      0.09%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4204337     99.90%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                   4136      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            5154488                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1335525500                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4208473                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         1783329500                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           102462                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy            99462                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         679735096                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         678448171                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         746367473                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         743541954                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index a32ac72f7..ba967980d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,162 +1,162 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.848053                       # Number of seconds simulated
-sim_ticks                                2848053071500                       # Number of ticks simulated
-final_tick                               2848053071500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.848948                       # Number of seconds simulated
+sim_ticks                                2848948370000                       # Number of ticks simulated
+final_tick                               2848948370000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 153295                       # Simulator instruction rate (inst/s)
-host_op_rate                                   185627                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3443122383                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 659004                       # Number of bytes of host memory used
-host_seconds                                   827.17                       # Real time elapsed on the host
-sim_insts                                   126801159                       # Number of instructions simulated
-sim_ops                                     153545030                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 158621                       # Simulator instruction rate (inst/s)
+host_op_rate                                   192077                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3558804720                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 665700                       # Number of bytes of host memory used
+host_seconds                                   800.54                       # Real time elapsed on the host
+sim_insts                                   126981470                       # Number of instructions simulated
+sim_ops                                     153764073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         8768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         8960                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1683840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1312624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8530944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           199296                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           609360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       366080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1698304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1350900                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8536512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           207232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           624212                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       339264                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12712960                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1683840                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       199296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1883136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8845504                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12767176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1698304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       207232                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1905536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8850048                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8863068                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          137                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8867612                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          140                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26310                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             21032                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       133296                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3114                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9541                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         5720                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26536                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             21631                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       133383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           12                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3238                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9774                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         5301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                199182                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138211                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                200031                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138282                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142602                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3079                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               142673                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3145                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              591225                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              460885                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2995360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               69976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              213957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       128537                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              596116                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              474175                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2996373                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           270                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               72740                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              219103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       119084                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4463737                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         591225                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          69976                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             661201                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3105807                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6153                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4481364                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         596116                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          72740                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             668856                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3106426                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6151                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3111974                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3105807                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3079                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3112591                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3106426                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3145                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             591225                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             467038                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2995360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              69976                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             213971                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       128537                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             596116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             480326                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2996373                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          270                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              72740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             219117                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       119084                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7575711                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        199182                       # Number of read requests accepted
-system.physmem.writeReqs                       142602                       # Number of write requests accepted
-system.physmem.readBursts                      199182                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     142602                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12737472                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8875904                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12712960                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8863068                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          49648                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12703                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12645                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12416                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12383                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15579                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12155                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12470                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12693                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11969                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11857                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12504                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11838                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11708                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12391                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11950                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11762                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9214                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9232                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9104                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8883                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8269                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8437                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8818                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8777                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8437                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8418                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9013                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8780                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8383                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8480                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8424                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8017                       # Per bank write bursts
+system.physmem.bw_total::total                7593956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        200031                       # Number of read requests accepted
+system.physmem.writeReqs                       142673                       # Number of write requests accepted
+system.physmem.readBursts                      200031                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     142673                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12791872                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10112                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8880320                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12767176                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8867612                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      158                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          68768                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12184                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12601                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               13506                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12929                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15744                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12758                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12529                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12787                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11927                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12161                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11607                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10617                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11871                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12870                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12074                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11708                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8731                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9199                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9827                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9174                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8354                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8906                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8822                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8920                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8409                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8625                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8250                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7761                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8553                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8825                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8501                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7898                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2848052462500                       # Total gap between requests
+system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2848947824000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     552                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     554                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  198602                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  199449                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 138211                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     87578                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61104                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     11612                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9452                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7822                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6360                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4675                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3805                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       696                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      208                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      180                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      143                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 138282                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     88254                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     61332                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     11783                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9470                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7796                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6317                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5163                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4597                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3794                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       675                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      220                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      170                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -184,157 +184,161 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4408                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4909                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5831                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7825                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8951                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9075                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7997                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      505                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       47                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        89100                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      242.573648                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     137.731983                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     302.151175                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46893     52.63%     52.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17637     19.79%     72.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6363      7.14%     79.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3624      4.07%     83.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2948      3.31%     86.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1436      1.61%     88.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          938      1.05%     89.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          975      1.09%     90.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8286      9.30%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          89100                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6864                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.995047                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      543.916897                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6863     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6864                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6864                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.204837                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.711823                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.958888                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5637     82.12%     82.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             489      7.12%     89.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              82      1.19%     90.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             154      2.24%     92.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              37      0.54%     93.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             124      1.81%     95.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              47      0.68%     95.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              16      0.23%     95.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              21      0.31%     96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              19      0.28%     96.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.09%     96.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              10      0.15%     96.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             153      2.23%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.01%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.07%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              30      0.44%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.06%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.03%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.04%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.16%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.04%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6864                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5502163905                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9233845155                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    995115000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27645.87                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15                     2858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4553                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::19                     5946                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::57                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       32                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       86                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        92034                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      235.479584                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.901184                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     297.713631                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          49789     54.10%     54.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17966     19.52%     73.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6251      6.79%     80.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3568      3.88%     84.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2967      3.22%     87.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1449      1.57%     89.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          893      0.97%     90.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          932      1.01%     91.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8219      8.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          92034                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6844                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.203828                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      563.949624                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6843     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6844                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6844                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.273963                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.786776                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.867549                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5615     82.04%     82.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             464      6.78%     88.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             114      1.67%     90.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             150      2.19%     92.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              34      0.50%     93.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             131      1.91%     95.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              38      0.56%     95.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              19      0.28%     95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              23      0.34%     96.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              24      0.35%     96.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               8      0.12%     96.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.12%     96.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             141      2.06%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               9      0.13%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              23      0.34%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               5      0.07%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.01%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.04%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.03%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.04%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.01%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.01%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.01%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.19%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6844                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5355833046                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9103451796                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    999365000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26796.18                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46395.87                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.47                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45546.18                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.46                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.48                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        3.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.71                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     165564                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     83044                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.19                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.87                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8332901.66                       # Average gap between requests
-system.physmem.pageHitRate                      73.61                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  347056920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  189366375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 803743200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                458356320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186020568240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            84074155830                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1635078931500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1906972178385                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.571882                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2719967809945                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95102540000                       # Time in different power states
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.97                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     165962                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     80631                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.03                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.10                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8313144.36                       # Average gap between requests
+system.physmem.pageHitRate                      72.82                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  368376120                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  200998875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 819296400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                466125840                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186079052640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            85041435285                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1634767692000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1907742977160                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.631992                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2719447345615                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95132440000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32976648805                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     34362631885                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  326539080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  178171125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 748628400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                440328960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186020568240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            83156024340                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1635884310000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1906754570145                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.495475                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2721316836638                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95102540000                       # Time in different power states
+system.physmem_1.actEnergy                  327400920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  178641375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 739705200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                433006560                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186079052640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            83645503290                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1635992193750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1907395503735                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.510026                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2721498270016                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95132440000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31633548862                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     32317496984                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
@@ -360,15 +364,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               36422708                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         17757542                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1699668                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            20591819                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               15078708                       # Number of BTB hits
+system.cpu0.branchPred.lookups               36425252                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         17807915                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1745628                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            20690008                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               15088743                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            73.226693                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               11344544                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            821497                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.927681                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               11310340                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            873015                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -399,56 +403,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    72997                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               72997                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47155                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        25842                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples        72997                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          72997    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        72997                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         7509                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 10509.122386                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9271.690184                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  8241.046102                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767         7465     99.41%     99.41% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535           36      0.48%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839            7      0.09%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         7509                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples    581566000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0      581566000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total    581566000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5843     77.81%     77.81% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1666     22.19%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         7509                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        72997                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    73398                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               73398                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47504                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        25894                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        73398                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          73398    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        73398                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         7534                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12254.313778                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11412.538854                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6583.009911                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767         7485     99.35%     99.35% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535           43      0.57%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            5      0.07%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         7534                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    581987000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0      581987000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    581987000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5832     77.41%     77.41% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1702     22.59%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7534                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        73398                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        72997                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7509                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        73398                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7534                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7509                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        80506                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7534                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        80932                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    24918355                       # DTB read hits
-system.cpu0.dtb.read_misses                     66392                       # DTB read misses
-system.cpu0.dtb.write_hits                   18544526                       # DTB write hits
-system.cpu0.dtb.write_misses                     6605                       # DTB write misses
+system.cpu0.dtb.read_hits                    24893776                       # DTB read hits
+system.cpu0.dtb.read_misses                     66568                       # DTB read misses
+system.cpu0.dtb.write_hits                   18528826                       # DTB write hits
+system.cpu0.dtb.write_misses                     6830                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3803                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1293                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2019                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3826                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1295                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2023                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      636                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                24984747                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18551131                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      643                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24960344                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18535656                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         43462881                       # DTB hits
-system.cpu0.dtb.misses                          72997                       # DTB misses
-system.cpu0.dtb.accesses                     43535878                       # DTB accesses
+system.cpu0.dtb.hits                         43422602                       # DTB hits
+system.cpu0.dtb.misses                          73398                       # DTB misses
+system.cpu0.dtb.accesses                     43496000                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -478,37 +482,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     4165                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                4165                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walks                     4162                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                4162                       # Table walker walks initiated with short descriptors
 system.cpu0.itb.walker.walksShortTerminationLevel::Level1          324                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3841                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         4165                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           4165    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         4165                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2676                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 10991.778774                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean  9686.198014                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6109.891448                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2598     97.09%     97.09% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767           50      1.87%     98.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           27      1.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3838                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         4162                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           4162    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         4162                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2674                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12829.655946                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 12107.498542                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5222.854689                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         2410     90.13%     90.13% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          239      8.94%     99.07% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           23      0.86%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2676                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples    580856500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      580856500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total    580856500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2357     88.08%     88.08% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          319     11.92%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2676                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         2674                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples    581277500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      581277500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total    581277500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2355     88.07%     88.07% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          319     11.93%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2674                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4165                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4165                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4162                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4162                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2676                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2676                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6841                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    71531107                       # ITB inst hits
-system.cpu0.itb.inst_misses                      4165                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2674                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2674                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6836                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    71465911                       # ITB inst hits
+system.cpu0.itb.inst_misses                      4162                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -517,131 +522,131 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2451                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2452                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     8112                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     8217                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                71535272                       # ITB inst accesses
-system.cpu0.itb.hits                         71531107                       # DTB hits
-system.cpu0.itb.misses                           4165                       # DTB misses
-system.cpu0.itb.accesses                     71535272                       # DTB accesses
-system.cpu0.numCycles                       246249018                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                71470073                       # ITB inst accesses
+system.cpu0.itb.hits                         71465911                       # DTB hits
+system.cpu0.itb.misses                           4162                       # DTB misses
+system.cpu0.itb.accesses                     71470073                       # DTB accesses
+system.cpu0.numCycles                       248898522                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  113090684                       # Number of instructions committed
-system.cpu0.committedOps                    136745700                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      8942808                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     1853                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5449882320                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.177447                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.459253                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  112980792                       # Number of instructions committed
+system.cpu0.committedOps                    136605971                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      8918624                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     1867                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5449022663                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.203016                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.453923                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1854                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      199226503                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       47022515                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements           754267                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          495.799422                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           41868735                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           754779                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            55.471516                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        600230000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   495.799422                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.968358                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.968358                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                    1869                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      199912219                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       48986303                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements           760179                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          497.990908                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           41826926                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           760691                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            54.985436                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        600550000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.990908                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.972638                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.972638                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         86874809                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        86874809                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     23308542                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23308542                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     17374131                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      17374131                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       329905                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       329905                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374910                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       374910                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       371257                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       371257                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     40682673                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        40682673                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     41012578                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41012578                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       490349                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       490349                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       600389                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       600389                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141605                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       141605                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21484                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21484                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20155                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20155                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1090738                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1090738                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1232343                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1232343                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6919620500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6919620500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  11358969500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  11358969500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    328836500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    328836500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    472700000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    472700000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       403000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       403000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  18278590000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  18278590000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  18278590000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  18278590000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     23798891                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     23798891                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     17974520                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17974520                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       471510                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       471510                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396394                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       396394                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391412                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       391412                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     41773411                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     41773411                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     42244921                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     42244921                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.020604                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033402                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.033402                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.300322                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.300322                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054199                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054199                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051493                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051493                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026111                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.026111                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029171                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029171                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14111.623558                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14111.623558                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18919.349788                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18919.349788                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15306.111525                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15306.111525                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23453.237410                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23453.237410                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         86810511                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        86810511                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     23283800                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23283800                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     17355484                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      17355484                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       329213                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       329213                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374953                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       374953                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370901                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       370901                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     40639284                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        40639284                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     40968497                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       40968497                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       494585                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       494585                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       604894                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       604894                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141990                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       141990                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21416                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21416                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20509                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20509                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1099479                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1099479                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1241469                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1241469                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6989932000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6989932000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  12583639500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  12583639500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    328970000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    328970000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    535273000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    535273000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       491000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       491000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  19573571500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  19573571500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  19573571500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  19573571500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     23778385                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     23778385                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17960378                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17960378                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       471203                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       471203                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396369                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       396369                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391410                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       391410                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     41738763                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     41738763                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     42209966                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     42209966                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020800                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.020800                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033679                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.033679                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.301335                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.301335                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054030                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054030                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052398                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052398                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026342                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.026342                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029412                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029412                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14132.923562                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14132.923562                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20803.048964                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20803.048964                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.945088                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.945088                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26099.419767                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26099.419767                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16758.002380                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16758.002380                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14832.388385                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14832.388385                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17802.587862                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 17802.587862                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.460137                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15766.460137                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -650,149 +655,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       540480                       # number of writebacks
-system.cpu0.dcache.writebacks::total           540480                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        76076                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        76076                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       264589                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       264589                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14754                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14754                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data       340665                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       340665                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data       340665                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       340665                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       414273                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       414273                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       335800                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       335800                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107967                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       107967                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6730                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6730                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20155                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20155                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       750073                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       750073                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       858040                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       858040                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32040                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32040                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28722                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28722                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60762                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60762                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5238286000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5238286000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6456534000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6456534000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1810830000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1810830000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104761500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104761500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    452552000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    452552000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       396000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       396000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11694820000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11694820000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13505650000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13505650000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6348331500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6348331500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5156547500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5156547500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11504879000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11504879000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017407                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017407                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018682                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018682                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228981                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228981                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016978                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016978                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051493                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051493                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017956                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.017956                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020311                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.020311                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12644.526677                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12644.526677                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19227.319833                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19227.319833                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16772.069243                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16772.069243                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15566.344725                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15566.344725                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.584718                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.584718                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       760179                       # number of writebacks
+system.cpu0.dcache.writebacks::total           760179                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        76321                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        76321                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       266412                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       266412                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14897                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14897                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data       342733                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       342733                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data       342733                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       342733                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       418264                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       418264                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       338482                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       338482                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       108425                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       108425                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6519                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6519                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20509                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20509                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       756746                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       756746                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       865171                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       865171                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32043                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32043                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28725                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28725                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60768                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60768                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5296846500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5296846500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7120379000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7120379000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1808041000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1808041000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    103110500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103110500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    514774000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    514774000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       481000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       481000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12417225500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12417225500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14225266500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  14225266500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6702942500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6702942500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5452503000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5452503000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12155445500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12155445500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017590                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017590                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018846                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018846                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230103                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.230103                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016447                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016447                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052398                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052398                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018131                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018131                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020497                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.020497                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12663.883337                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12663.883337                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21036.211674                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21036.211674                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16675.499193                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16675.499193                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15816.919773                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15816.919773                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25099.907358                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25099.907358                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15591.575753                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15591.575753                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15740.117011                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15740.117011                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 198137.687266                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198137.687266                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179533.023466                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179533.023466                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189343.323130                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189343.323130                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16408.709792                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16408.709792                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16442.144385                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16442.144385                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209185.859626                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209185.859626                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189817.336815                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189817.336815                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200030.369602                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200030.369602                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          2044285                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.729271                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           69477789                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          2044797                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            33.977842                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6924011000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.729271                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999471                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999471                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          2044142                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.727750                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           69412626                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          2044654                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            33.948348                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       6975539000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.727750                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999468                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999468                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          230                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          103                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        145090031                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       145090031                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     69477789                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       69477789                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     69477789                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        69477789                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     69477789                       # number of overall hits
-system.cpu0.icache.overall_hits::total       69477789                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      2044818                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2044818                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      2044818                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2044818                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      2044818                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2044818                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20517256500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  20517256500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  20517256500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  20517256500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  20517256500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  20517256500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     71522607                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     71522607                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     71522607                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     71522607                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     71522607                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     71522607                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028590                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028590                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028590                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028590                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028590                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028590                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10033.781246                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10033.781246                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10033.781246                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10033.781246                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10033.781246                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10033.781246                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        144959270                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       144959270                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     69412626                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       69412626                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     69412626                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        69412626                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     69412626                       # number of overall hits
+system.cpu0.icache.overall_hits::total       69412626                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      2044673                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2044673                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      2044673                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2044673                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      2044673                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2044673                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20581599000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  20581599000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  20581599000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  20581599000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  20581599000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  20581599000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     71457299                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     71457299                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     71457299                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     71457299                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     71457299                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     71457299                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028614                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028614                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028614                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028614                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028614                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028614                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10065.961159                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10065.961159                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10065.961159                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10065.961159                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10065.961159                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10065.961159                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -801,469 +806,464 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2044818                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      2044818                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      2044818                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      2044818                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      2044818                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      2044818                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3915                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total         3915                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3915                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total         3915                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19494848000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  19494848000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19494848000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  19494848000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19494848000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  19494848000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    557217500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    557217500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    557217500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    557217500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028590                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028590                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028590                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028590                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028590                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028590                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9533.781491                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9533.781491                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9533.781491                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9533.781491                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9533.781491                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9533.781491                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142328.863346                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142328.863346                       # average overall mshr uncacheable latency
+system.cpu0.icache.writebacks::writebacks      2044142                       # number of writebacks
+system.cpu0.icache.writebacks::total          2044142                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2044673                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      2044673                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      2044673                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      2044673                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      2044673                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      2044673                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total         3917                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total         3917                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19559263000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  19559263000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19559263000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  19559263000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19559263000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  19559263000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    557356500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    557356500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028614                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028614                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028614                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9565.961403                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9565.961403                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9565.961403                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1923323                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1923513                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit          165                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1928199                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1928402                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit          177                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       243791                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          310417                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16162.197478                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           5245257                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          326630                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           16.058712                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle    2827807181000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  6560.031691                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    62.859334                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.055204                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  5926.735945                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1926.535864                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1685.979439                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.400393                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003837                       # Average percentage of cache occupancy
+system.cpu0.l2cache.prefetcher.pfSpanPage       245070                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          307107                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16117.232598                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           4904017                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          323243                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           15.171301                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.112164                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    60.295680                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.052107                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1300.772647                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.900642                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003680                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000003                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.361739                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.117586                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.102904                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.986462                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          984                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15223                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          330                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          428                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          218                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4188                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8533                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2180                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.060059                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000366                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.929138                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        93116780                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       93116780                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        86201                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4393                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         90594                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       540479                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       540479                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28758                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28758                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2008                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         2008                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       233257                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       233257                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1970223                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1970223                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       427246                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       427246                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        86201                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4393                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1970223                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       660503                       # number of demand (read+write) hits
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-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        86201                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4393                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1970223                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       660503                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       2721320                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          779                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           93                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          872                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26665                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        26665                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18145                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        18145                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        47128                       # number of ReadExReq misses
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-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        74595                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        74595                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101717                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       101717                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          779                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker           93                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        74595                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       148845                       # number of demand (read+write) misses
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-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          779                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker           93                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        74595                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       148845                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       224312                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     36149500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2302000                       # number of ReadReq miss cycles
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-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    622250500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    622250500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    390027000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    390027000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       384498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       384498                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3148896999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   3148896999                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4603637500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4603637500                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3550040997                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3550040997                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     36149500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2302000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4603637500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   6698937996                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  11341026996                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     36149500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2302000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4603637500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   6698937996                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  11341026996                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        86980                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4486                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        91466                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks       540479                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       540479                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55423                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        55423                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20153                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20153                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       280385                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       280385                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      2044818                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      2044818                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       528963                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       528963                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        86980                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4486                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      2044818                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       809348                       # number of demand (read+write) accesses
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-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        86980                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4486                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      2044818                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       809348                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2945632                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008956                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.020731                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.009534                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.481118                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.481118                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.900362                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.900362                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.079393                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.983718                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          975                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15154                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          320                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          419                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          227                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4177                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8282                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2255                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.059509                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.924927                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        93492271                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       93492271                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        89943                       # number of ReadReq hits
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+system.cpu0.l2cache.ReadReq_hits::total         95657                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks       509380                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total       509380                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      2249647                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      2249647                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       233063                       # number of ReadExReq hits
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+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1974299                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1974299                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       431967                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       431967                       # number of ReadSharedReq hits
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+system.cpu0.l2cache.ReadReq_misses::total          843                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        56685                       # number of UpgradeReq misses
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+system.cpu0.l2cache.UpgradeReq_miss_latency::total    198503500                       # number of UpgradeReq miss cycles
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+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4513596000                       # number of ReadCleanReq miss cycles
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+system.cpu0.l2cache.WritebackDirty_accesses::total       509380                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      2249647                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      2249647                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56685                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadSharedReq_accesses::total       533201                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        90673                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5827                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      2044673                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       815009                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2956182                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        90673                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5827                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      2044673                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       815009                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2956182                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.008736                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.168083                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.168083                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.036480                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.036480                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.192295                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.192295                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008956                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.020731                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.036480                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.183907                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.076151                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008956                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.020731                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.036480                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.183907                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.076151                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 46405.006418                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24752.688172                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44095.756881                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 23335.852241                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 23335.852241                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21495.012400                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21495.012400                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       192249                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       192249                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66815.841941                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66815.841941                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 61715.094845                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 61715.094845                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34901.157103                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34901.157103                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 46405.006418                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24752.688172                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 61715.094845                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45006.133871                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 50559.163112                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 46405.006418                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24752.688172                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 61715.094845                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45006.133871                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 50559.163112                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          102                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.172972                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.172972                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034418                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034418                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.189861                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.189861                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034418                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.184021                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.074825                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034418                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.184021                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.074825                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44808.422301                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3501.869983                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3501.869983                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2200.580261                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2200.580261                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       464999                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       464999                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66052.395117                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66052.395117                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64137.266604                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64137.266604                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35074.505571                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35074.505571                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64137.266604                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45142.696624                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 51184.587411                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64137.266604                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45142.696624                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 51184.587411                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           52                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       205168                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          205168                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5239                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5239                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           89                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           89                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          602                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          602                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           89                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5841                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         5930                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           89                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5841                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         5930                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          779                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           93                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          872                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks        10393                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total        10393                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       251914                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       251914                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26665                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26665                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18145                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18145                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41889                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41889                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        74506                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        74506                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       101115                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       101115                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          779                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           93                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        74506                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143004                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       218382                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          779                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           93                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        74506                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143004                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       251914                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       470296                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3915                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32040                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        35955                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28722                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28722                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3915                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60762                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        64677                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     31475500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1744000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     33219500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21126531245                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21126531245                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    933301999                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    933301999                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    299858500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    299858500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       342498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       342498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2392710000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2392710000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4153675000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4153675000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2908093997                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2908093997                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     31475500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1744000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4153675000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5300803997                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   9487698497                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     31475500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1744000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4153675000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5300803997                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21126531245                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  30614229742                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    525897000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6091912000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6617809000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4940592000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4940592000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    525897000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11032504000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11558401000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008956                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.020731                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009534                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.writebacks::writebacks       238189                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          238189                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5772                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         5772                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           79                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           79                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          597                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          597                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           79                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6369                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         6448                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           79                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6369                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         6448                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          730                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          113                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          843                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264088                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       264088                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56685                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56685                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20508                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20508                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42973                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        42973                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        70295                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        70295                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100637                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100637                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          730                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          113                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        70295                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143610                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       214748                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          730                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          113                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        70295                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143610                       # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total       478836                       # number of overall MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32043                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        35960                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28725                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28725                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60768                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        64685                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     32715500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21010993372                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21010993372                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1525168000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1525168000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    360192000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    360192000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       404999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       404999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2462258500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2462258500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4089276000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4089276000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2913504497                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2913504497                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4089276000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5375762997                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   9497754497                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4089276000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5375762997                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21010993372                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  30508747869                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6446417500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6972437500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5236548000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5236548000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11682965500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12208985500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.008736                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.481118                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.481118                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.900362                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.900362                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.149398                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.149398                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.036436                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.036436                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.191157                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.191157                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008956                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.020731                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.036436                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.176690                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.074138                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008956                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.020731                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.036436                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.176690                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.152490                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.152490                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034380                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.188741                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.188741                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.176207                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.072644                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.176207                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.159659                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38095.756881                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83864.061723                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35001.012526                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35001.012526                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16525.682006                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16525.682006                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       171249                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       171249                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57120.246365                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57120.246365                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 55749.536950                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 55749.536950                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28760.263037                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28760.263037                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 55749.536950                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37067.522566                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43445.423602                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 55749.536950                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37067.522566                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 65095.662608                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190134.581773                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 184058.100403                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172014.205139                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172014.205139                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181569.138606                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 178709.603105                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.161978                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38808.422301                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79560.575914                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79560.575914                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26906.024521                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26906.024521                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17563.487420                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17563.487420                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       404999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       404999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57297.803272                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57297.803272                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58173.070631                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28950.629460                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28950.629460                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37433.068707                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44227.440987                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37433.068707                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79560.575914                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63714.398811                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201180.210967                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193894.257508                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182299.321149                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182299.321149                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192255.224789                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188745.234598                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      5752448                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2898331                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        44168                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       171817                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       171638                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          179                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        142841                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2765458                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28722                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28722                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       746343                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2333999                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       319529                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        85747                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42548                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       112824                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           16                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       299375                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       296092                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2044818                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       602268                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3078                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6106044                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2739032                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12492                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       185819                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          9043387                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    131118848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     90716354                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17944                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       347920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         222201066                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     910866                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      6693455                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.042507                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.201876                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests      5764816                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2905184                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        45291                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       351229                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       346765                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4464                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        143291                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2770361                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28725                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28725                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       748097                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      2249647                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       247676                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       331668                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        87164                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42906                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       114222                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       300767                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       297392                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2044673                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       607119                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3062                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6104641                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2759378                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13827                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       189965                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          9067811                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    259587264                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104603354                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        23308                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       362692                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         364576618                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1079592                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4075784                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.104187                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.309067                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           6409112     95.75%     95.75% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            284164      4.25%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               179      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           3655604     89.69%     89.69% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            415716     10.20%     99.89% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              4464      0.11%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       6693455                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    3504755489                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    115583734                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       4075784                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    5775269994                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    115824460                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   3073459276                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   3073569625                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1298870694                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1308368315                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      8011489                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      8011477                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     98861455                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     99320942                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                3534290                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          1990183                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           201553                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2067319                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1417438                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3602112                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2032281                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           210658                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2218631                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1453392                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            68.564068                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 735878                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             53173                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            65.508505                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 748126                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             55361                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1293,59 +1293,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    21952                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               21952                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        17656                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4296                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples        21952                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          21952    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        21952                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1858                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11787.944026                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10957.170839                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  8000.267562                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         1715     92.30%     92.30% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          133      7.16%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151            6      0.32%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535            1      0.05%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.05%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::212992-229375            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1858                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -2099073032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -2099073032    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -2099073032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1319     70.99%     70.99% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          539     29.01%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1858                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        21952                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                    22520                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               22520                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18297                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4223                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        22520                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          22520    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        22520                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1840                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11809.782609                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11060.962968                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6551.399815                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         1685     91.58%     91.58% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          142      7.72%     99.29% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151            8      0.43%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.16%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::147456-163839            2      0.11%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1840                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1558893032                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1558893032    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1558893032                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1331     72.34%     72.34% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          509     27.66%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1840                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        22520                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        21952                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1858                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        22520                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1840                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1858                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        23810                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1840                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        24360                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3504265                       # DTB read hits
-system.cpu1.dtb.read_misses                     20273                       # DTB read misses
-system.cpu1.dtb.write_hits                    2919622                       # DTB write hits
-system.cpu1.dtb.write_misses                     1679                       # DTB write misses
+system.cpu1.dtb.read_hits                     3580818                       # DTB read hits
+system.cpu1.dtb.read_misses                     20748                       # DTB read misses
+system.cpu1.dtb.write_hits                    2975375                       # DTB write hits
+system.cpu1.dtb.write_misses                     1772                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1723                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       86                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   239                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1719                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       96                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   254                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      213                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3524538                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2921301                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3601566                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2977147                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6423887                       # DTB hits
-system.cpu1.dtb.misses                          21952                       # DTB misses
-system.cpu1.dtb.accesses                      6445839                       # DTB accesses
+system.cpu1.dtb.hits                          6556193                       # DTB hits
+system.cpu1.dtb.misses                          22520                       # DTB misses
+system.cpu1.dtb.accesses                      6578713                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1375,42 +1373,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     1951                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                1951                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          155                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1796                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         1951                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           1951    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         1951                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples          845                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11383.431953                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10916.753394                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  4130.106784                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          149     17.63%     17.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          569     67.34%     84.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          107     12.66%     97.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.12%     97.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671            9      1.07%     98.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767            4      0.47%     99.29% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            4      0.47%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                     1949                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                1949                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          152                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1797                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         1949                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           1949    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         1949                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          843                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11825.029656                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11322.074300                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  4470.335302                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          130     15.42%     15.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          558     66.19%     81.61% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          110     13.05%     94.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           21      2.49%     97.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            4      0.47%     97.63% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           10      1.19%     98.81% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            2      0.24%     99.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            6      0.71%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::57344-61439            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total          845                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -2099960532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -2099960532    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -2099960532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          705     83.43%     83.43% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          140     16.57%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          845                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total          843                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -1559948532                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1559948532    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1559948532                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          703     83.39%     83.39% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          140     16.61%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          843                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1951                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1951                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1949                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1949                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          845                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          845                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         2796                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                     6761340                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1951                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          843                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          843                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         2792                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     6911047                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1949                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1419,130 +1418,130 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     909                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     907                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1020                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1031                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 6763291                       # ITB inst accesses
-system.cpu1.itb.hits                          6761340                       # DTB hits
-system.cpu1.itb.misses                           1951                       # DTB misses
-system.cpu1.itb.accesses                      6763291                       # DTB accesses
-system.cpu1.numCycles                        39381699                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 6912996                       # ITB inst accesses
+system.cpu1.itb.hits                          6911047                       # DTB hits
+system.cpu1.itb.misses                           1949                       # DTB misses
+system.cpu1.itb.accesses                      6912996                       # DTB accesses
+system.cpu1.numCycles                        40490463                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   13710475                       # Number of instructions committed
-system.cpu1.committedOps                     16799330                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      1340837                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2719                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5656091241                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.872380                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.348143                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   14000678                       # Number of instructions committed
+system.cpu1.committedOps                     17158102                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      1376852                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2767                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5656768220                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.892036                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.345777                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2719                       # number of quiesce instructions executed
-system.cpu1.tickCycles                       26653258                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       12728441                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements           152894                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          470.093140                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            6072239                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           153243                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            39.624903                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     110033723500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   470.093140                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.918151                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.918151                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          349                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          286                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.681641                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12903758                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12903758                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3189039                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3189039                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2677291                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2677291                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41980                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        41980                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69267                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        69267                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        60867                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        60867                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5866330                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5866330                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5908310                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5908310                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       130563                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       130563                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       120040                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       120040                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24252                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        24252                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16672                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        16672                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23310                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23310                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       250603                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        250603                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       274855                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       274855                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2128187500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2128187500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4337924000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   4337924000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    321753000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    321753000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    615942500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    615942500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1442500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1442500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   6466111500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6466111500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   6466111500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6466111500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3319602                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3319602                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2797331                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2797331                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66232                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        66232                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        85939                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        85939                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84177                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        84177                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      6116933                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      6116933                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      6183165                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6183165                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039331                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.039331                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.042912                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.042912                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.366167                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.366167                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.193998                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.193998                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.276916                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.276916                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040969                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.040969                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044452                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.044452                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16300.081187                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16300.081187                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36137.320893                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 36137.320893                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19299.004319                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19299.004319                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26423.959674                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26423.959674                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2770                       # number of quiesce instructions executed
+system.cpu1.tickCycles                       27318087                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       13172376                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements           156172                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          474.293359                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            6205519                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           156527                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            39.645039                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      91623607000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   474.293359                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.926354                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.926354                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          355                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          304                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.693359                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         13166537                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        13166537                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3257703                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3257703                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2730447                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2730447                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42566                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        42566                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70436                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        70436                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61872                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        61872                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5988150                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5988150                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      6030716                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        6030716                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       134164                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       134164                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       121295                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       121295                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24483                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        24483                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16576                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        16576                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23384                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23384                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       255459                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        255459                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       279942                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       279942                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2171565000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2171565000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4482158000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   4482158000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    319581000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    319581000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    639162500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    639162500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1395500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1395500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6653723000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6653723000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6653723000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6653723000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3391867                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3391867                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2851742                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2851742                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        67049                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        67049                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87012                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        87012                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85256                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        85256                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6243609                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6243609                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6310658                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6310658                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039555                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.039555                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.042534                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.042534                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.365151                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.365151                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.190502                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.190502                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274280                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274280                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040915                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.040915                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044360                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044360                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16185.899347                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16185.899347                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36952.537203                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 36952.537203                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19279.741795                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19279.741795                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27333.326206                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27333.326206                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25802.211067                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 25802.211067                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23525.537101                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23525.537101                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26046.148306                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26046.148306                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23768.219846                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23768.219846                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1551,149 +1550,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        95329                       # number of writebacks
-system.cpu1.dcache.writebacks::total            95329                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12149                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        12149                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        41106                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        41106                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11576                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11576                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        53255                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        53255                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        53255                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        53255                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       118414                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       118414                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        78934                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        78934                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23724                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        23724                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5096                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5096                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23310                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23310                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       197348                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       197348                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       221072                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       221072                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2845                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2845                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2191                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2191                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5036                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5036                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1811744000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1811744000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2651572500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2651572500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    432946000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    432946000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     92138000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     92138000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    592646500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    592646500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1428500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1428500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4463316500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4463316500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4896262500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4896262500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    356276500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    356276500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    224816500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    224816500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    581093000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    581093000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035671                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035671                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028218                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028218                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.358195                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.358195                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059298                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.059298                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.276916                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.276916                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032263                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.032263                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035754                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035754                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15300.082760                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15300.082760                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33592.273292                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33592.273292                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18249.283426                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18249.283426                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18080.455259                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18080.455259                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25424.560275                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25424.560275                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       156173                       # number of writebacks
+system.cpu1.dcache.writebacks::total           156173                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12677                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        12677                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        41645                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        41645                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11699                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11699                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        54322                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        54322                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        54322                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        54322                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       121487                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       121487                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79650                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        79650                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23961                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        23961                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4877                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4877                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23384                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23384                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       201137                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       201137                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       225098                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       225098                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2976                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2976                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5287                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5287                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1847735500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1847735500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2733456500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2733456500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    448084000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    448084000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87974000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87974000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    615791500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    615791500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1382500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1382500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4581192000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4581192000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5029276000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5029276000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    389353500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    389353500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    251607000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    251607000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    640960500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    640960500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035817                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035817                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027930                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027930                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.357366                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.357366                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056050                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056050                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274280                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274280                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032215                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.032215                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035669                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035669                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15209.326924                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15209.326924                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34318.349027                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34318.349027                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18700.555069                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18700.555069                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18038.548288                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18038.548288                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26333.882142                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26333.882142                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22616.476985                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22616.476985                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22147.818358                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22147.818358                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125228.998243                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125228.998243                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102609.082611                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 102609.082611                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115387.807784                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 115387.807784                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22776.475735                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22776.475735                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22342.606331                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22342.606331                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130831.149194                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130831.149194                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108873.647772                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108873.647772                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121233.308114                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121233.308114                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           837637                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.228366                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            5922018                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           838149                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             7.065591                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      72771979500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.228366                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975055                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975055                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           857356                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.135276                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6052000                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           857868                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             7.054698                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      73316283000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.135276                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974874                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.974874                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          465                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           46                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          464                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           47                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         14358483                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        14358483                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      5922018                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        5922018                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      5922018                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         5922018                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      5922018                       # number of overall hits
-system.cpu1.icache.overall_hits::total        5922018                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       838149                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       838149                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       838149                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        838149                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       838149                       # number of overall misses
-system.cpu1.icache.overall_misses::total       838149                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7371671000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   7371671000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   7371671000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   7371671000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   7371671000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   7371671000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      6760167                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      6760167                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      6760167                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      6760167                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      6760167                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      6760167                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.123983                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.123983                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.123983                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.123983                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.123983                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.123983                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8795.179616                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8795.179616                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8795.179616                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8795.179616                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8795.179616                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8795.179616                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         14677604                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14677604                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6052000                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6052000                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6052000                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6052000                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6052000                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6052000                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       857868                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       857868                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       857868                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        857868                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       857868                       # number of overall misses
+system.cpu1.icache.overall_misses::total       857868                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7591768500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7591768500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7591768500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7591768500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7591768500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7591768500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      6909868                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      6909868                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      6909868                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      6909868                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      6909868                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      6909868                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.124151                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.124151                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.124151                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.124151                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.124151                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.124151                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8849.576508                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8849.576508                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8849.576508                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8849.576508                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8849.576508                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8849.576508                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1702,452 +1701,456 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       838149                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       838149                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       838149                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       838149                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       838149                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       838149                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       857356                       # number of writebacks
+system.cpu1.icache.writebacks::total           857356                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       857868                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       857868                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       857868                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       857868                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       857868                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       857868                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6952596500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   6952596500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6952596500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   6952596500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6952596500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   6952596500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15127000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15127000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15127000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     15127000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.123983                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.123983                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.123983                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.123983                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.123983                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.123983                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8295.179616                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8295.179616                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8295.179616                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8295.179616                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8295.179616                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8295.179616                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135062.500000                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135062.500000                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135062.500000                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7162834500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   7162834500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7162834500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   7162834500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7162834500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   7162834500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15350500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     15350500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.124151                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.124151                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.124151                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8349.576508                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8349.576508                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8349.576508                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       119402                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       119476                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           64                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       119508                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       119564                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           49                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        48156                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           37250                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15275.676235                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1897057                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           52360                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           36.231035                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        48908                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           37772                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15172.719385                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1844058                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           52876                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           34.875142                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  7998.087446                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    32.292792                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.074638                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4213.861593                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2174.488490                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   856.871276                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.488165                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001971                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14738.461893                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    30.967636                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.078899                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   403.210957                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.899564                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001890                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000005                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.257194                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.132720                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.052299                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.932353                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1099                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           91                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13920                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           56                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1042                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.024610                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.926069                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          917                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14102                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           47                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          870                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           57                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1993                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        11603                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.067078                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005554                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.849609                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        33573934                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       33573934                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        23345                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2401                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         25746                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks        95329                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total        95329                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1276                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1276                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          784                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total          784                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        17759                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        17759                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       825014                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       825014                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        81245                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        81245                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        23345                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2401                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       825014                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data        99004                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         949764                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        23345                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2401                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       825014                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data        99004                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        949764                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          724                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          240                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          964                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        27711                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        27711                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22526                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22526                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32189                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        32189                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13135                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        13135                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        65988                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        65988                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          724                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          240                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        13135                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data        98177                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       112276                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          724                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          240                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        13135                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data        98177                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       112276                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     16832000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4807500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     21639500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    545169500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    545169500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    480035000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    480035000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1407500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1407500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1686123500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1686123500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    733172000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    733172000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1579312997                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1579312997                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     16832000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4807500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    733172000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3265436497                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   4020247997                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     16832000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4807500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    733172000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3265436497                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   4020247997                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        24069                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2641                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        26710                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks        95329                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total        95329                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28987                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        28987                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23310                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23310                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        49948                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        49948                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       838149                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       838149                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       147233                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       147233                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        24069                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2641                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       838149                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       197181                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      1062040                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        24069                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2641                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       838149                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       197181                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1062040                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.030080                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.090875                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.036091                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.955980                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.955980                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.966366                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.966366                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.644450                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.644450                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.015671                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.015671                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.448188                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.448188                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.030080                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.090875                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.015671                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.497903                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.105717                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.030080                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.090875                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.015671                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.497903                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.105717                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23248.618785                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20031.250000                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22447.614108                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19673.396846                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19673.396846                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21310.263695                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21310.263695                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52381.978316                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52381.978316                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 55818.195660                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 55818.195660                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23933.336319                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23933.336319                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23248.618785                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20031.250000                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 55818.195660                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33260.707671                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 35806.833134                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23248.618785                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20031.250000                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 55818.195660                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33260.707671                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 35806.833134                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           54                       # number of cycles access was blocked
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           53                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          316                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1682                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12104                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.055969                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.860718                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        34274864                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       34274864                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        23931                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2459                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         26390                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks        94554                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total        94554                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       900775                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total       900775                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        17922                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        17922                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       845092                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       845092                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        83494                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total        83494                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        23931                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2459                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       845092                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       101416                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         972898                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        23931                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2459                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       845092                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       101416                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        972898                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          683                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          243                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          926                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29302                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29302                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23383                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        23383                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32429                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        32429                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        12776                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        12776                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        66828                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        66828                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          683                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker          243                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst        12776                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data        99257                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       112959                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          683                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          243                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        12776                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data        99257                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       112959                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     15528000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4905000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     20433000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     65464500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     65464500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     59174500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     59174500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1363000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1363000                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1719425500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1719425500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    735868000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    735868000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1599140998                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1599140998                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     15528000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4905000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    735868000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3318566498                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   4074867498                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     15528000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4905000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    735868000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3318566498                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4074867498                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        24614                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2702                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        27316                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks        94554                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total        94554                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       900775                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       900775                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29302                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29302                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23383                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23383                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50351                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        50351                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       857868                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       857868                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       150322                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       150322                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        24614                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2702                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       857868                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       200673                       # number of demand (read+write) accesses
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+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        24614                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2702                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       857868                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       200673                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      1085857                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.033900                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.644059                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.644059                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.014893                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.014893                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.444566                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.444566                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.014893                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.494621                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.104028                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.014893                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.494621                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.104028                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22065.874730                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2234.130776                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2234.130776                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2530.663302                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2530.663302                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1363000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1363000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53021.230997                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53021.230997                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57597.683156                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57597.683156                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23929.206291                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23929.206291                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57597.683156                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33434.080196                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 36073.863065                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57597.683156                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33434.080196                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 36073.863065                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           91                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           27                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    22.750000                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        25088                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           25088                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          258                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          258                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           13                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           45                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           45                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           13                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          303                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          316                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           13                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          303                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          316                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          724                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          240                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          964                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         1571                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total         1571                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        18681                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        18681                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        27711                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        27711                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22526                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22526                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31931                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        31931                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        13122                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        13122                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        65943                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        65943                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          724                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          240                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        13122                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data        97874                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       111960                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          724                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          240                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        13122                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data        97874                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        18681                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       130641                       # number of overall MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        29006                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           29006                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          239                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          239                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            9                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           41                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           41                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            9                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          280                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          289                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            9                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data          280                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total          289                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          683                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          243                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          926                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        20213                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        20213                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29302                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29302                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23383                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23383                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32190                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        32190                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        12767                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        12767                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        66787                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        66787                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          683                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          243                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        12767                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data        98977                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       112670                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          683                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          243                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        12767                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data        98977                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        20213                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       132883                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         2845                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         2957                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2191                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2191                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         2976                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3088                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5036                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5148                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     12488000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3367500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     15855500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1045426686                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1045426686                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    554064000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    554064000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    417044500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    417044500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1323500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1323500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1465371000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1465371000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    653754000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    653754000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1181307497                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1181307497                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     12488000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3367500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    653754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2646678497                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3316287997                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     12488000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3367500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    653754000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2646678497                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1045426686                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4361714683                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14231000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    333495000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    347726000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    208256000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    208256000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14231000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    541751000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    555982000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.030080                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.090875                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.036091                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5287                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5399                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     14877000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    967332273                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    967332273                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    596044000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    596044000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    438887000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    438887000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1285000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1285000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1502190000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1502190000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    658879500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    658879500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1196481498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1196481498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    658879500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2698671498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3372427998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    658879500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2698671498                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    967332273                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4339760271                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    365478500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    379933000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    234145500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    234145500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    599624000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    614078500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.033900                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.955980                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.955980                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.966366                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.966366                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.639285                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.639285                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.015656                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.015656                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.447882                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.447882                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.030080                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.090875                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.015656                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.496366                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.105420                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.030080                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.090875                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.015656                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.496366                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.639312                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.639312                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014882                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.444293                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.444293                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.493225                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103761                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.493225                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.123009                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16447.614108                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55962.030191                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19994.370467                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19994.370467                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18513.917251                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18513.917251                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45891.797939                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45891.797939                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49821.216278                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49821.216278                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.069681                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.069681                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49821.216278                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27041.691328                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29620.292935                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49821.216278                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27041.691328                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33387.027679                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117221.441125                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117594.183294                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95050.661798                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 95050.661798                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 107575.655282                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 107999.611500                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.122376                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16065.874730                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47856.937268                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47856.937268                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.410143                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.410143                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18769.490656                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18769.490656                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1285000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1285000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46666.356011                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46666.356011                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51608.012846                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.886101                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.886101                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27265.642503                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29931.907322                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27265.642503                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47856.937268                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32658.506137                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122808.635753                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123035.297927                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101317.827780                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101317.827780                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113414.790997                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113739.303575                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      2085429                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1050114                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18070                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       105283                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       105064                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          219                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         32952                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1055933                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2191                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2191                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       125445                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict       933113                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        22957                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        71384                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41419                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        84915                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq            7                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        57410                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        54585                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       838149                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       236592                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq           39                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2498025                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       734861                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6388                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50317                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          3289591                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     53648704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     21442516                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10564                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        96276                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          75198060                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     344587                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      2379730                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.062577                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.242581                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests      2131909                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1073389                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18199                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       177399                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       176178                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1221                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         33577                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1078735                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2311                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2311                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       124920                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       900775                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        97230                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        24545                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        71695                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41696                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        84990                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        57514                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        55014                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       857868                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       234653                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           35                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2557119                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       745420                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6448                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        51357                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          3360344                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    108744896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25394242                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        98456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         134248402                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     381517                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1451505                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.140526                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.349944                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           2231032     93.75%     93.75% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            148479      6.24%     99.99% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               219      0.01%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0           1248752     86.03%     86.03% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            201532     13.88%     99.92% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              1221      0.08%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       2379730                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1153078495                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     79714518                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1451505                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    2095009994                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     78651519                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1257481819                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1287084271                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    326951344                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    333125737                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      3747000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      3746000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     26275944                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     26768449                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59425                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59425                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56620                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               59424                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59424                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56618                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
@@ -2168,11 +2171,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107932                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180868                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71564                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180866                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71562                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
@@ -2193,67 +2196,67 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162814                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2483990                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40103000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2483988                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             51019501                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               109500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                85000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               572500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               21500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               45500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6101000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              169500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            32834001                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              123500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186411762                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           186304797                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               32500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84733000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36433                       # number of replacements
-system.iocache.tags.tagsinuse               14.472862                       # Cycle average of tags in use
+system.iocache.tags.replacements                36449                       # number of replacements
+system.iocache.tags.tagsinuse               14.470000                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36465                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         271656669000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.472862                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.904554                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.904554                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         272418338000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.470000                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.904375                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.904375                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2267,14 +2270,14 @@ system.iocache.demand_misses::realview.ide          243                       #
 system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          243                       # number of overall misses
 system.iocache.overall_misses::total              243                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31866877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31866877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4715834885                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4715834885                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31866877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31866877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31866877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31866877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     31658876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31658876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4735531921                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4735531921                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31658876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31658876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31658876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31658876                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2291,24 +2294,24 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 131139.411523                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 131139.411523                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130185.371163                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130185.371163                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 131139.411523                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 131139.411523                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 131139.411523                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 131139.411523                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            14                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 130283.440329                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 130283.440329                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130729.127678                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130729.127678                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130283.440329                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130283.440329                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130283.440329                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130283.440329                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           628                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   73                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     3.500000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.602740                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36190                       # number of writebacks
-system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.writebacks::writebacks           36206                       # number of writebacks
+system.iocache.writebacks::total                36206                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
@@ -2317,14 +2320,14 @@ system.iocache.demand_mshr_misses::realview.ide          243
 system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19716877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19716877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2904634885                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2904634885                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19716877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19716877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19716877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19716877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19508876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19508876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2924331921                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2924331921                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19508876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19508876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19508876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19508876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2333,580 +2336,576 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 81139.411523                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 81139.411523                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80185.371163                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80185.371163                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 81139.411523                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 81139.411523                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 81139.411523                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 81139.411523                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80283.440329                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 80283.440329                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80729.127678                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80729.127678                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80283.440329                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80283.440329                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80283.440329                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80283.440329                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   133318                       # number of replacements
-system.l2c.tags.tagsinuse                64014.997062                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     446453                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   198047                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.254278                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   131732                       # number of replacements
+system.l2c.tags.tagsinuse                63242.215263                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     477411                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   195803                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.438221                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12007.955719                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    82.059666                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.029625                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     9722.429733                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3069.037039                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34559.641433                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     9.516745                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1816.838650                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      555.114204                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2192.374249                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.183227                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001252                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.148353                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.046830                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.527338                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000145                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.027723                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.008470                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.033453                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.976791                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        30866                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           82                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        33781                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2           78                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5648                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        25140                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           81                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          325                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2821                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        30623                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.470978                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.001251                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.515457                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  5802831                       # Number of tag accesses
-system.l2c.tags.data_accesses                 5802831                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          230256                       # number of Writeback hits
-system.l2c.Writeback_hits::total               230256                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            3083                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             464                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                3547                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           148                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           197                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               345                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4599                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1379                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 5978                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          467                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           86                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        52086                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        51828                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        50532                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           70                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           13                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        10095                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data         4893                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3282                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           173352                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           467                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            86                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               52086                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               56427                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        50532                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            70                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            13                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               10095                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                6272                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         3282                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  179330                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          467                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           86                       # number of overall hits
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+system.l2c.tags.occ_blocks::cpu1.inst     1918.660878                       # Average occupied blocks per requestor
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-system.l2c.ReadExReq_accesses::total            24925                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          604                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu0.data        61566                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu1.data         6486                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         9002                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       349456                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          604                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker           87                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           74498                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           77174                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       183998                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.data           15803                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher         9002                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              374381                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          604                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       183998                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::total             374381                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.754616                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.823305                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.766491                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.770543                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.858680                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.830799                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.705343                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.851991                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.760160                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.226821                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.300840                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.158172                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.230329                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.245606                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.503938                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.226821                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::total           0.520996                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.226821                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.011494                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu0.data      0.268834                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.186047                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.230329                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.603113                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::total          0.520996                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3647.400063                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2473.866790                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  3429.485528                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7626.760563                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2251.044277                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  3828.217237                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 149178.399491                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132081.191736                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 142015.385021                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140923.357664                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst   2956600500                       # number of overall miss cycles
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+system.l2c.WritebackDirty_accesses::total       267195                       # number of WritebackDirty accesses(hits+misses)
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.519756                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.260556                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.246684                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.573647                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.386528                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.724203                       # miss rate for ReadExReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.159528                       # miss rate for ReadSharedReq accesses
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+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.243478                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.009174                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.243478                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.528891                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3150.649728                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2719.655607                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  3069.802253                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7596.774194                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2696.442382                       # average SCUpgradeReq miss latency
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 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       133000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 130596.510798                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137126.771411                       # average ReadSharedReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       142250                       # average ReadSharedReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140152.542373                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 148268.856363                       # average ReadSharedReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 130596.510798                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 143521.738083                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 151539.933451                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       142250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 134324.892420                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 133430.227678                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 147661.402305                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140923.357664                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 130596.510798                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 143521.738083                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       142250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 134324.892420                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 133430.227678                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 169976.647378                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 147661.402305                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               687                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 130603.432282                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 142916.920410                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136166.666667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 133067.863954                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 132890.952820                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 146806.898747                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               305                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        6                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           229                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     50.833333                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              102021                       # number of writebacks
-system.l2c.writebacks::total                   102021                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            6                       # number of ReadSharedReq MSHR hits
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-system.l2c.overall_mshr_hits::total                13                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3105                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3105                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         9481                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2162                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        11643                       # number of UpgradeReq MSHR misses
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+system.l2c.demand_mshr_miss_latency::cpu1.data   1200767500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    837010222                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  26798862237                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     17811500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       123000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   2702366000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   2770092500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18890768758                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      2116000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    375139500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1176413500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    915066423                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  26850022181                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    443682000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5515186000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11878500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    282299000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6253045500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4452219000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    171006500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4623225500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    443682000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9967405000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11878500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    453305500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10876271000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   2729644000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2837377500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18787928515                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1514000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    386686000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1200767500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    837010222                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  26798862237                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5869618000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    311913500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6637396500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4748092000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    194851500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4942943500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10617710000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    506765000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  11580340000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.754616                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.823305                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.766491                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.770543                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.858680                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.830799                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.705343                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.851991                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.760160                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.226821                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.300760                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.158155                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.186047                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.229872                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.245606                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.503900                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.226821                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.300760                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.268821                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.186047                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.229872                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.603113                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.520961                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.226821                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011494                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.300760                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.268821                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.725367                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.186047                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.229872                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.603113                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.635414                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.520961                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75388.092079                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 74924.144311                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75301.941166                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77293.762575                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76691.311612                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76868.063754                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139178.399491                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122081.191736                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 132015.385021                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.233652                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.519756                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.260556                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.246684                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.573647                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.386528                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.724203                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.866031                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.777075                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159528                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.224278                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.510645                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.275002                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.589716                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.528851                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.275002                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.589716                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.528851                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75581.070597                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75191.096178                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75507.917750                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77408.602151                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76636.504254                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76918.507609                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137998.651705                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122013.339860                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 131357.273606                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120609.033295                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127131.303276                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       132250                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124424.378109                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130152.542373                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 138273.544253                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126986.600345                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127372.812500                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137420.742603                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120609.033295                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133524.173335                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       132250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124424.378109                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123430.227678                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 137665.594300                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132916.920410                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122890.952820                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 136811.953365                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120609.033295                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133524.173335                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       132250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124424.378109                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123430.227678                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 137665.594300                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172134.394507                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99366.068286                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160713.619307                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155010.758304                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 78049.520767                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149556.028208                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164040.107304                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90084.558824                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 155773.635439                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132916.920410                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122890.952820                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 136811.953365                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183179.415161                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104915.405314                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169993.507491                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165294.760661                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84314.798788                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159264.837608                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174725.348868                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95905.563967                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 165242.219717                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               38908                       # Transaction distribution
-system.membus.trans_dist::ReadResp             215242                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30913                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30913                       # Transaction distribution
-system.membus.trans_dist::Writeback            138211                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            17281                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            73717                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40307                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           13440                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             39445                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            18844                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        176334                       # Transaction distribution
+system.membus.trans_dist::ReadReq               39045                       # Transaction distribution
+system.membus.trans_dist::ReadResp             215502                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31036                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31036                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       138282                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            17700                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            74095                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40637                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           14846                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40045                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19551                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        176457                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107934                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       674810                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       796498                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108909                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108909                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 905407                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162814                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14226                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       678987                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       801187                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108925                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108925                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 910112                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19258908                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19450490                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21767610                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           121785                       # Total snoops (count)
-system.membus.snoop_fanout::samples            591590                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28452                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19316644                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19509252                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                21827396                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           120950                       # Total snoops (count)
+system.membus.snoop_fanout::samples            593773                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  591590    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  593773    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              591590                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            91392000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              593773                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            91220498                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               24328                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11844500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12309500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1004304747                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1009592824                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1168943229                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1175000125                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64602498                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64118281                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2949,52 +2948,52 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests       982687                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       493902                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       158313                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          22110                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        21385                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          725                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              38912                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            507516                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30913                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30913                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           368484                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          106099                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           77161                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         40652                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         117813                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           21                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           21                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51062                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51062                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       468619                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests      1045381                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       564426                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       153843                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          20977                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        20003                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          974                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              39048                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            502086                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31036                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31036                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       405496                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          105907                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          110001                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43870                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         153871                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51160                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51160                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       463053                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1216476                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       257070                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1473546                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35115318                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4064004                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               39179322                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          452154                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1258731                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.293892                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.456806                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1307707                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       268101                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1575808                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36951502                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4337654                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               41289156                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          448414                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           942644                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.339212                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.475620                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 889525     70.67%     70.67% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 368481     29.27%     99.94% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    725      0.06%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 623862     66.18%     66.18% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 317808     33.71%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    974      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1258731                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          836264644                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             942644                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          904161512                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           342619                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           342622                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         685711951                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         693453750                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         211221475                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         213389277                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 481a34a0c..e97d068c7 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.858301                       # Number of seconds simulated
-sim_ticks                                2858301146500                       # Number of ticks simulated
-final_tick                               2858301146500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.858555                       # Number of seconds simulated
+sim_ticks                                2858554679500                       # Number of ticks simulated
+final_tick                               2858554679500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 158663                       # Simulator instruction rate (inst/s)
-host_op_rate                                   191838                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4049033168                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 629392                       # Number of bytes of host memory used
-host_seconds                                   705.92                       # Real time elapsed on the host
-sim_insts                                   112003872                       # Number of instructions simulated
-sim_ops                                     135422492                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 162796                       # Simulator instruction rate (inst/s)
+host_op_rate                                   196833                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4157408079                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 628580                       # Number of bytes of host memory used
+host_seconds                                   687.58                       # Real time elapsed on the host
+sim_insts                                   111935485                       # Number of instructions simulated
+sim_ops                                     135338943                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         7936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         7616                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1692928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9156716                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1708096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9149804                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10858604                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1692928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1692928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7945984                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10866540                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1708096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1708096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7937280                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7963508                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker          124                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7954804                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          119                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26452                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             143595                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26689                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             143487                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170187                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124156                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170311                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124020                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               128537                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2776                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               128401                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2664                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               592285                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3203552                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               597538                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3200850                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3798971                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          592285                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             592285                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2779967                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6131                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2786098                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2779967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2776                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3801411                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          597538                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             597538                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2776676                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6130                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2782806                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2776676                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2664                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              592285                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3209683                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              597538                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3206980                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6585070                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170187                       # Number of read requests accepted
-system.physmem.writeReqs                       128537                       # Number of write requests accepted
-system.physmem.readBursts                      170187                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     128537                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10884288                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7975936                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10858604                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7963508                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6584217                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170311                       # Number of read requests accepted
+system.physmem.writeReqs                       128401                       # Number of write requests accepted
+system.physmem.readBursts                      170311                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     128401                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10891264                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8640                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7967296                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10866540                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7954804                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      135                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          40806                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10600                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10887                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11108                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10980                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13553                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10410                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10585                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10816                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10327                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10604                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9912                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9123                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10363                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10770                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10067                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9962                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7842                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8249                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8721                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8464                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7420                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7583                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7625                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7909                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7872                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8104                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7451                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6976                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7788                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7975                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7387                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7258                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          49408                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10771                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10784                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10887                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10717                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14062                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10208                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10996                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10949                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9936                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10239                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9937                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9167                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10278                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11186                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10249                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9810                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8068                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8140                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8529                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8260                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7653                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7417                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7934                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8022                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7566                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7724                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7504                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7051                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7682                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8291                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7536                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7112                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          16                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2858300743000                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2858554234000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  169630                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169754                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124156                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    163271                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      6497                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       287                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124020                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163165                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      6708                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       291                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -159,159 +159,157 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1999                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2047                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2399                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                     6060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6722                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7541                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9555                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7722                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6841                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6509                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6410                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7385                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9757                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7720                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7133                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6581                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6447                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                      319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      141                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61607                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      306.136640                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     182.409953                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.199512                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22530     36.57%     36.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14842     24.09%     60.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6878     11.16%     71.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3579      5.81%     77.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2575      4.18%     81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2036      3.30%     85.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1091      1.77%     86.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1049      1.70%     88.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7027     11.41%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61607                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6204                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.410058                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      569.248357                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6203     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::34                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      225                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61347                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      307.404893                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.124702                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.856556                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22378     36.48%     36.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14856     24.22%     60.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6657     10.85%     71.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3691      6.02%     77.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2584      4.21%     81.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1979      3.23%     85.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1099      1.79%     86.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1109      1.81%     88.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6994     11.40%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61347                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6216                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.377091                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      569.055211                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6215     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6204                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6204                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.087685                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.454852                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.723718                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5415     87.28%     87.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              82      1.32%     88.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              29      0.47%     89.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             170      2.74%     91.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              36      0.58%     92.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             140      2.26%     94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              51      0.82%     95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               9      0.15%     95.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              26      0.42%     96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              17      0.27%     96.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.06%     96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.13%     96.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             160      2.58%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.03%     99.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              20      0.32%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.02%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.03%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.06%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.05%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.13%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.02%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.05%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6204                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1827154250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5015910500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    850335000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10743.73                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6216                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6215                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.029123                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.467033                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.100027                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5396     86.82%     86.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             102      1.64%     88.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              39      0.63%     89.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             172      2.77%     91.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              31      0.50%     92.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             152      2.45%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              39      0.63%     95.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.19%     95.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              17      0.27%     95.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              24      0.39%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.06%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.11%     96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             159      2.56%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.10%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.11%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.42%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             5      0.08%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.05%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6215                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1812035750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5002835750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    850880000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10648.01                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29493.73                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29398.01                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.79                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.78                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.50                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139389                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93694                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.96                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.17                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9568366.60                       # Average gap between requests
-system.physmem.pageHitRate                      79.09                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  240959880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  131476125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 693724200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                413508240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186689833200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            86986692810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1638672097500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1913828291955                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.570205                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2725916009250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95444700000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.83                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139556                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93759                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.01                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.30                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9569599.59                       # Average gap between requests
+system.physmem.pageHitRate                      79.17                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  241731000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  131896875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 697117200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                414817200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186706615680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            86828058675                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1638965418000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1913985654630                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.565069                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2726406946000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95453280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     36932994500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     36694429000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  224789040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  122652750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 632790600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                394055280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186689833200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            85302372735                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1640149571250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1913516064855                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.460970                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2728391286000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95444700000                       # Time in different power states
+system.physmem_1.actEnergy                  222037200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  121151250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 630247800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                391819680                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186706615680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            85116075930                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1640467157250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1913655104790                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.449434                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2728919167500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95453280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     34465013500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     34182085000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
@@ -331,15 +329,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                31040865                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16831531                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2506988                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18486474                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13317466                       # Number of BTB hits
+system.cpu.branchPred.lookups                31017399                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16820647                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2503170                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18419836                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13303162                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.038973                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7868005                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1514854                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.221935                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7872052                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1510670                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -370,55 +368,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     66489                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                66489                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43580                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22909                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples        66489                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           66489    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        66489                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7766                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12735.320628                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10552.887084                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8498.851872                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767         7759     99.91%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839            6      0.08%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7766                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples    513949000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0       513949000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total    513949000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6383     82.19%     82.19% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1383     17.81%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7766                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66489                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks                     65808                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                65808                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        42987                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22821                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples        65808                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           65808    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        65808                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7823                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12723.315863                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10567.827696                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8328.598591                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767         7817     99.92%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.06%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total         7823                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples    517922000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0       517922000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total    517922000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6431     82.21%     82.21% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1392     17.79%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7823                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        65808                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66489                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7766                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        65808                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7823                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7766                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        74255                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7823                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        73631                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24754555                       # DTB read hits
-system.cpu.dtb.read_misses                      59253                       # DTB read misses
-system.cpu.dtb.write_hits                    19441053                       # DTB write hits
-system.cpu.dtb.write_misses                      7236                       # DTB write misses
+system.cpu.dtb.read_hits                     24739501                       # DTB read hits
+system.cpu.dtb.read_misses                      58797                       # DTB read misses
+system.cpu.dtb.write_hits                    19434146                       # DTB write hits
+system.cpu.dtb.write_misses                      7011                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4351                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1268                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1795                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4354                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1307                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1800                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       764                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24813808                       # DTB read accesses
-system.cpu.dtb.write_accesses                19448289                       # DTB write accesses
+system.cpu.dtb.perms_faults                       763                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24798298                       # DTB read accesses
+system.cpu.dtb.write_accesses                19441157                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44195608                       # DTB hits
-system.cpu.dtb.misses                           66489                       # DTB misses
-system.cpu.dtb.accesses                      44262097                       # DTB accesses
+system.cpu.dtb.hits                          44173647                       # DTB hits
+system.cpu.dtb.misses                           65808                       # DTB misses
+system.cpu.dtb.accesses                      44239455                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -448,36 +446,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                      5448                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                 5448                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1          320                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         5128                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples         5448                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            5448    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         5448                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3191                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12717.173300                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10597.999219                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7372.723577                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         2455     76.94%     76.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          735     23.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks                      5439                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 5439                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          319                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         5120                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples         5439                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            5439    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         5439                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3184                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12910.175879                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10824.296487                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7389.330309                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         2456     77.14%     77.14% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          727     22.83%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3191                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples    513294500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       513294500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total    513294500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2881     90.29%     90.29% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           310      9.71%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3191                       # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::total         3184                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples    517267500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       517267500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total    517267500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2874     90.26%     90.26% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           310      9.74%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3184                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5448                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total         5448                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5439                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         5439                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3191                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3191                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total         8639                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     57598121                       # ITB inst hits
-system.cpu.itb.inst_misses                       5448                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3184                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3184                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         8623                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     57560838                       # ITB inst hits
+system.cpu.itb.inst_misses                       5439                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -486,127 +484,127 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2979                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2972                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8499                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8472                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57603569                       # ITB inst accesses
-system.cpu.itb.hits                          57598121                       # DTB hits
-system.cpu.itb.misses                            5448                       # DTB misses
-system.cpu.itb.accesses                      57603569                       # DTB accesses
-system.cpu.numCycles                        332010047                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 57566277                       # ITB inst accesses
+system.cpu.itb.hits                          57560838                       # DTB hits
+system.cpu.itb.misses                            5439                       # DTB misses
+system.cpu.itb.accesses                      57566277                       # DTB accesses
+system.cpu.numCycles                        333233745                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   112003872                       # Number of instructions committed
-system.cpu.committedOps                     135422492                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7777324                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      3034                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5384653012                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.964273                       # CPI: cycles per instruction
-system.cpu.ipc                               0.337351                       # IPC: instructions per cycle
+system.cpu.committedInsts                   111935485                       # Number of instructions committed
+system.cpu.committedOps                     135338943                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7768370                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                   5383936377                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.977016                       # CPI: cycles per instruction
+system.cpu.ipc                               0.335907                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     3034                       # number of quiesce instructions executed
-system.cpu.tickCycles                       227998615                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       104011432                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            840949                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.900791                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42597434                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            841461                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.623183                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         590729500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.900791                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999806                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999806                       # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
+system.cpu.tickCycles                       228546607                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       104687138                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            843126                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.899809                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42573204                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            843638                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.463829                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         594757500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.899809                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          362                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          358                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         176149332                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        176149332                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23058407                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23058407                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18275243                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18275243                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       356879                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        356879                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443776                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443776                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460246                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460246                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41333650                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41333650                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41690529                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41690529                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       492651                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        492651                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       547770                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       547770                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       169693                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       169693                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22295                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22295                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         176066237                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        176066237                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23041742                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23041742                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18267850                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18267850                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       356487                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        356487                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443903                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443903                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460330                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460330                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41309592                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41309592                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41666079                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41666079                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       494543                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        494543                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       548727                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       548727                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       169803                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       169803                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22255                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22255                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      1040421                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1040421                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1210114                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1210114                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   8002189000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   8002189000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  35630203980                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  35630203980                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    292207000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    292207000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      1043270                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1043270                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1213073                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1213073                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8036420500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8036420500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  35621632480                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  35621632480                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    292921000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    292921000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  43632392980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  43632392980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  43632392980                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  43632392980                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23551058                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23551058                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18823013                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18823013                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       526572                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       526572                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466071                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466071                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460248                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460248                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42374071                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42374071                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42900643                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42900643                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020918                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.020918                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029101                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029101                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.322260                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.322260                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047836                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047836                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data  43658052980                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  43658052980                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  43658052980                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  43658052980                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23536285                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23536285                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     18816577                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     18816577                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       526290                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       526290                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466158                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       466158                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460332                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460332                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42352862                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42352862                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42879152                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42879152                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021012                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.021012                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029162                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029162                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.322642                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.322642                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047741                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047741                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024553                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024553                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.028207                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.028207                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16243.119368                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16243.119368                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65045.920697                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65045.920697                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13106.391568                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13106.391568                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024633                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024633                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028291                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028291                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16250.195635                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16250.195635                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64916.857527                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64916.857527                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13162.031004                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13162.031004                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41937.247499                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41937.247499                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36056.431857                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 36056.431857                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41847.319467                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41847.319467                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35989.633748                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35989.633748                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          277                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                23                       # number of cycles access was blocked
@@ -615,145 +613,145 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.043478
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       698521                       # number of writebacks
-system.cpu.dcache.writebacks::total            698521                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76580                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        76580                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249277                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       249277                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14066                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14066                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       325857                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       325857                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       325857                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       325857                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       416071                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       416071                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298493                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298493                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121470                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       121470                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8229                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8229                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       700279                       # number of writebacks
+system.cpu.dcache.writebacks::total            700279                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76721                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        76721                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249708                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       249708                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14008                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14008                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       326429                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       326429                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       326429                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       326429                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       417822                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       417822                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299019                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299019                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121366                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       121366                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8247                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8247                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       714564                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       714564                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       836034                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       836034                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31128                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total        31128                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27583                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        27583                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total        58711                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6493922500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6493922500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19218375500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19218375500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1715298500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1715298500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    114624000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    114624000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       716841                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       716841                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       838207                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       838207                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6533285000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6533285000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19191527000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19191527000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1710229000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1710229000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    114982000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    114982000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25712298000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25712298000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27427596500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27427596500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5937313500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5937313500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4787315000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4787315000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10724628500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10724628500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017667                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017667                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015858                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015858                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230681                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230681                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017656                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017656                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25724812000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25724812000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27435041000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27435041000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277494000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277494000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5085199500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5085199500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11362693500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11362693500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017752                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017752                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015891                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015891                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230607                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230607                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017691                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017691                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016863                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016863                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019488                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019488                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15607.726806                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15607.726806                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64384.677363                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64384.677363                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14121.169836                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14121.169836                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13929.274517                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13929.274517                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016925                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016925                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019548                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019548                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15636.527038                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15636.527038                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64181.630599                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64181.630599                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.500091                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.500091                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13942.282042                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13942.282042                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35983.198146                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35983.198146                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32806.795537                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 32806.795537                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190738.675790                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190738.675790                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173560.345140                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173560.345140                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182668.128630                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182668.128630                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35886.356947                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35886.356947                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32730.627399                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32730.627399                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201654.159974                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201654.159974                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184353.230133                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184353.230133                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193526.135164                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193526.135164                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           2897329                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.212489                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54691304                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2897841                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.873121                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       18295812500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.212489                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998462                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998462                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           2897280                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.208865                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54654096                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2897792                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.860600                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       18409362500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.208865                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998455                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998455                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60487009                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60487009                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     54691304                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54691304                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54691304                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54691304                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54691304                       # number of overall hits
-system.cpu.icache.overall_hits::total        54691304                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2897853                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2897853                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2897853                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        2897853                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      2897853                       # number of overall misses
-system.cpu.icache.overall_misses::total       2897853                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  40491792500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  40491792500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  40491792500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  40491792500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  40491792500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  40491792500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57589157                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57589157                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57589157                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57589157                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57589157                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57589157                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050319                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050319                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050319                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::cpu.inst     0.050319                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050319                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13973.031931                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13973.031931                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13973.031931                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13973.031931                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.031931                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13973.031931                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60449703                       # Number of tag accesses
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+system.cpu.icache.ReadReq_hits::cpu.inst     54654096                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst  40494431000                       # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_accesses::cpu.inst     57551900                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_avg_miss_latency::total 13974.178723                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13974.178723                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13974.178723                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13974.178723                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13974.178723                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -762,212 +760,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2897853                       # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::cpu.inst      2897853                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      2897853                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3490                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total         3490                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3490                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total         3490                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  37593940500                       # number of ReadReq MSHR miss cycles
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-system.cpu.icache.demand_mshr_miss_latency::total  37593940500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  37593940500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  37593940500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    450883500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    450883500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    450883500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    450883500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050319                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total     0.050319                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050319                       # mshr miss rate for overall accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12973.032276                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12973.032276                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.032276                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.032276                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.032276                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.032276                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129192.979943                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129192.979943                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129192.979943                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129192.979943                       # average overall mshr uncacheable latency
+system.cpu.icache.writebacks::writebacks      2897280                       # number of writebacks
+system.cpu.icache.writebacks::total           2897280                       # number of writebacks
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+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3763                       # number of overall MSHR uncacheable misses
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+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    485921500                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050351                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12974.179068                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12974.179068                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12974.179068                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12974.179068                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96606                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65026.172791                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            7027132                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161852                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            43.417023                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96402                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65018.831836                       # Cycle average of tags in use
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+system.cpu.l2cache.tags.sampled_refs           161646                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            43.490819                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 47537.333831                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    67.598904                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000505                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 12131.683782                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5289.555770                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.725362                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001031                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 47317.372704                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    63.574942                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000511                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 12247.402145                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5390.481534                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.722006                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000970                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.185115                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.080712                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992221                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           50                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65196                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994812                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007923                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007923                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026106                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026106                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001663                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000216                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007923                       # miss rate for demand accesses
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+system.cpu.l2cache.demand_miss_rate::total     0.044084                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001663                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000216                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007923                       # miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141340.336134                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       132500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total       135876                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1122.437775                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1122.437775                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 141266.666667                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1120.431287                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1120.431287                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128205.063870                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128205.063870                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130816.697112                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130816.697112                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132385.203722                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132385.203722                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135903.225806                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128126.602050                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128126.602050                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130563.066202                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130563.066202                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132281.505843                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132281.505843                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141340.336134                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130816.697112                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128613.150415                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 128919.345358                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135903.225806                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130563.066202                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128535.491712                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 128821.182196                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141340.336134                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130816.697112                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128613.150415                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 128919.345358                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130563.066202                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128535.491712                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 128821.182196                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -976,188 +980,189 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        87966                       # number of writebacks
-system.cpu.l2cache.writebacks::total            87966                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           19                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           19                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          141                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          141                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          141                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          160                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          141                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          160                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          124                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        87830                       # number of writebacks
+system.cpu.l2cache.writebacks::total            87830                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           23                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           23                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          142                       # number of ReadSharedReq MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          125                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2732                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2732                       # number of UpgradeReq MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131125                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       131125                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22973                       # number of ReadCleanReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       122500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15734500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    193275000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    193275000                       # number of UpgradeReq MSHR miss cycles
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 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
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 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10018268500                       # number of overall MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000215                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001626                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.983087                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.983087                       # mshr miss rate for UpgradeReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001663                       # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001575                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982406                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982406                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.443411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007928                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007928                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025735                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025735                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000215                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007928                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172517                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.044093                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001717                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000215                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007928                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172517                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.044093                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.441961                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.441961                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007915                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007915                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025846                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025846                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001663                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000216                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007915                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.171957                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.044041                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001663                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000216                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007915                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.171957                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.044041                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total       125876                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70744.875549                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70744.875549                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131266.666667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70755.482456                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70755.482456                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118205.063870                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118205.063870                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120864.906630                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120864.906630                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122468.814525                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122468.814525                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118126.602050                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118126.602050                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120631.926582                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120631.926582                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122428.263482                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122428.263482                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120864.906630                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118617.575945                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118929.787601                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120631.926582                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118546.138204                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118839.765779                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120864.906630                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118617.575945                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118929.787601                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113624.068768                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178237.262272                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 171723.308683                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162059.928217                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162059.928217                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113624.068768                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170636.993068                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167438.087812                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120631.926582                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118546.138204                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118839.765779                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189152.184388                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180996.919153                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172852.051914                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172852.051914                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181494.336955                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177400.907534                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      7509435                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      3770131                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58870                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          575                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          575                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      7513660                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      3772219                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58915                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          590                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          590                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         134592                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3578420                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         27583                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        27583                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       822692                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2989768                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2779                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         134081                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3579527                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       824300                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      2845639                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       144382                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2785                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2781                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295719                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295719                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      2897853                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       545999                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2787                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296239                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296239                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      2897804                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       547664                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8648477                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2639755                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15227                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       161605                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          11465064                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    185683904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98756893                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18604                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       288828                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          284748229                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      192861                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      7812074                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.018867                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.136054                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8648746                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2646408                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15180                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160178                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          11470512                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    367819456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99009385                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18484                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       286196                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          467133521                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      192542                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4075210                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.021724                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.145782                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            7664687     98.11%     98.11% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             147387      1.89%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3986679     97.83%     97.83% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              88531      2.17%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        7812074                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4533598000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       377377                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4075210                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     7434516500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       380377                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4352382759                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4352877441                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1308632806                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1312009118                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      10576000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      10561994                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      89410974                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      88663416                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
@@ -1213,63 +1218,63 @@ system.iobus.pkt_size_system.bridge.master::total       159125
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             46504000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                89000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               569500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               51500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6052000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              168000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            33698500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              124500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186368011                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           186339520                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               37500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.036757                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.036928                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         274667845000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.036757                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064797                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064797                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         274875272000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.036928                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064808                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064808                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1283,14 +1288,14 @@ system.iocache.demand_misses::realview.ide          234                       #
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29104877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29104877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4697807134                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4697807134                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     29104877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     29104877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     29104877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     29104877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     29051377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     29051377                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4719366143                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4719366143                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     29051377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     29051377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     29051377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     29051377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1307,19 +1312,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124379.816239                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124379.816239                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129687.696941                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129687.696941                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124379.816239                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124379.816239                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124379.816239                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124379.816239                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124151.183761                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124151.183761                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130282.855096                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130282.855096                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124151.183761                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124151.183761                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124151.183761                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124151.183761                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           731                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   70                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.442857                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1333,14 +1338,14 @@ system.iocache.demand_mshr_misses::realview.ide          234
 system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17404877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17404877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2886607134                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2886607134                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17404877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17404877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17404877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17404877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17351377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17351377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2908166143                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2908166143                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17351377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17351377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17351377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17351377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1349,68 +1354,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74379.816239                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74379.816239                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79687.696941                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79687.696941                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74379.816239                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74379.816239                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74379.816239                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74379.816239                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74151.183761                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74151.183761                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80282.855096                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80282.855096                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74151.183761                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74151.183761                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74151.183761                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74151.183761                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               34618                       # Transaction distribution
-system.membus.trans_dist::ReadResp              71995                       # Transaction distribution
-system.membus.trans_dist::WriteReq              27583                       # Transaction distribution
-system.membus.trans_dist::WriteResp             27583                       # Transaction distribution
-system.membus.trans_dist::Writeback            124156                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8653                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4582                       # Transaction distribution
+system.membus.trans_dist::ReadReq               34893                       # Transaction distribution
+system.membus.trans_dist::ReadResp              72333                       # Transaction distribution
+system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
+system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       124020                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8585                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4599                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4584                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129275                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129275                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         37377                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4601                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129063                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129063                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         37440                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455163                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562725                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455241                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562809                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 671625                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 671709                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16504992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16668765                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16504224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16668009                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18985885                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18985129                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              506                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402707                       # Request fanout histogram
+system.membus.snoop_fanout::samples            402632                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402707    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402632    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402707                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87547000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402632                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87539000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1701500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1722000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           878616291                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           878086902                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          998538415                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          999035643                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64594078                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64196432                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 51e8b32a5..ce335443d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.832619                       # Number of seconds simulated
-sim_ticks                                2832618668500                       # Number of ticks simulated
-final_tick                               2832618668500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.832918                       # Number of seconds simulated
+sim_ticks                                2832917624000                       # Number of ticks simulated
+final_tick                               2832917624000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65632                       # Simulator instruction rate (inst/s)
-host_op_rate                                    79607                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1643300725                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 630388                       # Number of bytes of host memory used
-host_seconds                                  1723.74                       # Real time elapsed on the host
-sim_insts                                   113133035                       # Number of instructions simulated
-sim_ops                                     137220830                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  67788                       # Simulator instruction rate (inst/s)
+host_op_rate                                    82221                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1698232616                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 630604                       # Number of bytes of host memory used
+host_seconds                                  1668.16                       # Real time elapsed on the host
+sim_insts                                   113081477                       # Number of instructions simulated
+sim_ops                                     137157144                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         1600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1321728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9386216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1316032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9392488                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10710952                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1321728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1321728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8026688                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10711336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1316032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1316032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8002368                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8044212                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           25                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22899                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147180                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8019892                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22810                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             147278                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170126                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          125417                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170132                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          125037                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129798                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            565                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               466610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3313618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               129418                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            474                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            181                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               464550                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3315482                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3781290                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          466610                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466610                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2833663                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6187                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2839850                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2833663                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           565                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              466610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3319804                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3781026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          464550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             464550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2824780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2830965                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2824780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           181                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              464550                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3321668                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6621140                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170127                       # Number of read requests accepted
-system.physmem.writeReqs                       129798                       # Number of write requests accepted
-system.physmem.readBursts                      170127                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129798                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10879424                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8704                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8056320                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10711016                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8044212                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      136                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6611992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170133                       # Number of read requests accepted
+system.physmem.writeReqs                       129418                       # Number of write requests accepted
+system.physmem.readBursts                      170133                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129418                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10877696                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10816                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8031936                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10711400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8019892                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      169                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          40796                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11277                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10595                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11086                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11282                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12957                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9975                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10510                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10855                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10363                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10082                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10269                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9303                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9940                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11053                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10302                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10142                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8501                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7938                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8637                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8770                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7610                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7376                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7709                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8071                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7782                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7594                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7680                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6982                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7590                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8396                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7757                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7487                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          48557                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11298                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10506                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10925                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11199                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12883                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10202                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10845                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11219                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10577                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10527                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10037                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8948                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9970                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10631                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9988                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10209                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8496                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7860                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8364                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8532                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7663                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7568                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8029                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8274                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8070                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7909                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7508                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6646                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7551                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8006                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7465                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7558                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832618457500                       # Total gap between requests
+system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2832917392000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166575                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166581                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125417                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150718                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16419                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 125037                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150592                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16496                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -159,155 +159,156 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5703                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7455                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6629                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2033                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5707                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7704                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7922                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7435                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7511                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6870                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6611                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6539                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       47                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      304.834026                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.217682                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.637512                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23314     37.53%     37.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14709     23.68%     61.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6728     10.83%     72.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3491      5.62%     77.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2622      4.22%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1595      2.57%     84.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1577      2.54%     86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1006      1.62%     88.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7076     11.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62118                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6287                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.034993                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      563.024200                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6286     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::59                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        62145                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      304.281406                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.810971                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.663684                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23300     37.49%     37.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14989     24.12%     61.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6559     10.55%     72.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3523      5.67%     77.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2511      4.04%     81.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1609      2.59%     84.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1592      2.56%     87.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1065      1.71%     88.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6997     11.26%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62145                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6266                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.121768                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      563.971651                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6265     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6287                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6287                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.022268                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.451800                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.249481                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5461     86.86%     86.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             111      1.77%     88.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              41      0.65%     89.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             176      2.80%     92.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              30      0.48%     92.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             149      2.37%     94.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              46      0.73%     95.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               9      0.14%     95.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              13      0.21%     96.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              18      0.29%     96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.08%     96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.05%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             163      2.59%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.06%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               8      0.13%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              20      0.32%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.05%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.67% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6266                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6266                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.028567                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.454463                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.210745                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5460     87.14%     87.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             110      1.76%     88.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              30      0.48%     89.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             168      2.68%     92.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              26      0.41%     92.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             137      2.19%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              53      0.85%     95.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              15      0.24%     95.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              11      0.18%     95.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              21      0.34%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.10%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.11%     96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             165      2.63%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.08%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              23      0.37%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.66% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-115             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            13      0.21%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.06%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6287                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2109686750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5297018000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849955000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12410.58                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            12      0.19%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6266                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2116809750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5303634750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849820000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12454.46                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31160.58                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31204.46                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.78                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.84                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.83                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.90                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139766                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93986                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.22                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.64                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9444422.63                       # Average gap between requests
-system.physmem.pageHitRate                      79.00                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  244301400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  133299375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 690588600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                418685760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185012602320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83544770610                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626283896000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896328144065                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.462100                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705327267750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94587220000                       # Time in different power states
+system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139542                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93775                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.70                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9457212.27                       # Average gap between requests
+system.physmem.pageHitRate                      78.96                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  246546720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  134524500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 694792800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                419813280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185031927600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83588992920                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626422631000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1896539228820                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.466691                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705562728250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94597100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32700163500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32757782250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  225310680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  122937375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 635333400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                397016640                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185012602320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82147816890                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627509294000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896050311305                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.364017                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2707380849000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94587220000                       # Time in different power states
+system.physmem_1.actEnergy                  223269480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  121823625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 630918600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                393420240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185031927600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            81878542335                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1627923026250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1896202928130                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.347979                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2708066096500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94597100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30650586000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30247332250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
@@ -327,15 +328,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46909632                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24036779                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233520                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29533462                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21344460                       # Number of BTB hits
+system.cpu.branchPred.lookups                46858822                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24018425                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1233385                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29501817                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21322160                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.272123                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11742450                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33774                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.274057                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11724285                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33905                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -366,45 +367,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks              9696                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksShort         9696                       # Table walker walks initiated with short descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples         9696                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0         9696    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total         9696                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks              9701                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksShort         9701                       # Table walker walks initiated with short descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples         9701                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0         9701    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total         9701                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.dtb.walker.walksPending::samples    375751000                       # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::0    375751000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::total    375751000                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K         6227     82.67%     82.67% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::1M         1305     17.33%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total         7532                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9696                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K         6238     82.77%     82.77% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::1M         1299     17.23%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total         7537                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9701                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9696                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7532                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9701                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7537                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7532                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total        17228                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7537                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total        17238                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             24584215                       # DTB read hits
-system.cpu.checker.dtb.read_misses               8281                       # DTB read misses
-system.cpu.checker.dtb.write_hits            19636610                       # DTB write hits
-system.cpu.checker.dtb.write_misses              1415                       # DTB write misses
+system.cpu.checker.dtb.read_hits             24572028                       # DTB read hits
+system.cpu.checker.dtb.read_misses               8280                       # DTB read misses
+system.cpu.checker.dtb.write_hits            19630755                       # DTB write hits
+system.cpu.checker.dtb.write_misses              1421                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid               0                       # Number of times TLB was flushed by ASID
 system.cpu.checker.dtb.flush_entries             4283                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           1650                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           1642                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         24592496                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        19638025                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         24580308                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        19632176                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  44220825                       # DTB hits
-system.cpu.checker.dtb.misses                    9696                       # DTB misses
-system.cpu.checker.dtb.accesses              44230521                       # DTB accesses
+system.cpu.checker.dtb.hits                  44202783                       # DTB hits
+system.cpu.checker.dtb.misses                    9701                       # DTB misses
+system.cpu.checker.dtb.accesses              44212484                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -452,7 +453,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst         3170                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total         3170                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin::total         7995                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            115833137                       # ITB inst hits
+system.cpu.checker.itb.inst_hits            115778479                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4825                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -469,11 +470,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        115837962                       # ITB inst accesses
-system.cpu.checker.itb.hits                 115833137                       # DTB hits
+system.cpu.checker.itb.inst_accesses        115783304                       # ITB inst accesses
+system.cpu.checker.itb.hits                 115778479                       # DTB hits
 system.cpu.checker.itb.misses                    4825                       # DTB misses
-system.cpu.checker.itb.accesses             115837962                       # DTB accesses
-system.cpu.checker.numCycles                139072975                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses             115783304                       # DTB accesses
+system.cpu.checker.numCycles                139006189                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -505,79 +506,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     71741                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                71741                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29467                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22287                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19987                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        51754                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   426.227924                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2584.933278                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-8191        50562     97.70%     97.70% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-16383          857      1.66%     99.35% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-24575          291      0.56%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-32767           20      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-40959           10      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-49151            9      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::90112-98303            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        51754                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17702                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9865.120013                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8642.768996                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17474     98.71%     98.71% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535          221      1.25%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                     71435                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                71435                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29241                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22400                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19794                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        51641                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   426.153638                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2576.445985                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        49864     96.56%     96.56% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          585      1.13%     97.69% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          525      1.02%     98.71% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383          340      0.66%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479           52      0.10%     99.47% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          220      0.43%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671           14      0.03%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::28672-32767           10      0.02%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            8      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151           11      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::53248-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::57344-61439            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::61440-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        51641                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17522                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11533.700491                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9159.086359                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8173.463802                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        17339     98.96%     98.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535          177      1.01%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-360447            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17702                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131083168816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.618031                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.493607                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131025996816     99.96%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      38371000      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       7847500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6991500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1099000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       491500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1479000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       882500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        17522                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131382086816                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.616564                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.493575                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  131327318816     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      37570000      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       7000000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6185500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1198500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       643000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1366500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       794500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::16-17        10000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131083168816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6361     82.57%     82.57% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1343     17.43%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7704                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71741                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131382086816                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6381     82.69%     82.69% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1336     17.31%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7717                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71435                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71741                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7704                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71435                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7717                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7704                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        79445                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7717                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        79152                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25458814                       # DTB read hits
-system.cpu.dtb.read_misses                      61805                       # DTB read misses
-system.cpu.dtb.write_hits                    19912938                       # DTB write hits
-system.cpu.dtb.write_misses                      9936                       # DTB write misses
+system.cpu.dtb.read_hits                     25445516                       # DTB read hits
+system.cpu.dtb.read_misses                      61525                       # DTB read misses
+system.cpu.dtb.write_hits                    19906341                       # DTB write hits
+system.cpu.dtb.write_misses                      9910                       # DTB write misses
 system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4319                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       361                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2196                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4317                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       358                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2185                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1314                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25520619                       # DTB read accesses
-system.cpu.dtb.write_accesses                19922874                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1330                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25507041                       # DTB read accesses
+system.cpu.dtb.write_accesses                19916251                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45371752                       # DTB hits
-system.cpu.dtb.misses                           71741                       # DTB misses
-system.cpu.dtb.accesses                      45443493                       # DTB accesses
+system.cpu.dtb.hits                          45351857                       # DTB hits
+system.cpu.dtb.misses                           71435                       # DTB misses
+system.cpu.dtb.accesses                      45423292                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -607,54 +613,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     11944                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                11944                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3964                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7740                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore          240                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11704                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   651.102187                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2927.030280                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        11135     95.14%     95.14% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191          148      1.26%     96.40% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          183      1.56%     97.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383           77      0.66%     98.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479          110      0.94%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           40      0.34%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767            6      0.05%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11704                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3569                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 13485.850378                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  8473.200886                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         2612     73.19%     73.19% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          916     25.67%     98.85% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151           38      1.06%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-147455            3      0.08%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3569                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23708925416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.962784                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.189405                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       882867000      3.72%      3.72% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     22825544916     96.27%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2          513500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23708925416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          3010     90.42%     90.42% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           319      9.58%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3329                       # Table walker page sizes translated
+system.cpu.itb.walker.walks                     11899                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                11899                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3941                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7737                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore          221                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11678                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   616.629560                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2880.318774                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        11122     95.24%     95.24% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191          159      1.36%     96.60% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          193      1.65%     98.25% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383           62      0.53%     98.78% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           98      0.84%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           32      0.27%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total        11678                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3549                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12870.386024                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10191.624224                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  8688.844550                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         2600     73.26%     73.26% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          892     25.13%     98.39% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151           55      1.55%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3549                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  24007842416                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.962955                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.189019                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       889977000      3.71%      3.71% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     23117314916     96.29%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          493000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           57500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  24007842416                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          3008     90.38%     90.38% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           320      9.62%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3328                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11944                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        11944                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11899                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        11899                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3329                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3329                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        15273                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66274552                       # ITB inst hits
-system.cpu.itb.inst_misses                      11944                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3328                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3328                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        15227                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66219818                       # ITB inst hits
+system.cpu.itb.inst_misses                      11899                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -663,143 +670,143 @@ system.cpu.itb.flush_tlb                          128                       # Nu
 system.cpu.itb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3096                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3095                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2199                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2205                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66286496                       # ITB inst accesses
-system.cpu.itb.hits                          66274552                       # DTB hits
-system.cpu.itb.misses                           11944                       # DTB misses
-system.cpu.itb.accesses                      66286496                       # DTB accesses
-system.cpu.numCycles                        277645869                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66231717                       # ITB inst accesses
+system.cpu.itb.hits                          66219818                       # DTB hits
+system.cpu.itb.misses                           11899                       # DTB misses
+system.cpu.itb.accesses                      66231717                       # DTB accesses
+system.cpu.numCycles                        278809396                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104816225                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184723631                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46909632                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33086910                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     160672113                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6155878                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     195967                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 9078                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        333869                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       563276                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          182                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66274743                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1128462                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5280                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          269668649                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.835474                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.219488                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104752228                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184594753                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46858822                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33046445                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     161837102                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6149420                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     189977                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 9772                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        357687                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       560902                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          181                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66220013                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1133469                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5179                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          270782559                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.831431                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.217897                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                170383279     63.18%     63.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29238814     10.84%     74.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14077384      5.22%     79.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55969172     20.75%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                171565839     63.36%     63.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29222654     10.79%     74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14067780      5.20%     79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55926286     20.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            269668649                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168955                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.665321                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77872075                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             120737431                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64613956                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3845227                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2599960                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3423402                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                486431                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157413712                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3694235                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2599960                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83719189                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11483136                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       75823110                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62612793                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33430461                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146780851                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                948885                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                459435                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  64832                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  17222                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30677805                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150464365                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678641295                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164414257                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10882                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141779508                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8684854                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2843849                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2647501                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13873635                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26407527                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21301019                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1697624                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2214062                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143514940                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2121406                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143299756                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            270446                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8415512                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14711754                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125531                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     269668649                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.531392                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.866832                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            270782559                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.168068                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.662082                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77849645                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             121907615                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64584092                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3844418                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2596789                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3423202                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                486322                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157325754                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3698413                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2596789                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83693975                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11775859                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76672657                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62585691                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33457588                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146699029                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                957260                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                452831                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  63761                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  16550                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30707740                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150373398                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678238170                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164317610                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10889                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141712294                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8661101                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2840653                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2644485                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13863116                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26394295                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21292545                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1689185                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2215742                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143439670                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2121732                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143229007                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            270292                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8404254                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14686510                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125844                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270782559                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.528945                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.865530                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           181393020     67.27%     67.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45154562     16.74%     84.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            32029362     11.88%     95.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10280384      3.81%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              811287      0.30%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                  34      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           182544969     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45137079     16.67%     84.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32020155     11.83%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10269839      3.79%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              810484      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       269668649                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270782559                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7353326     32.78%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     31      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5633689     25.11%     57.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9445566     42.11%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7336568     32.74%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5631848     25.13%     57.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9441706     42.13%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95980665     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113853      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95930740     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               113813      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -823,101 +830,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8580      0.01%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26189090     18.28%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21005231     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8576      0.01%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26175663     18.28%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20997878     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143299756                       # Type of FU issued
-system.cpu.iq.rate                           0.516124                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22432612                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156543                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          578935614                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         154057233                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140187198                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35605                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13116                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11364                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165706663                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23368                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           323603                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143229007                       # Type of FU issued
+system.cpu.iq.rate                           0.513717                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22410154                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156464                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          579885434                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153971015                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140120635                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35585                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13122                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11367                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165613479                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23345                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           322744                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1496259                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          507                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18537                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       706534                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1495175                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          502                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18526                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       703988                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88309                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6292                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        87827                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6407                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2599960                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1252151                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                541403                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145836919                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2596789                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1243570                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                532137                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145762333                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26407527                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21301019                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096274                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  18146                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                505783                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18537                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317326                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471404                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               788730                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142356745                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25786743                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            871381                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26394295                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21292545                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1096246                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17995                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                497968                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18526                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317449                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471196                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               788645                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142286885                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25773498                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            870795                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200573                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46662722                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26519669                       # Number of branches executed
-system.cpu.iew.exec_stores                   20875979                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.512728                       # Inst execution rate
-system.cpu.iew.wb_sent                      141970613                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140198562                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63271886                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95802115                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        200931                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46642508                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26501737                       # Number of branches executed
+system.cpu.iew.exec_stores                   20869010                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.510337                       # Inst execution rate
+system.cpu.iew.wb_sent                      141900432                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140132002                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63223126                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95712973                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.504955                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660444                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.502609                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660549                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7621436                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995875                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755541                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    266730475                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.515036                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.120154                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7603118                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995888                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755464                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    267848804                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.512648                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.117834                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    193314140     72.48%     72.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43245727     16.21%     88.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15468136      5.80%     94.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4389606      1.65%     96.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6355153      2.38%     98.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1682348      0.63%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       799161      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       412032      0.15%     99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1064172      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    194453826     72.60%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43232556     16.14%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15468323      5.78%     94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4394328      1.64%     96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6341907      2.37%     98.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1685586      0.63%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       800919      0.30%     99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       412081      0.15%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1059278      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    266730475                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113287940                       # Number of instructions committed
-system.cpu.commit.committedOps              137375735                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    267848804                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113236382                       # Number of instructions committed
+system.cpu.commit.committedOps              137312049                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45505753                       # Number of memory references committed
-system.cpu.commit.loads                      24911268                       # Number of loads committed
-system.cpu.commit.membars                      814898                       # Number of memory barriers committed
-system.cpu.commit.branches                   26034583                       # Number of branches committed
+system.cpu.commit.refs                       45487677                       # Number of memory references committed
+system.cpu.commit.loads                      24899120                       # Number of loads committed
+system.cpu.commit.membars                      814929                       # Number of memory barriers committed
+system.cpu.commit.branches                   26016406                       # Number of branches committed
 system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120199859                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4887749                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120142081                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4881652                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91748615     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          112788      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91703052     66.78%     66.78% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          112745      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -941,501 +948,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8579      0.01%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8575      0.01%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24911268     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20594485     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24899120     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20588557     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137375735                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1064172                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    388465780                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292930075                       # The number of ROB writes
-system.cpu.timesIdled                          888709                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7977220                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5387591469                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113133035                       # Number of Instructions Simulated
-system.cpu.committedOps                     137220830                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.454154                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.454154                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.407472                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.407472                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155797969                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88612712                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9524                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137312049                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1059278                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    389547304                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292761659                       # The number of ROB writes
+system.cpu.timesIdled                          892855                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         8026837                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5387025853                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113081477                       # Number of Instructions Simulated
+system.cpu.committedOps                     137157144                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.465562                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.465562                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.405587                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.405587                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155726558                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88564581                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9527                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502896978                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53174784                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               347572280                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521694                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            840044                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.925899                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40105851                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            840556                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.713479                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 502647576                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53157224                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               348272878                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521665                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            837515                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.925653                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40092431                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            838027                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.841455                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.925899                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.925653                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179336842                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179336842                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23308523                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23308523                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15546666                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15546666                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       346021                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        346021                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441431                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441431                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460353                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460353                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38855189                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38855189                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39201210                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39201210                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       708825                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        708825                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3606988                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3606988                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177865                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177865                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27388                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27388                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4315813                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4315813                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4493678                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4493678                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11757743000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11757743000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232345213174                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232345213174                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    375611000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    375611000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       278000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       278000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244102956174                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244102956174                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244102956174                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244102956174                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24017348                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24017348                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19153654                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19153654                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523886                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523886                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468819                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468819                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460358                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460358                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43171002                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43171002                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43694888                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43694888                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029513                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029513                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188319                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188319                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339511                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339511                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058419                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058419                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099970                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099970                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102842                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102842                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16587.652806                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16587.652806                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64415.299739                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64415.299739                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13714.436980                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13714.436980                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55600                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55600                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56560.132743                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56560.132743                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54321.416927                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54321.416927                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       869823                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses         179262738                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179262738                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23296604                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23296604                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15545032                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15545032                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345927                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345927                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441660                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441660                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460331                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460331                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38841636                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38841636                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39187563                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39187563                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       708765                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        708765                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3602792                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3602792                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177926                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177926                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        27128                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        27128                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      4311557                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4311557                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4489483                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4489483                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11704891500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11704891500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 232547539185                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 232547539185                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    374670000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    374670000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       305000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       305000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 244252430685                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 244252430685                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 244252430685                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 244252430685                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24005369                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24005369                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19147824                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19147824                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523853                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523853                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468788                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468788                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460338                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460338                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43153193                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43153193                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43677046                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43677046                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029525                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029525                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188157                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188157                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339649                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339649                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057868                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057868                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000015                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000015                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.099913                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.099913                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102788                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102788                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16514.488582                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16514.488582                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64546.479282                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64546.479282                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13811.191389                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13811.191389                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56650.632401                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56650.632401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54405.469557                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54405.469557                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       871729                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6812                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6864                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.689812                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.000146                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       698262                       # number of writebacks
-system.cpu.dcache.writebacks::total            698262                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       293573                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       293573                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307033                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3307033                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18933                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18933                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3600606                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3600606                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3600606                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3600606                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       415252                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       415252                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299955                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299955                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119671                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119671                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8455                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8455                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       715207                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       715207                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       834878                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       834878                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       695593                       # number of writebacks
+system.cpu.dcache.writebacks::total            695593                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295624                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       295624                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3303164                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3303164                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18735                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18735                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3598788                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3598788                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3598788                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3598788                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413141                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       413141                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299628                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299628                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119644                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119644                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8393                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8393                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       712769                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       712769                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       832413                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       832413                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6403711500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6403711500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19964415469                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19964415469                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1698297000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1698297000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126773500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126773500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       273000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       273000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26368126969                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26368126969                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28066423969                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28066423969                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5935894500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5935894500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4789947462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4789947462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10725841962                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10725841962                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017290                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017290                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015660                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015660                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228429                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228429                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018035                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018035                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016567                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016567                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019107                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019107                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15421.265882                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15421.265882                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66558.035269                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66558.035269                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14191.383042                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14191.383042                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14993.908930                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14993.908930                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54600                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54600                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6386936500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6386936500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19975151483                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19975151483                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1701142500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1701142500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126808000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126808000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       298000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       298000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26362087983                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26362087983                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28063230483                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28063230483                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277199000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277199000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075698951                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075698951                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11352897951                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11352897951                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017210                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017210                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015648                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015648                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228392                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228392                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017904                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017904                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000015                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016517                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016517                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019058                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019058                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15459.459361                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15459.459361                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66666.504743                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66666.504743                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14218.368660                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14218.368660                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15108.781127                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15108.781127                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36985.458098                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36985.458098                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33713.109338                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33713.109338                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201651.161297                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201651.161297                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.137067                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.137067                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193359.300184                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193359.300184                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1889050                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.157898                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64290369                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1889562                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             34.023953                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       16212707500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.157898                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998355                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998355                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1886833                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.154154                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64237730                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1887345                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             34.036029                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       16318088500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.154154                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68161321                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68161321                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64290369                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64290369                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64290369                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64290369                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64290369                       # number of overall hits
-system.cpu.icache.overall_hits::total        64290369                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1981370                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1981370                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1981370                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1981370                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1981370                       # number of overall misses
-system.cpu.icache.overall_misses::total       1981370                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28130756994                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28130756994                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28130756994                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28130756994                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28130756994                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28130756994                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66271739                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66271739                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66271739                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66271739                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66271739                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66271739                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029898                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029898                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029898                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029898                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029898                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029898                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14197.629415                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14197.629415                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14197.629415                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14197.629415                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14197.629415                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14197.629415                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4834                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68104377                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68104377                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64237730                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64237730                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64237730                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64237730                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64237730                       # number of overall hits
+system.cpu.icache.overall_hits::total        64237730                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1979279                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1979279                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1979279                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1979279                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1979279                       # number of overall misses
+system.cpu.icache.overall_misses::total       1979279                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  28148050491                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  28148050491                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  28148050491                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  28148050491                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  28148050491                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  28148050491                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66217009                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66217009                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66217009                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66217009                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66217009                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66217009                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029891                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029891                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029891                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029891                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029891                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029891                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14221.365705                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14221.365705                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14221.365705                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14221.365705                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14221.365705                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14221.365705                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         4340                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               167                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               160                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    28.946108                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    27.125000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91786                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91786                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91786                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91786                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        91786                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        91786                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1889584                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1889584                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1889584                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1889584                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1889584                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1889584                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1886833                       # number of writebacks
+system.cpu.icache.writebacks::total           1886833                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91909                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        91909                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        91909                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91909                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        91909                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        91909                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887370                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1887370                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1887370                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1887370                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1887370                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1887370                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25162612496                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25162612496                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25162612496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25162612496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25162612496                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25162612496                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377653500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377653500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377653500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    377653500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028513                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028513                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028513                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028513                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028513                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028513                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13316.482621                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13316.482621                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13316.482621                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13316.482621                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13316.482621                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13316.482621                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125716.877497                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125716.877497                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125716.877497                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125716.877497                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25183213993                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  25183213993                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25183213993                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  25183213993                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25183213993                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  25183213993                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377667500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377667500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377667500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    377667500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028503                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028503                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028503                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13343.019118                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13343.019118                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13343.019118                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96843                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65028.531062                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5011588                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162159                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.905395                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96631                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65023.762629                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4997690                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           161869                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            30.874905                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49578.198261                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.786082                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     3.639229                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10379.582130                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5055.325361                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.756503                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000180                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000056                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.158380                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.077138                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992257                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2907                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6671                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55556                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996399                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         44337663                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        44337663                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        56125                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12636                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          68761                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       698262                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       698262                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           35                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           35                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       161870                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       161870                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1869604                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1869604                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       529846                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       529846                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        56125                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        12636                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1869604                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       691716                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2630081                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        56125                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        12636                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1869604                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       691716                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2630081                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           25                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total           32                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2716                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2716                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 49540.037548                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.058123                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     1.836532                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10328.574212                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5143.256214                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.755921                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000153                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000028                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157602                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.078480                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.992184                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65226                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2892                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6640                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55528                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995270                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         44234795                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        44234795                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54117                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11847                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          65964                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       695593                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       695593                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1846839                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1846839                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           33                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           33                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       161471                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       161471                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1867481                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1867481                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       527598                       # number of ReadSharedReq hits
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134857.843866                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 142562.500000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132379.302525                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130361.519254                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 130600.303222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 142562.500000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132379.302525                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130361.519254                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 130600.303222                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1444,8 +1457,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        89227                       # number of writebacks
-system.cpu.l2cache.writebacks::total            89227                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        88877                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88877                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
@@ -1456,29 +1469,29 @@ system.cpu.l2cache.demand_mshr_hits::total          138                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           26                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total          138                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           25                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total           32                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2716                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2716                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           21                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            8                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total           29                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2723                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2723                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135463                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       135463                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19906                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19906                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13291                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13291                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           25                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19906                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       148754                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168692                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           25                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19906                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       148754                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168692                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135531                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       135531                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19817                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19817                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13338                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13338                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           21                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            8                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        19817                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       148869                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168715                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           21                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            8                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19817                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       148869                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168715                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34133                       # number of ReadReq MSHR uncacheable
@@ -1487,148 +1500,149 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27585
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61718                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3235500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       858500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      4094000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    192221500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    192221500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       213500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       213500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16238965500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16238965500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2439385500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2439385500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1658508500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1658508500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3235500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       858500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2439385500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17897474000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20340953500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3235500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       858500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2439385500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17897474000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20340953500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340103000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5546780500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5886883500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4471146500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4471146500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340103000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10017927000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10358030000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000445                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000554                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000465                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987277                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987277                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455594                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455594                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010535                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010535                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024466                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024466                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000445                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000554                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010535                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.176965                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060271                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000445                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000554                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010535                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.176965                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060271                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker       129420                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122642.857143                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127937.500000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70773.748159                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70773.748159                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119877.497915                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119877.497915                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       129420                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       129420                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172468.974306                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162086.151894                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162086.151894                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113216.711052                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170622.458017                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167828.348294                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker      1060500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3771000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    192695000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    192695000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16252241500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16252241500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2425990000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2425990000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1667259500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1667259500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker      1060500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2425990000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17919501000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20349262000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker      1060500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2425990000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17919501000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20349262000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340117000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888077000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6228194000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756881000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756881000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340117000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644958000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10985075000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000439                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988026                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988026                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.456330                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.456330                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010500                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024652                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024652                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177637                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060442                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177637                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060442                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130034.482759                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70765.699596                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70765.699596                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119915.307199                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119915.307199                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122419.639703                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125000.712251                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125000.712251                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120370.936864                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120613.235338                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120370.936864                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120613.235338                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189150.856115                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182468.403012                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172444.480696                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172444.480696                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181301.870082                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177988.188211                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5492109                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2761974                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        46577                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          382                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          382                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5484076                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758688                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        47112                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          381                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          381                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         127618                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2560581                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         127589                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2556141                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       823684                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1992109                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2751                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2756                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297333                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297333                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1889584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       543472                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5634635                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2637259                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        32087                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       130191                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8434172                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    120978240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98677545                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        50572                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       224600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          219930957                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      194580                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5786927                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.021369                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.144611                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty       820637                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1846839                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       142823                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2757                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2763                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297002                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297002                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887370                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       541297                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        36194                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5627539                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2629603                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31270                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128179                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8416591                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    239034368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98344937                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        47420                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       216552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          337643277                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      197136                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3052848                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025905                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.158851                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5663267     97.86%     97.86% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             123660      2.14%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2973765     97.41%     97.41% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              79083      2.59%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5786927                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3520664000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       259127                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3052848                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5400072997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       264877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2838013223                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2834880345                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1307328687                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1303595064                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19448990                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19421986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74088903                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74092896                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1653,9 +1667,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
@@ -1678,207 +1692,209 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             43091000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                99500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                29000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                91000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               647500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6192000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              167000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            33054500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              126000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186319025                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           186395016                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36413                       # number of replacements
-system.iocache.tags.tagsinuse                1.005013                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256397447000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005013                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062813                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062813                       # Average percentage of cache occupancy
+system.iocache.tags.replacements                36409                       # number of replacements
+system.iocache.tags.tagsinuse                1.005392                       # Cycle average of tags in use
+system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         256608771000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.005392                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062837                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062837                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
-system.iocache.tags.data_accesses              328023                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          223                       # number of overall misses
-system.iocache.overall_misses::total              223                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28159877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28159877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4697532148                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4697532148                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28159877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28159877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28159877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28159877                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
+system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
+system.iocache.tags.data_accesses              328227                       # Number of data accesses
+system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
+system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
+system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
+system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          249                       # number of overall misses
+system.iocache.overall_misses::total              249                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     31311876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31311876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4715518140                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4715518140                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31311876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31311876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31311876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31311876                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126277.475336                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 126277.475336                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126277.475336                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126277.475336                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126277.475336                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.506024                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125750.506024                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130280.926647                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130280.926647                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125750.506024                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125750.506024                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125750.506024                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125750.506024                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           725                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   77                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.415584                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36190                       # number of writebacks
-system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17009877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17009877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2886332148                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2886332148                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17009877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17009877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17009877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17009877                       # number of overall MSHR miss cycles
+system.iocache.writebacks::writebacks           36160                       # number of writebacks
+system.iocache.writebacks::total                36160                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36195                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36195                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          249                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18861876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18861876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2905768140                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2905768140                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18861876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18861876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18861876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18861876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.999199                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76277.475336                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76277.475336                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.506024                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.506024                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.926647                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.926647                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.506024                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75750.506024                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.506024                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75750.506024                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               34133                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67584                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67565                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::Writeback            125417                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7628                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4571                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       125037                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7766                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4596                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4574                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133608                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133608                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33452                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4599                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133659                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133659                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33433                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36194                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455251                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562821                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108888                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108888                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 671709                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455099                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562669                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108826                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108826                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 671495                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16438044                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16601449                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18918569                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              487                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402837                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16416028                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16579433                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18894633                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              513                       # Total snoops (count)
+system.membus.snoop_fanout::samples            402650                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402837    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402650    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402837                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83606500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402650                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83677500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1745500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1748500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           875905157                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           874312374                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          988369672                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          988164899                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64470242                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64093300                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 1b6a9683d..787619867 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,166 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.627261                       # Number of seconds simulated
-sim_ticks                                2627260787000                       # Number of ticks simulated
-final_tick                               2627260787000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.837504                       # Number of seconds simulated
+sim_ticks                                2837504217500                       # Number of ticks simulated
+final_tick                               2837504217500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73269                       # Simulator instruction rate (inst/s)
-host_op_rate                                    88893                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1598642516                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 609448                       # Number of bytes of host memory used
-host_seconds                                  1643.43                       # Real time elapsed on the host
-sim_insts                                   120413300                       # Number of instructions simulated
-sim_ops                                     146090184                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  89459                       # Simulator instruction rate (inst/s)
+host_op_rate                                   108491                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2108642938                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 665360                       # Number of bytes of host memory used
+host_seconds                                  1345.65                       # Real time elapsed on the host
+sim_insts                                   120381204                       # Number of instructions simulated
+sim_ops                                     145991739                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         1536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1139008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1190376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8167488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         1792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1298560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1282472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8427712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           326368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           665684                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       594880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           172400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           575316                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       374464                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12087580                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1139008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       326368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1465376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8694784                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12134316                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1298560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       172400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1470960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8568768                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8712348                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           24                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             20044                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             19120                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       127617                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           14                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8586332                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           28                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22537                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20559                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       131683                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            6                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5167                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10422                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         9295                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2762                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9010                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         5851                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                191724                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          135856                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                192455                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          133887                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               140247                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           585                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              433534                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              453086                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      3108747                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           341                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            24                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              124224                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              253376                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       226426                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              365                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4600830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         433534                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         124224                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             557758                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3309448                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6670                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                 15                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3316134                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3309448                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          585                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          122                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             433534                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             459756                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      3108747                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          341                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             124224                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             253391                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       226426                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             365                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7916964                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        191724                       # Number of read requests accepted
-system.physmem.writeReqs                       140247                       # Number of write requests accepted
-system.physmem.readBursts                      191724                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     140247                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12260288                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10048                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8725248                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12087580                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8712348                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      157                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_writes::total               138278                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              457642                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              451972                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2970114                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               60758                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              202754                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       131969                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4276405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         457642                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          60758                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             518399                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3019826                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3026016                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3019826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             457642                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             458148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2970114                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          135                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              60758                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             202768                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       131969                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             338                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7302420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        192456                       # Number of read requests accepted
+system.physmem.writeReqs                       138278                       # Number of write requests accepted
+system.physmem.readBursts                      192456                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     138278                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12307136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9984                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8599232                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12134380                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8586332                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      156                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          50731                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11367                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11306                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12534                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11925                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14392                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11995                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12528                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12413                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12465                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12343                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12048                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11291                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11598                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11714                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10851                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10797                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8020                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8176                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9316                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8567                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8317                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8617                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9080                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8981                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                9059                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8883                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8732                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8494                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8573                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8275                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7766                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7476                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          65662                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11960                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11050                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12052                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12058                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14137                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12072                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12490                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12293                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12129                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11971                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11835                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10924                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11792                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12532                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11740                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11264                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8435                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7998                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8830                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8684                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8112                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8575                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8926                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8709                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8491                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8366                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8474                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8070                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8488                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8576                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8125                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7504                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2627260507500                       # Total gap between requests
+system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2837503950500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
-system.physmem.readPktSize::4                    3086                       # Read request sizes (log2)
+system.physmem.readPktSize::4                    3087                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  188059                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  188790                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 135856                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     61031                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     73227                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12933                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     10004                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      8250                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7158                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      6223                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      5068                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      4443                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1296                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      829                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      578                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      273                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      238                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 133887                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     61458                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     73949                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     12857                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9980                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8183                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7124                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      6164                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      5080                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4433                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1271                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      792                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      552                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      233                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      214                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -188,160 +188,159 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9358                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10651                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     8113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      660                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2740                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5397                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8785                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10865                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9207                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10503                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8864                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7439                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      624                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      214                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      219                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::40                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      104                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::49                      117                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::54                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        86649                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      242.189431                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     136.582911                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     303.571271                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46399     53.55%     53.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16583     19.14%     72.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5986      6.91%     79.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3348      3.86%     83.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2763      3.19%     86.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1550      1.79%     88.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1005      1.16%     89.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          914      1.05%     90.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8101      9.35%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          86649                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6686                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.651211                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      549.102387                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6684     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6686                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6686                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.390667                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.828394                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.276627                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5432     81.24%     81.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             492      7.36%     88.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              97      1.45%     90.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             153      2.29%     92.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              34      0.51%     92.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             125      1.87%     94.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              42      0.63%     95.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              20      0.30%     95.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              24      0.36%     96.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              25      0.37%     96.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.09%     96.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.09%     96.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             159      2.38%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.09%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               6      0.09%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              24      0.36%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               8      0.12%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.04%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.03%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.12%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.01%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6686                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6416960776                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10008842026                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    957835000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       33497.21                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  52247.21                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.67                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.32                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.60                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.32                       # Average system write bandwidth in MiByte/s
+system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       11                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        86935                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      240.482751                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     135.610645                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     303.163398                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          46710     53.73%     53.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        16982     19.53%     73.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5795      6.67%     79.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3191      3.67%     83.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2666      3.07%     86.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1598      1.84%     88.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          941      1.08%     89.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          911      1.05%     90.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8141      9.36%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          86935                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6558                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.322812                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      574.114177                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6556     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6558                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6558                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.488411                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.922621                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.969935                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5288     80.63%     80.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             495      7.55%     88.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             103      1.57%     89.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             154      2.35%     92.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              30      0.46%     92.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             130      1.98%     94.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              43      0.66%     95.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              19      0.29%     95.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              29      0.44%     95.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              20      0.30%     96.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              10      0.15%     96.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              12      0.18%     96.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             145      2.21%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               7      0.11%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               5      0.08%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              33      0.50%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              10      0.15%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.15%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6558                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6213827144                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9819433394                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    961495000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       32313.19                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      4999.97                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  51063.10                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.03                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.28                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.03                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.07                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     159898                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81351                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.47                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.66                       # Row buffer hit rate for writes
-system.physmem.avgGap                      7914126.56                       # Average gap between requests
-system.physmem.pageHitRate                      73.57                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  337168440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  183970875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 767988000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                447599520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           171599840880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            75926466675                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1509753884250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1759016918640                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.525234                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2511501025755                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     87729980000                       # Time in different power states
+system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.17                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     160530                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     79197                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.93                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8579414.12                       # Average gap between requests
+system.physmem.pageHitRate                      73.38                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  333396000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  181912500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 765273600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                442383120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185331978000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80482301685                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1631904131250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1899441376155                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.405614                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2714718220190                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94750240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     28029087995                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     28035696060                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  317898000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  173456250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 726226800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                435831840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           171599840880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            75533290650                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1510098775500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1758885319920                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.475144                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2512077352355                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     87729980000                       # Time in different power states
+system.physmem_1.actEnergy                  323832600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  176694375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 734658600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                428289120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185331978000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80147926575                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1632197442750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1899340822020                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.370176                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2715209176165                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94750240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27453418145                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     27544740085                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
@@ -352,30 +351,30 @@ system.realview.nvmem.bytes_inst_read::total          320
 system.realview.nvmem.num_reads::cpu0.inst            8                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             20                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           49                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           73                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              122                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           49                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           73                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          122                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           49                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           73                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             122                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu0.inst           45                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           68                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              113                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           45                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           68                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          113                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           45                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           68                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             113                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               22632354                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         14659623                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           908184                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            13749139                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               10145845                       # Number of BTB hits
+system.cpu0.branchPred.lookups               53984881                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         25029279                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1031275                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            32703051                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               24288553                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            73.792584                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                3729563                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             29268                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            74.269991                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15579180                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             33867                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -406,78 +405,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    62082                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               62082                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        23874                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        18654                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        19554                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        42528                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   489.830229                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  2960.338749                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        41379     97.30%     97.30% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          822      1.93%     99.23% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          148      0.35%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767          139      0.33%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                    71885                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               71885                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26706                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        21113                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        24066                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        47819                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   500.773751                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3132.734175                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        46517     97.28%     97.28% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          936      1.96%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          174      0.36%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767          150      0.31%     99.91% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::32768-40959           13      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           21      0.05%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-57343            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535            3      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-73727            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        42528                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        15147                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean  9846.471248                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  8208.075631                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  8231.250252                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767        15054     99.39%     99.39% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535           70      0.46%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839           21      0.14%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        15147                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  97524095656                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.460762                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.504971                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  97474132156     99.95%     99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     37222000      0.04%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5      6333500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      3452500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      1280500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11       673000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       722500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15       263000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17        16500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  97524095656                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5018     79.05%     79.05% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1330     20.95%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         6348                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        62082                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           21      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::106496-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::114688-122879            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        47819                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        18759                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 11059.171598                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9588.566879                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  7711.880133                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        18631     99.32%     99.32% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535          106      0.57%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071           16      0.09%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        18759                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  84429292764                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.657402                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.487897                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0    29095217424     34.46%     34.46% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    55270258340     65.46%     99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2       29607500      0.04%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::3       15656000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4        4826500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::5        2762000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6        4173000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::7        1494500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8        1031000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::9         697500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10        703000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::11        393500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12       1099500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::13        296000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14        143000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::15        934000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  84429292764                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5818     79.12%     79.12% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1535     20.88%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7353                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        71885                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        62082                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6348                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        71885                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7353                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6348                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        68430                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7353                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        79238                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    16776749                       # DTB read hits
-system.cpu0.dtb.read_misses                     53234                       # DTB read misses
-system.cpu0.dtb.write_hits                   13912942                       # DTB write hits
-system.cpu0.dtb.write_misses                     8848                       # DTB write misses
+system.cpu0.dtb.read_hits                    24461690                       # DTB read hits
+system.cpu0.dtb.read_misses                     61076                       # DTB read misses
+system.cpu0.dtb.write_hits                   18142518                       # DTB write hits
+system.cpu0.dtb.write_misses                    10809                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3447                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                       80                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2058                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3811                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      171                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2460                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      829                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                16829983                       # DTB read accesses
-system.cpu0.dtb.write_accesses               13921790                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     1016                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24522766                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18153327                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         30689691                       # DTB hits
-system.cpu0.dtb.misses                          62082                       # DTB misses
-system.cpu0.dtb.accesses                     30751773                       # DTB accesses
+system.cpu0.dtb.hits                         42604208                       # DTB hits
+system.cpu0.dtb.misses                          71885                       # DTB misses
+system.cpu0.dtb.accesses                     42676093                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -507,53 +518,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    10470                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort               10470                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4275                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6082                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          113                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        10357                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean   430.336970                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  2100.288015                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095         9961     96.18%     96.18% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191          126      1.22%     97.39% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287          203      1.96%     99.35% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383           38      0.37%     99.72% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479           13      0.13%     99.85% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575           10      0.10%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671            3      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959            2      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        10357                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2692                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 11506.129272                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 10069.776184                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6522.127356                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2498     92.79%     92.79% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          161      5.98%     98.77% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           32      1.19%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2692                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  20202424328                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.966577                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.179934                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      675884500      3.35%      3.35% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    19525926328     96.65%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2         564000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3          49500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  20202424328                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2260     87.63%     87.63% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          319     12.37%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2579                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    10900                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               10900                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4234                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6533                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          133                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        10767                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   543.187517                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  2520.119999                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095        10263     95.32%     95.32% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191          147      1.37%     96.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287          248      2.30%     98.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383           60      0.56%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479           13      0.12%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575           18      0.17%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671           11      0.10%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-32767            3      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        10767                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         3015                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 13136.152570                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 12059.608238                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  6103.776811                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         2740     90.88%     90.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          236      7.83%     98.71% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           36      1.19%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535            2      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         3015                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  20004739824                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.958205                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.200359                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      836985000      4.18%      4.18% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    19166939824     95.81%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2         745000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3          70000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  20004739824                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2539     88.10%     88.10% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          343     11.90%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2882                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10470                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10470                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10900                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10900                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2579                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2579                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        13049                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    35710587                       # ITB inst hits
-system.cpu0.itb.inst_misses                     10470                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2882                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2882                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        13782                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    74221386                       # ITB inst hits
+system.cpu0.itb.inst_misses                     10900                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -562,1046 +576,1042 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2356                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2623                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1940                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     2177                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                35721057                       # ITB inst accesses
-system.cpu0.itb.hits                         35710587                       # DTB hits
-system.cpu0.itb.misses                          10470                       # DTB misses
-system.cpu0.itb.accesses                     35721057                       # DTB accesses
-system.cpu0.numCycles                       126659372                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                74232286                       # ITB inst accesses
+system.cpu0.itb.hits                         74221386                       # DTB hits
+system.cpu0.itb.misses                          10900                       # DTB misses
+system.cpu0.itb.accesses                     74232286                       # DTB accesses
+system.cpu0.numCycles                       211089412                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          17871987                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     106431260                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   22632354                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          13875408                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    101673133                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                2651880                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    146874                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               68068                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       354842                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       428688                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles        93530                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 35711195                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               256145                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   4738                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         121963062                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.052824                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.258485                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          21154368                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     200477778                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   53984881                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          39867733                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    180634648                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                5887980                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    163875                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               73228                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       386540                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       467083                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       106682                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 74221667                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               284223                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   5134                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         205930414                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.189818                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.306225                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                62962688     51.62%     51.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                20162814     16.53%     68.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 8269817      6.78%     74.94% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                30567743     25.06%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                98513446     47.84%     47.84% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                31147875     15.13%     62.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                14935472      7.25%     70.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                61333621     29.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           121963062                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.178687                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.840295                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                18684987                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             58693341                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 38833256                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              4747637                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1003841                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             2912386                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               326313                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             104496141                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              3704345                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1003841                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                24126481                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12572099                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      34554184                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 38013567                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             11692890                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              99684423                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts               977099                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1404281                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                150386                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 54053                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               7679999                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          103244507                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            455598825                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       114217475                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             9462                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             92488092                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                10756412                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1189033                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1051673                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 11830745                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            17693579                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           15395073                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1633265                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2155883                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  96874005                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1635627                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 95096979                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           454397                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        8909178                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     20852751                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        116081                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    121963062                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.779720                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.027198                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           205930414                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.255744                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.949729                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26441792                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            111116512                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 60639193                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              5147176                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               2585741                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3185045                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               362773                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             158832709                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4189276                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               2585741                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                35360438                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               13326930                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      85149071                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 56726750                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             12781484                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             141877128                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1133387                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1508513                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                170712                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 63171                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               8443572                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          146064106                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            654194105                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       157626069                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            10971                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            133804111                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                12259992                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           2731692                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       2584898                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 22953113                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            25474104                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           19753680                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1758400                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2611655                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 138738893                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1764680                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                136614694                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           514032                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       11572613                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     23827744                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        127449                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    205930414                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.663402                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       0.962674                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           68765776     56.38%     56.38% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           22213388     18.21%     74.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           21122370     17.32%     91.91% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            8807290      7.22%     99.14% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1054209      0.86%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 29      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          127115623     61.73%     61.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           34474239     16.74%     78.47% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           32051807     15.56%     94.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           11118185      5.40%     99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1170514      0.57%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 46      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      121963062                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      205930414                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                8813581     40.35%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   132      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     40.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5351630     24.50%     64.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              7678552     35.15%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               11113465     43.69%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                    76      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5930869     23.32%     67.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8390890     32.99%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             2272      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             62602265     65.83%     65.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               87841      0.09%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     65.92% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          7143      0.01%     65.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     65.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     65.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            17444547     18.34%     84.28% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           14952910     15.72%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             2315      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             92049537     67.38%     67.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult              112728      0.08%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.46% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          8149      0.01%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            25196866     18.44%     85.91% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           19245098     14.09%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              95096979                       # Type of FU issued
-system.cpu0.iq.rate                          0.750809                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   21843895                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.229701                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         334422549                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        107425966                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     93117016                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              32763                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             11378                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         9790                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             116917216                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  21386                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          346137                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             136614694                       # Type of FU issued
+system.cpu0.iq.rate                          0.647189                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   25435300                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.186183                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         505071342                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        152083684                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    132900099                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              37792                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             13226                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses        11443                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             162023237                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  24442                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          380983                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1858057                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2517                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        18608                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       952368                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2125903                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2726                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        20804                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1085884                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       100941                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       343903                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       121982                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       393712                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1003841                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1765434                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               210085                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           98680740                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               2585741                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1952892                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               228879                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          140712950                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             17693579                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            15395073                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            848677                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 24988                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               163669                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         18608                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        265563                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       373947                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              639510                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             94079743                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             17020662                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           955277                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             25474104                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            19753680                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            902814                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 28763                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               175994                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         20804                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        314280                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       420638                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              734918                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            135458636                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             24717807                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1084310                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       171108                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    31795600                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                15818182                       # Number of branches executed
-system.cpu0.iew.exec_stores                  14774938                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.742778                       # Inst execution rate
-system.cpu0.iew.wb_sent                      93557624                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     93126806                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 48392376                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 80015738                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       209377                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    43763584                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                26159060                       # Number of branches executed
+system.cpu0.iew.exec_stores                  19045777                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.641712                       # Inst execution rate
+system.cpu0.iew.wb_sent                     134853240                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    132911542                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 67798610                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                109653581                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.735254                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.604786                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.629646                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.618298                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        7942186                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1519546                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           586085                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    120319586                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.745699                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.465434                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       10465758                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1637231                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           673026                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    202620964                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.637065                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.337510                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     78400270     65.16%     65.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     23370127     19.42%     84.58% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      7855137      6.53%     91.11% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3041175      2.53%     93.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      3186617      2.65%     96.29% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      1413825      1.18%     97.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1097896      0.91%     98.38% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       521063      0.43%     98.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1433476      1.19%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    140811364     69.49%     69.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     34122035     16.84%     86.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     12973971      6.40%     92.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3422170      1.69%     94.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      4965504      2.45%     96.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      2761485      1.36%     98.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1431161      0.71%     98.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       576287      0.28%     99.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1556987      0.77%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    120319586                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            74552173                       # Number of instructions committed
-system.cpu0.commit.committedOps              89722144                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    202620964                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           106609467                       # Number of instructions committed
+system.cpu0.commit.committedOps             129082799                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      30278227                       # Number of memory references committed
-system.cpu0.commit.loads                     15835522                       # Number of loads committed
-system.cpu0.commit.membars                     627502                       # Number of memory barriers committed
-system.cpu0.commit.branches                  15222627                       # Number of branches committed
-system.cpu0.commit.fp_insts                      9772                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 77510355                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             1849810                       # Number of function calls committed.
+system.cpu0.commit.refs                      42015997                       # Number of memory references committed
+system.cpu0.commit.loads                     23348201                       # Number of loads committed
+system.cpu0.commit.membars                     664671                       # Number of memory barriers committed
+system.cpu0.commit.branches                  25482813                       # Number of branches committed
+system.cpu0.commit.fp_insts                     11428                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                112616062                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             4882659                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        59351234     66.15%     66.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          85540      0.10%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         7143      0.01%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       15835522     17.65%     83.90% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      14442705     16.10%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        86948458     67.36%     67.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult         110195      0.09%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         8149      0.01%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       23348201     18.09%     85.54% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      18667796     14.46%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         89722144                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1433476                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   212523033                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  196970686                       # The number of ROB writes
-system.cpu0.timesIdled                         126988                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        4696310                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5127862528                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   74430479                       # Number of Instructions Simulated
-system.cpu0.committedOps                     89600450                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.701714                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.701714                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.587643                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.587643                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               104622739                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               56501496                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     8247                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                    2269                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                331476991                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                38443016                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              169856708                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1190913                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           672498                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          485.161129                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           27296512                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           673010                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            40.558851                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        129082799                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1556987                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   317266716                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  282405799                       # The number of ROB writes
+system.cpu0.timesIdled                         139400                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        5158998                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5463919353                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  106457624                       # Number of Instructions Simulated
+system.cpu0.committedOps                    128930956                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.982849                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.982849                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.504325                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.504325                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               146869793                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               83863812                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     9544                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                    2721                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                478325864                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                51342401                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              283146795                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1260752                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           750420                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          496.151485                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           38802198                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           750932                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            51.672053                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        426635500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.161129                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947580                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.947580                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.151485                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969046                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.969046                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          186                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         60152551                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        60152551                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     14711290                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       14711290                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     11396766                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      11396766                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       295733                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       295733                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       354236                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       354236                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       350938                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       350938                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     26108056                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        26108056                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     26403789                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       26403789                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       611234                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       611234                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1805910                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1805910                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141308                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       141308                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        24174                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        24174                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21176                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        21176                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2417144                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2417144                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2558452                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2558452                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9073163500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   9073163500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  32396978375                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  32396978375                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    391326000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    391326000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    534289500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    534289500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       728500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       728500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  41470141875                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  41470141875                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  41470141875                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  41470141875                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     15322524                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     15322524                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     13202676                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     13202676                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       437041                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       437041                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       378410                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       378410                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       372114                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       372114                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     28525200                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     28525200                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     28962241                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     28962241                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.039891                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.039891                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.136784                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.136784                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.323329                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.323329                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.063883                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.063883                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056907                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056907                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084737                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.084737                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088338                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.088338                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14844.009823                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14844.009823                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17939.420223                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17939.420223                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16187.887813                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16187.887813                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25230.898187                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25230.898187                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         83743288                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        83743288                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     22166108                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       22166108                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15386838                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15386838                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       316240                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       316240                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       371193                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       371193                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       369806                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       369806                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     37552946                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        37552946                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     37869186                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       37869186                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       688329                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       688329                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1970797                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1970797                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       153398                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       153398                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        26102                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        26102                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20247                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20247                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2659126                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2659126                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2812524                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2812524                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9979901000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   9979901000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36499508368                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  36499508368                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    419269000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    419269000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    539016500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    539016500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       316500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       316500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  46479409368                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  46479409368                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  46479409368                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  46479409368                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     22854437                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     22854437                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17357635                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17357635                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       469638                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       469638                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       397295                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       397295                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       390053                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       390053                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     40212072                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     40212072                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     40681710                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     40681710                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030118                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.030118                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.113541                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.113541                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.326630                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.326630                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065699                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065699                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051908                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051908                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.066128                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.066128                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069135                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.069135                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14498.736796                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14498.736796                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18520.176542                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18520.176542                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16062.715501                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16062.715501                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26622.042772                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26622.042772                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17156.669969                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 17156.669969                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16209.075595                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16209.075595                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         1312                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      5225040                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               49                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         192315                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    26.775510                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    27.169176                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17479.205336                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 17479.205336                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16525.871199                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16525.871199                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         1220                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      5610117                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               53                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         211671                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.018868                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    26.503947                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       490431                       # number of writebacks
-system.cpu0.dcache.writebacks::total           490431                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       244715                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       244715                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1493725                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1493725                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        18048                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18048                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1738440                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1738440                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1738440                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1738440                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       366519                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       366519                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       312185                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       312185                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        97992                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        97992                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6126                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6126                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21176                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        21176                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       678704                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       678704                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       776696                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       776696                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17958                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17958                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16709                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16709                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34667                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34667                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4650113000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4650113000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6789940400                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6789940400                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1696741500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1696741500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97425500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97425500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    513125500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    513125500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       716500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       716500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11440053400                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11440053400                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13136794900                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13136794900                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3760775500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3760775500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2938081500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2938081500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6698857000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6698857000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.023920                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.023920                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.023646                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.023646                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224217                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224217                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016189                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016189                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056907                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056907                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023793                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023793                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026818                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026818                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12687.235860                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12687.235860                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21749.733011                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21749.733011                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17315.102253                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17315.102253                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15903.607574                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15903.607574                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24231.464866                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24231.464866                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       750420                       # number of writebacks
+system.cpu0.dcache.writebacks::total           750420                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       277928                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       277928                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1634691                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1634691                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        19352                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        19352                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1912619                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1912619                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1912619                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1912619                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       410401                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       410401                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       336106                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       336106                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107319                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       107319                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6750                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6750                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20247                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20247                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       746507                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       746507                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       853826                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       853826                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31838                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31838                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28498                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28498                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60336                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60336                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5125711500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5125711500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7684887402                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7684887402                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1795459000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1795459000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    109420000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    109420000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    518776500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    518776500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       309500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       309500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12810598902                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12810598902                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14606057902                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  14606057902                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6629004500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6629004500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5396257500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5396257500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12025262000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12025262000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017957                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017957                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019364                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019364                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228514                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228514                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016990                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016990                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051908                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051908                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018564                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018564                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020988                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.020988                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.520006                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.520006                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22864.475499                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22864.475499                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16730.113028                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16730.113028                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16210.370370                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16210.370370                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25622.388502                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25622.388502                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16855.732985                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16855.732985                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16913.689397                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16913.689397                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209420.620336                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209420.620336                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175838.260818                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175838.260818                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 193234.401592                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193234.401592                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17160.721737                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17160.721737                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17106.597717                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17106.597717                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208210.456059                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208210.456059                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189355.656537                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189355.656537                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199304.925749                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199304.925749                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1200820                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.709969                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           34456109                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1201332                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            28.681588                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       8093069500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.709969                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999434                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999434                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1310169                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.377289                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           72850689                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1310681                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            55.582319                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       8207375500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.377289                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998784                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998784                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          138                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         72616555                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        72616555                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     34456109                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       34456109                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     34456109                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        34456109                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     34456109                       # number of overall hits
-system.cpu0.icache.overall_hits::total       34456109                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1251492                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1251492                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1251492                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1251492                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1251492                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1251492                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13477536890                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13477536890                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13477536890                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13477536890                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13477536890                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13477536890                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     35707601                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     35707601                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     35707601                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     35707601                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     35707601                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     35707601                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.035048                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.035048                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.035048                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.035048                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.035048                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.035048                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10769.175424                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10769.175424                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10769.175424                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10769.175424                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10769.175424                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10769.175424                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1798735                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        149746644                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       149746644                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     72850689                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       72850689                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     72850689                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        72850689                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     72850689                       # number of overall hits
+system.cpu0.icache.overall_hits::total       72850689                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1367277                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1367277                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1367277                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1367277                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1367277                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1367277                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14942894261                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14942894261                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14942894261                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14942894261                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14942894261                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14942894261                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     74217966                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     74217966                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     74217966                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     74217966                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     74217966                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     74217966                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.018422                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.018422                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.018422                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.018422                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.018422                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.018422                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10928.944362                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10928.944362                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10928.944362                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10928.944362                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10928.944362                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10928.944362                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      2021185                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets         1804                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           112593                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           126207                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets             15                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.975549                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.014841                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets   120.266667                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        50137                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        50137                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        50137                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        50137                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        50137                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        50137                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1201355                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1201355                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1201355                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1201355                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1201355                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1201355                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1310169                       # number of writebacks
+system.cpu0.icache.writebacks::total          1310169                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        56563                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        56563                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        56563                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        56563                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        56563                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        56563                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1310714                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1310714                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1310714                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1310714                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1310714                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1310714                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12113813705                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  12113813705                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12113813705                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  12113813705                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12113813705                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  12113813705                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    420637998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    420637998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    420637998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    420637998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.033644                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.033644                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.033644                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.033644                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.033644                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.033644                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10083.458849                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10083.458849                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10083.458849                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10083.458849                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10083.458849                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10083.458849                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140025.964714                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140025.964714                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13414113616                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  13414113616                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13414113616                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  13414113616                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13414113616                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  13414113616                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    420651998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    420651998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    420651998                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    420651998                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017660                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017660                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017660                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10234.203355                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10234.203355                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10234.203355                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10234.203355                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10234.203355                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10234.203355                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1767941                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1770755                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         2568                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1920430                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1923198                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         2526                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       220461                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          267926                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16038.044511                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3405557                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          284162                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           11.984562                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       245058                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          284507                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16100.171768                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3421600                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          300660                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           11.380297                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  9237.046322                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    12.824240                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.088026                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  3962.897629                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1653.213235                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1171.975059                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.563785                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000783                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000005                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.241876                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.100904                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.071532                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.978885                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1081                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15141                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           42                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          304                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          429                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          306                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14677.549696                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    12.049066                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     1.660096                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1408.912909                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.895847                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000735                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000101                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.085993                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.982676                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1016                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15129                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           23                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          340                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          424                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          229                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          418                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4597                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7301                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2771                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.065979                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.924133                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        63212919                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       63212919                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        49275                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker        12221                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         61496                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks       490428                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total       490428                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28559                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        28559                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1634                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total         1634                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       183915                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       183915                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1150269                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1150269                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       371621                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       371621                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        49275                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker        12221                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1150269                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       555536                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1767301                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        49275                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker        12221                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1150269                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       555536                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1767301                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          406                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          160                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          566                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        27413                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        27413                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19541                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        19541                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          499                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4650                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7772                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2079                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062012                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.923401                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        69513277                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       69513277                       # Number of data accesses
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total    607087500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    414982000                       # number of SCUpgradeReq miss cycles
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-system.cpu0.l2cache.Writeback_accesses::writebacks       490428                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total       490428                       # number of Writeback accesses(hits+misses)
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-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008172                       # miss rate for ReadReq accesses
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-system.cpu0.l2cache.ReadReq_miss_rate::total     0.009120                       # miss rate for ReadReq accesses
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-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.489763                       # miss rate for UpgradeReq accesses
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+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999982                       # miss rate for UpgradeReq accesses
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 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
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-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.210238                       # miss rate for ReadSharedReq accesses
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-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.012923                       # miss rate for demand accesses
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-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.012923                       # miss rate for overall accesses
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-system.cpu0.l2cache.overall_miss_rate::total     0.112094                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30360.837438                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26218.750000                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29189.929329                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22145.970890                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22145.970890                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21236.477151                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21236.477151                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       697999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       697999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53206.455201                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53206.455201                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 66558.786079                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 66558.786079                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33165.753515                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33165.753515                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30360.837438                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26218.750000                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 66558.786079                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41644.480455                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 47316.239662                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30360.837438                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26218.750000                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 66558.786079                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41644.480455                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 47316.239662                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          136                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.268953                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.268953                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042174                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042174                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.186382                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.186382                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.006601                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.010612                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042174                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.215181                       # miss rate for demand accesses
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3346.001405                       # average UpgradeReq miss latency
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+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2267.114492                       # average SCUpgradeReq miss latency
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+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68604.672793                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34868.093044                       # average ReadSharedReq miss latency
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+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32802.469136                       # average overall miss latency
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+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68604.672793                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42924.432603                       # average overall miss latency
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+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25630.573248                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68604.672793                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42924.432603                       # average overall miss latency
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+system.cpu0.l2cache.blocked_cycles::no_mshrs          171                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    28.500000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       193883                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          193883                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.writebacks::writebacks       233188                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          233188                       # number of writebacks
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 system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        31886                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        31886                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           21                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           21                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          720                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          720                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           21                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        32606                       # number of demand (read+write) MSHR hits
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-system.cpu0.l2cache.ReadReq_mshr_misses::total          565                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         8411                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total         8411                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       234452                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       234452                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        27413                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        27413                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19541                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19541                       # number of SCUpgradeReq MSHR misses
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-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        51054                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        51054                       # number of ReadCleanReq MSHR misses
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        17958                       # number of ReadReq MSHR uncacheable
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-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4015125500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2810012462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2810012462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    398106500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6427031462                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   6825137962                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008172                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.012842                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.009104                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60336                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63340                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10845500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3082000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     13927500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21538120931                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21538120931                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1460130500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1460130500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    365635499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    365635499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       254999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       254999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2446283000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2446283000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3458747998                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3458747998                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2770762497                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2770762497                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     10845500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3082000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3458747998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5217045497                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   8689720995                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     10845500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3082000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3458747998                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5217045497                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21538120931                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  30227841926                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    398120500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6373987500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6772108000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5179265462                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5179265462                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    398120500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11553252962                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11951373462                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.006585                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.010612                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.007367                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.489763                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.489763                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.922834                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.922834                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999982                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.158543                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.158543                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042497                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042497                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.208708                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.208708                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008172                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.012842                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042497                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.191011                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.095702                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008172                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.012842                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042497                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.191011                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.152150                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.152150                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042140                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042140                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184874                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.184874                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.006585                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.010612                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042140                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.173460                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.089168                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.006585                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.010612                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042140                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.173460                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.213492                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23219.469027                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 89557.677124                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32682.978879                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32682.978879                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18064.019037                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18064.019037                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       625999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       625999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57218.002951                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57218.002951                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 60574.842304                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60574.842304                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26869.500117                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26869.500117                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 60574.842304                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35755.485450                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 42370.378910                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 60574.842304                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35755.485450                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 68405.133252                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201415.469429                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191543.054098                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168173.586810                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168173.586810                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185393.355699                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 181177.509543                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.207675                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24826.203209                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82913.548852                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26305.339867                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26305.339867                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18059.641361                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18059.641361                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       254999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       254999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57253.797365                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57253.797365                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62622.175514                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62622.175514                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28583.126123                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28583.126123                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62622.175514                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37354.260919                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44458.479333                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62622.175514                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37354.260919                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66402.273009                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.625039                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194366.224671                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181741.366482                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181741.366482                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191481.917296                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188686.035081                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      3900428                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1972103                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        30395                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       166078                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       165928                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          150                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq         98608                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1819240                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        16709                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        16709                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback       685334                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      1450937                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       287419                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        90627                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43495                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       114961                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           22                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           33                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       273601                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       270191                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1201355                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       557036                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3216                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3585963                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2443651                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        28820                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       110863                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6169297                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     76933952                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     82016191                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        49524                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       198724                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         159198391                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     860528                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      4738789                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.052471                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.223116                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests      4274202                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2158357                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        33137                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       328935                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       324390                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4545                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        121088                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2005227                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28498                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28498                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       739211                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1521984                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       210746                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       317495                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        85916                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42642                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       113550                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            9                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           15                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       299038                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       295760                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1310714                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       595848                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3361                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3912120                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2727113                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        32094                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       130288                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6801615                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    166153536                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    103357964                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        59176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       245424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         269816100                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1019832                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      3249125                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.119614                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.328792                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           4490292     94.76%     94.76% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            248347      5.24%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               150      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2865028     88.18%     88.18% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            379552     11.68%     99.86% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              4545      0.14%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       4738789                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    2495889948                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    112738429                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3249125                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    4275785445                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    115025120                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1805438687                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1969663813                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1156413493                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1293120190                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     16448481                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     17309980                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     61214934                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     68982399                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups               35362528                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         12650645                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           376011                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            19640345                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               15643376                       # Number of BTB hits
+system.cpu1.branchPred.lookups                4001540                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2313487                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           245860                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2018567                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1484210                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            79.649191                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               12652559                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             10779                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            73.527904                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 788035                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              5731                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1631,90 +1641,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    24283                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               24283                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        11247                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5966                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore         7070                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        17213                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   473.798873                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  2831.806000                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        16574     96.29%     96.29% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191          219      1.27%     97.56% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287          229      1.33%     98.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383           75      0.44%     99.33% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479           20      0.12%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575           24      0.14%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671            7      0.04%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767           43      0.25%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863           17      0.10%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959            3      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::40960-45055            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    15963                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               15963                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8440                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3082                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         4441                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        11522                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   609.182434                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3297.605064                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        10996     95.43%     95.43% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          174      1.51%     96.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287          184      1.60%     98.54% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383           58      0.50%     99.05% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           13      0.11%     99.16% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           21      0.18%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671            5      0.04%     99.38% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           47      0.41%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863           21      0.18%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959            2      0.02%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::53248-57343            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        17213                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         5394                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 10976.177234                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  9365.976538                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  8403.035892                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         4813     89.23%     89.23% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          520      9.64%     98.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151           49      0.91%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535            4      0.07%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-147455            3      0.06%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839            4      0.07%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::212992-229375            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         5394                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  75766592176                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.320474                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.469554                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    51526613188     68.01%     68.01% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    24219637488     31.97%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2       12480500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3        3766000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4        1197500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5         815500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6         985500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7         293500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8         146000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9         224500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10         83500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11         76500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12        137000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13         18000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14         22000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15         95500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  75766592176                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1932     75.85%     75.85% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          615     24.15%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         2547                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        24283                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total        11522                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         3235                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11713.446677                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10455.998129                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6677.373091                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         2744     84.82%     84.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          453     14.00%     98.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151           32      0.99%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            5      0.15%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         3235                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  75555560672                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.169680                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.377976                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    62765308336     83.07%     83.07% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    12774698836     16.91%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2       10450000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3        2017500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4        1080000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5         463500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6         984500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7         133500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8          33500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9          93000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10         18000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11         18000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12         88500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13         11000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14         24500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15        138000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  75555560672                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1230     72.78%     72.78% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          460     27.22%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1690                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        15963                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        24283                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2547                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        15963                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1690                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2547                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        26830                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1690                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        17653                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    11209013                       # DTB read hits
-system.cpu1.dtb.read_misses                     21079                       # DTB read misses
-system.cpu1.dtb.write_hits                    7325054                       # DTB write hits
-system.cpu1.dtb.write_misses                     3204                       # DTB write misses
+system.cpu1.dtb.read_hits                     3544820                       # DTB read hits
+system.cpu1.dtb.read_misses                     14056                       # DTB read misses
+system.cpu1.dtb.write_hits                    3033862                       # DTB write hits
+system.cpu1.dtb.write_misses                     1907                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2001                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       73                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   612                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1651                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       51                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   364                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      367                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                11230092                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7328258                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      252                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 3558876                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3035769                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         18534067                       # DTB hits
-system.cpu1.dtb.misses                          24283                       # DTB misses
-system.cpu1.dtb.accesses                     18558350                       # DTB accesses
+system.cpu1.dtb.hits                          6578682                       # DTB hits
+system.cpu1.dtb.misses                          15963                       # DTB misses
+system.cpu1.dtb.accesses                      6594645                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1744,57 +1751,60 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     6861                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                6861                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4105                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2676                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore           80                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         6781                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   216.855921                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  1684.274104                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-4095         6669     98.35%     98.35% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-8191           39      0.58%     98.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-12287           44      0.65%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-16383           12      0.18%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-20479            5      0.07%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-24575            5      0.07%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-28671            2      0.03%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::28672-32767            2      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-36863            3      0.04%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         6781                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         1249                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11729.383507                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10507.790303                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  6381.189280                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          353     28.26%     28.26% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383          814     65.17%     93.43% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575           24      1.92%     95.36% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           32      2.56%     97.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959           17      1.36%     99.28% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151            7      0.56%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535            1      0.08%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::73728-81919            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         1249                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  15604919032                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.958751                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.198933                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0      643875264      4.13%      4.13% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    14960875268     95.87%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2         148500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3          20000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  15604919032                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          997     85.29%     85.29% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          172     14.71%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         1169                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     6382                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                6382                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4076                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2250                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore           56                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         6326                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   181.394246                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  1406.259305                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-4095         6214     98.23%     98.23% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-8191           59      0.93%     99.16% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-12287           37      0.58%     99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-16383            6      0.09%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-20479            4      0.06%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-24575            2      0.03%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-28671            3      0.05%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::36864-40959            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         6326                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          893                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11600.783875                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 10727.998992                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5550.111041                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095           41      4.59%      4.59% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          147     16.46%     21.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          548     61.37%     82.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          107     11.98%     94.40% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           11      1.23%     95.63% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            5      0.56%     96.19% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           19      2.13%     98.32% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            3      0.34%     98.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.11%     98.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.56%     99.33% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.34%     99.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::53248-57343            2      0.22%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::61440-65535            1      0.11%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          893                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  11098487732                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.931053                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.253398                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0      765303264      6.90%      6.90% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    10333090968     93.10%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2          93500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  11098487732                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          693     82.80%     82.80% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          144     17.20%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          837                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6861                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6861                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6382                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6382                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1169                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1169                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         8030                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    45813094                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6861                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          837                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          837                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         7219                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     7191521                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6382                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1803,1043 +1813,1040 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1199                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     901                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      526                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      347                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                45819955                       # ITB inst accesses
-system.cpu1.itb.hits                         45813094                       # DTB hits
-system.cpu1.itb.misses                           6861                       # DTB misses
-system.cpu1.itb.accesses                     45819955                       # DTB accesses
-system.cpu1.numCycles                       115872528                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 7197903                       # ITB inst accesses
+system.cpu1.itb.hits                          7191521                       # DTB hits
+system.cpu1.itb.misses                           6382                       # DTB misses
+system.cpu1.itb.accesses                      7197903                       # DTB accesses
+system.cpu1.numCycles                        32425900                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          11244647                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     115696053                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   35362528                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          28295935                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    100513645                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3955668                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     92958                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               43827                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       218813                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       324785                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles        35760                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 45812479                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               133633                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2410                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         114452269                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.250587                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.333322                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           8095443                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      21322301                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    4001540                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           2272245                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     22576717                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 701366                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     87665                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               29928                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       190452                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       273109                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        16492                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  7191191                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               105174                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2314                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          31620489                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.824543                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.195918                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                53787165     47.00%     47.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                15397458     13.45%     60.45% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 8067873      7.05%     67.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                37199773     32.50%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                19556210     61.85%     61.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 4372737     13.83%     75.68% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1374906      4.35%     80.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 6316636     19.98%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           114452269                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.305185                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.998477                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                14331089                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             67536075                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 29425449                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1338809                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1820847                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              912295                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               160061                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              74627346                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              1451044                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1820847                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                19084331                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2925531                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      61205079                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 25977648                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              3438833                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              61437487                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               313811                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               329328                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 50880                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 21104                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               2227690                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           61781071                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            288761968                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        65715217                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             1660                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             58198437                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 3582634                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1923301                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1845273                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 13635165                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            11552975                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            7780383                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           701343                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          925146                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  60392573                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             653667                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 59853310                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           146761                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        4556505                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      7374621                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         54925                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    114452269                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.522954                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.862457                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            31620489                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.123406                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.657570                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 6635373                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             16232056                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  7605382                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               916534                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                231144                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              619166                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               122135                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              20047523                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               930312                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                231144                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 7872130                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2262020                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      11428772                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  7266376                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2560047                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              19035604                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               152359                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               204838                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 28045                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 12601                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1704098                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           18785965                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             89036414                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        21967957                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups                6                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             16823959                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1962006                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            364639                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        299553                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2452699                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             3781052                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            3343720                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           554765                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          448879                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  18340674                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             508914                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 18185979                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            84059                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1788804                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      4127246                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         41236                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     31620489                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.575133                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.924807                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           77949624     68.11%     68.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           17744881     15.50%     83.61% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           14511556     12.68%     96.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3899540      3.41%     99.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             346643      0.30%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5                 25      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           20837444     65.90%     65.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            5408008     17.10%     83.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            3574976     11.31%     94.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            1572233      4.97%     99.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             227820      0.72%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                  8      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      114452269                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       31620489                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3494882     44.84%     44.84% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   604      0.01%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1953801     25.07%     69.91% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              2345303     30.09%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                1135208     27.60%     27.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   664      0.02%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1335102     32.46%     60.07% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1642689     39.93%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               67      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             40748712     68.08%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               52853      0.09%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4129      0.01%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            11462159     19.15%     87.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            7585390     12.67%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               24      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             11205359     61.62%     61.62% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               26215      0.14%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          3128      0.02%     61.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.78% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             3726030     20.49%     82.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            3225223     17.73%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              59853310                       # Type of FU issued
-system.cpu1.iq.rate                          0.516544                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    7794590                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.130228                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         242094525                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         65611557                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     57714006                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads               5715                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              2046                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         1784                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              67644200                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   3633                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          110002                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              18185979                       # Type of FU issued
+system.cpu1.iq.rate                          0.560847                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    4113663                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.226200                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          72190169                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         20646412                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     17793804                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes                 4                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              22299618                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           72560                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       628284                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          842                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        10885                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       426405                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       346468                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          605                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         8056                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       274891                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        57089                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       100676                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        35566                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        53462                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1820847                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 727831                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               179449                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           61101449                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles                231144                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 519259                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               154115                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           18866238                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             11552975                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             7780383                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            331927                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 11154                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               159363                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         10885                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         82141                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       153260                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              235401                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             59500982                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             11329735                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           328066                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts              3781052                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             3343720                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            266301                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  6646                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               141712                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          8056                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         30125                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       104168                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              134293                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             17982694                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              3650056                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           187326                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        55209                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    18836194                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                12894851                       # Number of branches executed
-system.cpu1.iew.exec_stores                   7506459                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.513504                       # Inst execution rate
-system.cpu1.iew.wb_sent                      59314333                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     57715790                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 28288530                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 43462608                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        16650                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     6820794                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 2588349                       # Number of branches executed
+system.cpu1.iew.exec_stores                   3170738                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.554578                       # Inst execution rate
+system.cpu1.iew.wb_sent                      17880625                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     17793804                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  8844802                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 13735859                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.498097                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.650871                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.548753                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.643921                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        4228906                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         598742                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           219024                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    112407306                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.502841                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.169324                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        1618894                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         467678                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           126321                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     31256140                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.545936                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.299262                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     84196637     74.90%     74.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     15782926     14.04%     88.94% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6506905      5.79%     94.73% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       899885      0.80%     95.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      2238894      1.99%     97.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      1696394      1.51%     99.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       469505      0.42%     99.45% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       157300      0.14%     99.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       458860      0.41%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     23000082     73.59%     73.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      4925249     15.76%     89.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1442060      4.61%     93.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       538119      1.72%     95.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       452265      1.45%     97.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       297433      0.95%     98.08% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       181915      0.58%     98.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7        99730      0.32%     98.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       319287      1.02%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    112407306                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            46016034                       # Number of instructions committed
-system.cpu1.commit.committedOps              56522947                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     31256140                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            13926644                       # Number of instructions committed
+system.cpu1.commit.committedOps              17063847                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      18278669                       # Number of memory references committed
-system.cpu1.commit.loads                     10924691                       # Number of loads committed
-system.cpu1.commit.membars                     232005                       # Number of memory barriers committed
-system.cpu1.commit.branches                  12685356                       # Number of branches committed
-system.cpu1.commit.fp_insts                      1784                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 50487985                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             3456157                       # Number of function calls committed.
+system.cpu1.commit.refs                       6503413                       # Number of memory references committed
+system.cpu1.commit.loads                      3434584                       # Number of loads committed
+system.cpu1.commit.membars                     191656                       # Number of memory barriers committed
+system.cpu1.commit.branches                   2466066                       # Number of branches committed
+system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 15229015                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              413334                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        38188356     67.56%     67.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          51793      0.09%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.65% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4129      0.01%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       10924691     19.33%     86.99% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       7353978     13.01%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        10531890     61.72%     61.72% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          25416      0.15%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.87% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         3128      0.02%     61.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.89% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        3434584     20.13%     82.02% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       3068829     17.98%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         56522947                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               458860                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   152481338                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  123545319                       # The number of ROB writes
-system.cpu1.timesIdled                          68699                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        1420259                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5138082707                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   45982821                       # Number of Instructions Simulated
-system.cpu1.committedOps                     56489734                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.519909                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.519909                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.396840                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.396840                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                62666330                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               39173045                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     1381                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                     516                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                211754483                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                18307351                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              158297998                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                426234                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           227119                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          480.780000                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           17377933                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           227440                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            76.406670                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      89481619000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   480.780000                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.939023                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.939023                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          321                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          297                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           24                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.626953                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         36531516                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        36531516                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     10502192                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       10502192                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      6578620                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       6578620                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        65191                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        65191                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        88541                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        88541                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80577                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        80577                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     17080812                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        17080812                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     17146003                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       17146003                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       257246                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       257246                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       477990                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       477990                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        35676                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        35676                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        19120                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        19120                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23513                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23513                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       735236                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        735236                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       770912                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       770912                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4397234500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   4397234500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  13204055417                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  13204055417                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    384125500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    384125500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    615714500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    615714500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2019500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2019500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  17601289917                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  17601289917                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  17601289917                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  17601289917                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     10759438                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     10759438                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      7056610                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      7056610                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       100867                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       100867                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       107661                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       107661                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       104090                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       104090                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     17816048                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     17816048                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     17916915                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     17916915                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023909                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.023909                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.067736                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.067736                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.353693                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.353693                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.177594                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.177594                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225891                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225891                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.041268                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.041268                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043027                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.043027                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17093.499996                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 17093.499996                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27624.124808                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 27624.124808                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20090.245816                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20090.245816                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26186.131076                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26186.131076                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total         17063847                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               319287                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    48731479                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   37726129                       # The number of ROB writes
+system.cpu1.timesIdled                          54512                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         805411                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5642014046                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   13923580                       # Number of Instructions Simulated
+system.cpu1.committedOps                     17060783                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.328848                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.328848                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.429397                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.429397                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                20183446                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               11616875                       # number of integer regfile writes
+system.cpu1.cc_regfile_reads                 64541382                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                 5516447                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads               46291245                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                345789                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           150536                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          478.106753                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            5837857                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           150895                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            38.688207                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      89621465500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   478.106753                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.933802                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.933802                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          359                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          351                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.701172                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         12869097                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        12869097                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3072993                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3072993                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2528751                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2528751                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42878                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        42878                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70516                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        70516                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61926                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        61926                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5601744                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5601744                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5644622                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5644622                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       178967                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       178967                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       316584                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       316584                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23990                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        23990                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17392                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17392                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23411                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23411                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       495551                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        495551                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       519541                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       519541                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3311567500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3311567500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11108580447                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  11108580447                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    357363500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    357363500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    641574000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    641574000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       819500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total       819500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  14420147947                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  14420147947                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  14420147947                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  14420147947                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3251960                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3251960                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2845335                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2845335                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66868                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        66868                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87908                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        87908                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85337                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        85337                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6097295                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6097295                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6164163                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6164163                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.055034                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.055034                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.111264                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.111264                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.358767                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.358767                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.197843                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.197843                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274336                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274336                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.081274                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.081274                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.084284                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.084284                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18503.788408                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 18503.788408                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35088.887774                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 35088.887774                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20547.579347                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20547.579347                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27404.809705                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27404.809705                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23939.646477                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23939.646477                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22831.775763                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 22831.775763                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          342                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1982545                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               37                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          49131                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     9.243243                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    40.352222                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29099.220760                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 29099.220760                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27755.553358                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 27755.553358                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          351                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1652938                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               24                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          30246                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    14.625000                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    54.649805                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       137800                       # number of writebacks
-system.cpu1.dcache.writebacks::total           137800                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        93990                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        93990                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       374320                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       374320                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13607                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13607                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       468310                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       468310                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       468310                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       468310                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       163256                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       163256                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       103670                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       103670                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        32269                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        32269                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5513                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5513                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23513                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23513                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       266926                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       266926                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       299195                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       299195                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        17062                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        17062                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        14341                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        14341                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        31403                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        31403                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2326061500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2326061500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3203086933                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3203086933                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    553503000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    553503000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    109001000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    109001000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    592222500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    592222500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1998500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1998500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5529148433                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   5529148433                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6082651433                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   6082651433                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2940631000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2940631000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2452626000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   2452626000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   5393257000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   5393257000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015173                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.015173                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014691                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014691                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.319916                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.319916                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051207                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051207                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225891                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225891                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014982                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.014982                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.016699                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.016699                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14247.938820                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14247.938820                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30896.951220                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30896.951220                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17152.778208                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17152.778208                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19771.630691                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19771.630691                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25187.024199                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25187.024199                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       150537                       # number of writebacks
+system.cpu1.dcache.writebacks::total           150537                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        62639                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        62639                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       238187                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       238187                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12480                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12480                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       300826                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       300826                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       300826                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       300826                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116328                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       116328                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        78397                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        78397                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23066                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        23066                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4912                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4912                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23411                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23411                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       194725                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       194725                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       217791                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       217791                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3053                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3053                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2412                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2412                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5465                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5465                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1734233000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1734233000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2786620456                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2786620456                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    403892500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    403892500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     94891500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     94891500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    618171000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    618171000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       811500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       811500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4520853456                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4520853456                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4924745956                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4924745956                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    433886500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    433886500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    300722000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    300722000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    734608500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    734608500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035772                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035772                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027553                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027553                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.344948                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.344948                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055877                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055877                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274336                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274336                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031936                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031936                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035332                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035332                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14908.130459                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14908.130459                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35544.988405                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35544.988405                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17510.296540                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17510.296540                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19318.302117                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19318.302117                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26405.151425                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26405.151425                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20714.162101                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20714.162101                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20330.057097                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20330.057097                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172349.724534                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172349.724534                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171021.964995                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171021.964995                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171743.368468                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171743.368468                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23216.605243                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23216.605243                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.256503                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22612.256503                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142118.080576                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142118.080576                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124677.446103                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124677.446103                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134420.585544                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134420.585544                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           672301                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.450521                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           45113050                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           672813                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            67.051395                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      79271830500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.450521                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973536                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973536                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           559207                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.428858                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6611589                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           559719                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            11.812336                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      79408312500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.428858                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975447                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975447                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          497                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           15                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          494                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         92297132                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        92297132                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     45113050                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       45113050                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     45113050                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        45113050                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     45113050                       # number of overall hits
-system.cpu1.icache.overall_hits::total       45113050                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       699105                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       699105                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       699105                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        699105                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       699105                       # number of overall misses
-system.cpu1.icache.overall_misses::total       699105                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6808598319                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6808598319                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6808598319                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6808598319                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6808598319                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6808598319                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     45812155                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     45812155                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     45812155                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     45812155                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     45812155                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     45812155                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.015260                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.015260                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.015260                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.015260                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.015260                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.015260                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9739.021061                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9739.021061                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9739.021061                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9739.021061                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9739.021061                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9739.021061                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       778427                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          223                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            55737                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              2                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.966073                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets   111.500000                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses         14941719                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14941719                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6611589                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6611589                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6611589                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6611589                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6611589                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6611589                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       579409                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       579409                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       579409                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        579409                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       579409                       # number of overall misses
+system.cpu1.icache.overall_misses::total       579409                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5260271690                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5260271690                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5260271690                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5260271690                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5260271690                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5260271690                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      7190998                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      7190998                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      7190998                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      7190998                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      7190998                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      7190998                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.080574                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.080574                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.080574                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.080574                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.080574                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.080574                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9078.684815                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9078.684815                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9078.684815                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9078.684815                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9078.684815                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9078.684815                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       508858                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            41527                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.253666                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        26283                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        26283                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        26283                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        26283                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        26283                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        26283                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       672822                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       672822                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       672822                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       672822                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       672822                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       672822                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.ReadReq_mshr_uncacheable::total          102                       # number of ReadReq MSHR uncacheable
-system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.overall_mshr_uncacheable_misses::total          102                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6167077156                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   6167077156                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6167077156                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   6167077156                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6167077156                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   6167077156                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13506000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13506000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13506000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     13506000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014687                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014687                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014687                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.014687                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014687                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.014687                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9165.986184                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9165.986184                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9165.986184                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9165.986184                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9165.986184                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9165.986184                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132411.764706                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132411.764706                       # average overall mshr uncacheable latency
+system.cpu1.icache.writebacks::writebacks       559207                       # number of writebacks
+system.cpu1.icache.writebacks::total           559207                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        19686                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        19686                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        19686                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        19686                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        19686                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        19686                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       559723                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       559723                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       559723                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       559723                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       559723                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       559723                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          103                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.ReadReq_mshr_uncacheable::total          103                       # number of ReadReq MSHR uncacheable
+system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          103                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.overall_mshr_uncacheable_misses::total          103                       # number of overall MSHR uncacheable misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4814325924                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4814325924                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4814325924                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4814325924                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4814325924                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4814325924                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14117999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14117999                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14117999                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     14117999                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.077837                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.077837                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.077837                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.077837                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.077837                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.077837                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8601.265133                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8601.265133                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8601.265133                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8601.265133                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8601.265133                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8601.265133                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       262736                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       263407                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          604                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       109440                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       110020                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          525                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        68017                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           62303                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15536.648070                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1677232                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           76854                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           21.823614                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        49988                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           32853                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15122.347980                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1241496                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           48030                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           25.848345                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6569.267487                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    14.374590                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.390464                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  4943.655897                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2538.739672                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1470.219959                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.400956                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000877                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000024                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.301737                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.154952                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.089735                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.948282                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1250                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           33                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13268                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           18                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          890                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          342                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14684.371026                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    11.723090                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.949001                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   423.304863                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.896263                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000716                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000180                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.025836                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.922995                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          986                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           52                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14139                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          660                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          322                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           15                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          462                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8543                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4263                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.076294                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002014                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.809814                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        30842090                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       30842090                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        19102                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         7340                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         26442                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks       137798                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total       137798                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1915                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         1915                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1089                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total         1089                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        37080                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        37080                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       650319                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       650319                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       128580                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total       128580                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        19102                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         7340                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       650319                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       165660                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         842421                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        19102                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         7340                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       650319                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       165660                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        842421                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          434                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          283                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          717                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29244                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29244                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22424                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        22424                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        36071                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        36071                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        22492                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        22492                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        72430                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        72430                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          434                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          283                       # number of demand (read+write) misses
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-system.cpu1.l2cache.demand_misses::total       131710                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          434                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          283                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        22492                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data       108501                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       131710                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     10853500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5913500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     16767000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    593983499                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total    593983499                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    472238000                       # number of SCUpgradeReq miss cycles
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-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1967000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1967000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1909781999                       # number of ReadExReq miss cycles
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-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst   1248275500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total   1248275500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1835931492                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1835931492                       # number of ReadSharedReq miss cycles
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-system.cpu1.l2cache.demand_miss_latency::cpu1.inst   1248275500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3745713491                       # number of demand (read+write) miss cycles
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-system.cpu1.l2cache.overall_miss_latency::cpu1.inst   1248275500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3745713491                       # number of overall miss cycles
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-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        19536                       # number of ReadReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadReq_accesses::total        27159                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks       137799                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total       137799                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31159                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        31159                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23513                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23513                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        73151                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        73151                       # number of ReadExReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadCleanReq_accesses::total       672811                       # number of ReadCleanReq accesses(hits+misses)
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-system.cpu1.l2cache.ReadSharedReq_accesses::total       201010                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        19536                       # number of demand (read+write) accesses
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-system.cpu1.l2cache.overall_accesses::cpu1.inst       672811                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       274161                       # number of overall (read+write) accesses
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-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022215                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.037124                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.026400                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000007                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000007                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.938541                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.938541                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.953685                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.953685                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.493103                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.493103                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.033430                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.033430                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.360330                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.360330                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022215                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.037124                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.033430                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.395757                       # miss rate for demand accesses
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-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022215                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.037124                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.033430                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.395757                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.135208                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25008.064516                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20895.759717                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23384.937238                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20311.294590                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20311.294590                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21059.489832                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21059.489832                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52945.080508                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52945.080508                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 55498.643962                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 55498.643962                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25347.666602                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25347.666602                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25008.064516                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20895.759717                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 55498.643962                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34522.386807                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 38043.853853                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25008.064516                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20895.759717                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 55498.643962                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34522.386807                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 38043.853853                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          135                       # number of cycles access was blocked
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           24                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          776                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2695                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10668                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.060181                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003174                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.862976                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        24508280                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       24508280                       # Number of data accesses
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+system.cpu1.l2cache.WritebackDirty_hits::writebacks        93045                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total        93045                       # number of WritebackDirty hits
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+system.cpu1.l2cache.UpgradeReq_miss_latency::total     65970500                       # number of UpgradeReq miss cycles
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+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    617206499                       # number of ReadCleanReq miss cycles
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+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3239426999                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   3872137998                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9644000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5860500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    617206499                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3239426999                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   3872137998                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        12642                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         7302                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total        19944                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks        93045                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total        93045                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       604293                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       604293                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29064                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        29064                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23407                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23407                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        49972                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        49972                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       559721                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       559721                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       144301                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       144301                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        12642                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         7302                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       559721                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       194273                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       773938                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        12642                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         7302                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       559721                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       194273                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       773938                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.034488                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.040263                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.036602                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999957                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999957                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.653446                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.653446                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018631                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018631                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.450142                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.450142                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.034488                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.040263                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018631                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.502437                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.140538                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.034488                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.040263                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018631                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.502437                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.140538                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22119.266055                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19933.673469                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21239.041096                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2269.835535                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2269.835535                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2700.546868                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2700.546868                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       199625                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       199625                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53771.207203                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53771.207203                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59187.427982                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59187.427982                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22839.799233                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22839.799233                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22119.266055                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19933.673469                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59187.427982                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33187.450046                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 35599.974239                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22119.266055                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19933.673469                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59187.427982                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33187.450046                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 35599.974239                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           60                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    22.500000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           30                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        35002                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           35002                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks        26302                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           26302                       # number of writebacks
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           13                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total           14                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1611                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         1611                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst           19                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total           19                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          165                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          165                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           17                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_hits::total           18                       # number of ReadReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1057                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         1057                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            3                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           31                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           31                       # number of ReadSharedReq MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           13                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst           19                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1776                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         1809                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           17                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            3                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1088                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         1109                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           13                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst           19                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1776                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         1809                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          433                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          270                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          703                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         2881                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total         2881                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35799                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        35799                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29244                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29244                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22424                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22424                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34460                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        34460                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        22473                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        22473                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        72265                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        72265                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          433                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          270                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        22473                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data       106725                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       129901                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          433                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          270                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        22473                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data       106725                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35799                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       165700                       # number of overall MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          102                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        17062                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        17164                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        14341                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        14341                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          102                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        31403                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        31505                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      8235500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4129500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     12365000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1812441817                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1812441817                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    689767998                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    689767998                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    415217500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    415217500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1841000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1841000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1591439000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1591439000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst   1112203000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total   1112203000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1393604492                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1393604492                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      8235500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4129500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   1112203000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2985043492                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   4109611492                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      8235500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4129500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   1112203000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2985043492                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1812441817                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   5922053309                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12741000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2803854000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2816595000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   2344848498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   2344848498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12741000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   5148702498                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   5161443498                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022164                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.035419                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025885                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000007                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000007                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           17                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            3                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1088                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         1109                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          435                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          277                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          712                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        19626                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        19626                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29064                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29064                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23406                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23406                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31597                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        31597                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        10425                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        10425                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        64925                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        64925                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          435                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          277                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        10425                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data        96522                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       107659                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          435                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          277                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        10425                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data        96522                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        19626                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total       127285                       # number of overall MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          103                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3053                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3156                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2412                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2412                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          103                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5465                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5568                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7015500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3985000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11000500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1124452152                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1124452152                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    598927500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    598927500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    441961500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    441961500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       750500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       750500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1488249500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1488249500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    554608999                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    554608999                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1092439499                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1092439499                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7015500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3985000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    554608999                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2580688999                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3146298498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7015500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3985000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    554608999                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2580688999                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1124452152                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4270750650                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13345000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    409170500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    422515500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    282391996                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    282391996                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13345000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    691562496                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    704907496                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.034409                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.037935                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.035700                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.938541                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.938541                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.953685                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.953685                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.471080                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.471080                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.033402                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.033402                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.359509                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.359509                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022164                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.035419                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.033402                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.389279                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.133351                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022164                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.035419                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.033402                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.389279                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999957                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999957                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.632294                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.632294                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018625                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018625                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.449928                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.449928                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.034409                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.037935                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018625                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.496837                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.139105                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.034409                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.037935                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018625                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.496837                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.170100                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17588.904694                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50628.280594                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23586.650185                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23586.650185                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18516.656261                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18516.656261                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46182.211259                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46182.211259                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49490.633204                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49490.633204                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19284.639756                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19284.639756                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49490.633204                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27969.486924                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31636.488495                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49490.633204                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27969.486924                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35739.609590                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164333.255187                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164098.986250                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163506.624224                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163506.624224                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 163955.752571                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163829.344485                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.164464                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15450.140449                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57294.005503                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20607.194467                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20607.194467                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18882.401948                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18882.401948                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       187625                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       187625                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47100.974776                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47100.974776                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53199.903981                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53199.903981                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16826.176342                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16826.176342                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53199.903981                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26736.795746                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29224.667682                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53199.903981                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26736.795746                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33552.662529                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134022.436947                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133876.901141                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117077.941957                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117077.941957                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126543.915096                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126599.765805                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1911239                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       964293                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        15206                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       115900                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       115705                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          195                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         49800                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       965132                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        14341                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        14341                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback       177279                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict       810351                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        43777                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        73201                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42982                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        89676                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           33                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        81502                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        78977                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       672822                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       286780                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq          213                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2005740                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1027154                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        17080                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        42715                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          3092689                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     43061536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29508655                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        30492                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        78144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          72678827                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     390895                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      2268265                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.069071                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.253913                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1523677                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       769701                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12410                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       171538                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       169858                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1680                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         26336                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       768409                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2412                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2412                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       120538                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       604293                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        90253                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        23776                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        71073                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41600                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85044                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           15                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        57287                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        54410                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       559723                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       223005                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           24                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1668415                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       728070                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        15878                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        27246                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2439609                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     70944752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24680600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        29208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          95705128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     366083                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1123000                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.171945                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.381277                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           2111789     93.10%     93.10% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            156281      6.89%     99.99% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               195      0.01%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0            931586     82.96%     82.96% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            189734     16.90%     99.85% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              1680      0.15%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       2268265                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1127589981                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     88549490                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1123000                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1483438992                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     80062850                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1009459749                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    839820234                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    464204253                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    323064197                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      9470972                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      8585980                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     23200956                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     14617972                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31010                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31010                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                31018                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31018                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               59424                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              59424                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56618                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          846                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2855,16 +2862,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       107912                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       107932                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180864                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180884                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71562                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          447                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2880,67 +2887,67 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       162794                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484042                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  2484060                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             40405000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               111500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                15500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                90500                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               504000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               581000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               49500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6141000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              169500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            34081000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              124500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186507978                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           186321543                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            84714000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36458                       # number of replacements
-system.iocache.tags.tagsinuse               14.440882                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.554671                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256003407000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.440882                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.902555                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.902555                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         256310853000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.554671                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.909667                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.909667                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2954,14 +2961,14 @@ system.iocache.demand_misses::realview.ide          252                       #
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
 system.iocache.overall_misses::total              252                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32773877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32773877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4715888101                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4715888101                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32773877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32773877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32773877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32773877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32664376                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32664376                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4736716167                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4736716167                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32664376                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32664376                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32664376                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32664376                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2978,19 +2985,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 130055.067460                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 130055.067460                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130186.840244                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130186.840244                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 130055.067460                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 130055.067460                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 130055.067460                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 130055.067460                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            42                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 129620.539683                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 129620.539683                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130761.819981                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130761.819981                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 129620.539683                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 129620.539683                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 129620.539683                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 129620.539683                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           734                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   10                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   91                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     4.200000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.065934                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -3004,14 +3011,14 @@ system.iocache.demand_mshr_misses::realview.ide          252
 system.iocache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          252                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          252                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     20173877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     20173877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2904688101                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2904688101                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     20173877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     20173877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     20173877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     20173877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     20064376                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     20064376                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2925516167                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2925516167                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     20064376                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     20064376                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     20064376                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     20064376                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -3020,603 +3027,602 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80055.067460                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 80055.067460                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80186.840244                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80186.840244                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 80055.067460                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 80055.067460                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 80055.067460                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 80055.067460                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79620.539683                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 79620.539683                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80761.819981                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80761.819981                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 79620.539683                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 79620.539683                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 79620.539683                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 79620.539683                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   129384                       # number of replacements
-system.l2c.tags.tagsinuse                63948.068698                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     411864                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   193785                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.125366                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   124125                       # number of replacements
+system.l2c.tags.tagsinuse                63228.123175                       # Cycle average of tags in use
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+system.l2c.tags.sampled_refs                   188206                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.339739                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   12531.983329                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    14.494639                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     2.048364                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     6442.782513                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2029.980541                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34279.633489                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    10.674973                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.902888                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3492.124605                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1459.870620                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  3683.572737                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000221                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000163                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_blocks::cpu0.itb.walker     1.063314                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34966.595872                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.597372                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker     0.909987                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1640.209162                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      501.782314                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1607.058034                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.204506                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.053286                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.022276                       # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1022::2          130                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         6088                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        24764                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           30                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1024::2          427                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5063                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        27875                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.472809                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000458                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.509415                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  5503227                       # Number of tag accesses
-system.l2c.tags.data_accesses                 5503227                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks          228886                       # number of Writeback hits
-system.l2c.Writeback_hits::total               228886                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            2462                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             805                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                3267                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           259                       # number of SCUpgradeReq hits
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-system.l2c.SCUpgradeReq_hits::total               365                       # number of SCUpgradeReq hits
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-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          184                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker           77                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        33993                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        45721                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45094                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           77                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           41                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst        17373                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        11135                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         7486                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           161181                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           184                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker            77                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               33993                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               49655                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        45094                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            77                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            41                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               17373                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               13304                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         7486                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  167284                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          184                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker           77                       # number of overall hits
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-system.l2c.overall_hits::cpu0.data              49655                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        45094                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           77                       # number of overall hits
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-system.l2c.overall_hits::cpu1.inst              17373                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              13304                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         7486                       # number of overall hits
-system.l2c.overall_hits::total                 167284                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          8340                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3970                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             12310                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          899                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1200                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            2099                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          10813                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           8272                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              19085                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker           24                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker            5                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        17052                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data         7978                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       127774                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker           14                       # number of ReadSharedReq misses
+system.l2c.tags.occ_percent::cpu1.inst       0.025028                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.024522                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.964785                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        30882                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        33176                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          142                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         5961                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4        24779                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          587                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         4232                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        28320                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.471222                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000351                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.506226                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  6006105                       # Number of tag accesses
+system.l2c.tags.data_accesses                 6006105                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks       259490                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          259490                       # number of WritebackDirty hits
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+system.l2c.UpgradeReq_hits::cpu1.data            1866                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total               34419                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data          2126                       # number of SCUpgradeReq hits
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-system.l2c.ReadSharedReq_misses::total         169401                       # number of ReadSharedReq misses
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 system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
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 system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
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-system.l2c.overall_misses::total               188486                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data     18505000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     12201500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     30706500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2576000                       # number of SCUpgradeReq miss cycles
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-system.l2c.SCUpgradeReq_miss_latency::total      6067000                       # number of SCUpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::total   2749771000                       # number of ReadExReq miss cycles
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 system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker       132500                       # number of ReadSharedReq miss cycles
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 system.l2c.demand_miss_latency::cpu1.itb.walker       132500                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu1.itb.walker       132500                       # number of overall miss cycles
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-system.l2c.Writeback_accesses::writebacks       228886                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           228886                       # number of Writeback accesses(hits+misses)
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-system.l2c.demand_accesses::cpu1.l2cache.prefetcher        16781                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              355770                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          208                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker           82                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          51045                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          68446                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       172868                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker           91                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker           42                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          22457                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          23750                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher        16781                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             355770                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.772079                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.831414                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.790268                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.776339                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.918836                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.851867                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.733234                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.792261                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.757702                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.060976                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.334058                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.148569                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.739142                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.153846                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.023810                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.226388                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.163348                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.553900                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.512433                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.060976                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.334058                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.274538                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.739142                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.153846                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.023810                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.226388                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.439832                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.553900                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.529797                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.115385                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.060976                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.334058                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.274538                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.739142                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.153846                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.023810                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.226388                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.439832                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.553900                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.529797                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2218.824940                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3073.425693                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2494.435418                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2865.406007                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2909.166667                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2890.424011                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 152007.953389                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133717.238878                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 144080.220068                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140916.666667                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       130800                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132495.924290                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138931.436450                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 158098.213322                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 136892.857143                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_latency::cpu1.inst    358675500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1205167500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1053631366                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    28839065081                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       259490                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       259490                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        42290                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4340                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           46630                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2986                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2303                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          5289                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15327                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data         9573                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            24900                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          273                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker          138                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu0.data        58061                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       180100                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu1.data         6356                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8621                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       319262                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          273                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker          138                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           55232                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           73388                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       180100                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.inst           10424                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           15929                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8621                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              344162                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          273                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker          138                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       180100                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.data          15929                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8621                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             344162                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.230244                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.570046                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.261870                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.288011                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.574468                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.412743                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.726039                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.839444                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.769639                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.102564                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.021739                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.353907                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.157197                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.133333                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.083333                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.256715                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.151510                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.532610                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.102564                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.021739                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.353907                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.275999                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.133333                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.083333                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.256715                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.564944                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.549759                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.102564                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.021739                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.353907                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.275999                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.133333                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.083333                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.256715                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.564944                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.549759                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3150.097566                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2311.236863                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2980.140857                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6523.837209                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  3034.391534                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4409.070087                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151701.923077                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133108.138377                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 143905.030265                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 147428.571429                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average ReadSharedReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138226.416128                       # average ReadSharedReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 135166.666667                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       132500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135189.712825                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139307.957682                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 176785.010005                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 154709.938418                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140916.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker       130800                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 132495.924290                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 146456.122612                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 158098.213322                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136892.857143                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134034.192825                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140717.030114                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 180077.143394                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 153381.335676                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 147428.571429                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 135166.666667                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.itb.walker       132500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 135189.712825                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 134880.767758                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 176785.010005                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 153633.634742                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140916.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker       130800                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 132495.924290                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 146456.122612                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 158098.213322                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136892.857143                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 134034.192825                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 133922.380264                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 180077.143394                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 152421.514545                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.data 145629.795112                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135166.666667                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.itb.walker       132500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 135189.712825                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 134880.767758                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 176785.010005                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 153633.634742                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               389                       # number of cycles access was blocked
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 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
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 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs    129.666667                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               99650                       # number of writebacks
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+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      3848000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       358000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   2394620001                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2747181500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  19357474714                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       751000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       122500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    635761500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1304504500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1550266668                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  27072108278                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    344034000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3293772500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10902500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2496744500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6145453500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2525916538                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2101048002                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4626964540                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    344034000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5819689038                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10902500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4597792502                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10772418040                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    331521500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1115177500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    995121366                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  26946176081                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    344048000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5800891500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11490000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    354220500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6510650000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4694686038                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    241361004                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4936047042                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    344048000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10495577538                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11490000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    595581504                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  11446697042                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.772079                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.831414                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.790268                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.776339                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.918836                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.851867                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.733234                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.792261                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.757702                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.060976                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.334019                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.148569                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739142                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.153846                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.023810                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.226077                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.163348                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553900                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.512405                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.060976                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.334019                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.274538                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739142                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.153846                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.023810                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.226077                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.439832                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553900                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.529772                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.115385                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.060976                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.334019                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.274538                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739142                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.153846                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.023810                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.226077                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.439832                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.553900                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.529772                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75444.184652                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75349.496474                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75413.647522                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77427.701891                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        76740                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77034.542163                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 142007.953389                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123717.238878                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 134080.220068                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       120800                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122503.372493                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128931.436450                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.230244                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.570046                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.261870                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.288011                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.574468                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.412743                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726039                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.839444                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.769639                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.102564                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.021739                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.353853                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.157197                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.133333                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.256236                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.151510                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.532585                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.102564                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.021739                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.353853                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.275999                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.133333                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.256236                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.564944                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.549735                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.102564                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.021739                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.353853                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.275999                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.133333                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.256236                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.564944                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.549735                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75545.445209                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75297.493937                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75495.209238                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77613.373256                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76659.486017                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77035.273019                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141701.923077                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123108.138377                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 133905.030265                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122524.560018                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128226.416128                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125223.852669                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129307.957682                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144712.780285                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       120800                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122503.372493                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136456.122612                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124118.869337                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130717.030114                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143383.206188                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122524.560018                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135629.795112                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125223.852669                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124880.767758                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 143636.137449                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       120800                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122503.372493                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136456.122612                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124118.869337                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123922.380264                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 142423.155007                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122524.560018                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135629.795112                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125223.852669                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124880.767758                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 143636.137449                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183415.330215                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146359.370420                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161200.679380                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151171.017895                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146506.380448                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149016.571337                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167874.031154                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146426.512803                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 155731.543232                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124118.869337                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123922.380264                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 142423.155007                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.248131                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116137.868852                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171355.441505                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164737.386413                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100066.751244                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159690.942802                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173952.160203                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109040.919810                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 166122.879936                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               38123                       # Transaction distribution
-system.membus.trans_dist::ReadResp             207766                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31050                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31050                       # Transaction distribution
-system.membus.trans_dist::Writeback            135856                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            15674                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            78082                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          41568                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14509                       # Transaction distribution
+system.membus.trans_dist::ReadReq               37995                       # Transaction distribution
+system.membus.trans_dist::ReadResp             208280                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30910                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30910                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       133887                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14956                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            74359                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40536                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           14484                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             38794                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            18985                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        169644                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             38707                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19074                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        170286                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107912                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14282                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       661810                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       784044                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13724                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       655631                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       777327                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108934                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108934                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 892978                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162794                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                 886261                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28564                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18481720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18673398                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27448                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18402504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18593084                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20991542                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           125523                       # Total snoops (count)
-system.membus.snoop_fanout::samples            585264                       # Request fanout histogram
+system.membus.pkt_size::total                20911228                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           120617                       # Total snoops (count)
+system.membus.snoop_fanout::samples            578108                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  585264    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  578108    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              585264                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81621000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              578108                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81934000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               27500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11798981                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11360491                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           986725496                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           977870256                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1119474906                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1121733386                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64610767                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64044757                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -3659,56 +3665,56 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests       957960                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       483276                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       165836                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          22284                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        21444                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          840                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              38126                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            494242                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31050                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31050                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           364748                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           86802                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           81249                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         41933                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         123182                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           33                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           33                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50538                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50538                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       456132                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests       989446                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       534228                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       146104                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          20085                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        19207                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          878                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              37998                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            475278                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30910                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30910                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       393382                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           89983                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          108688                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43642                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         152330                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           15                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50244                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50244                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       437296                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1043214                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       384499                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1427713                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31299443                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6394691                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               37694134                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          458404                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          1229453                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.314167                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.465653                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1240411                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       256111                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1496522                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34963008                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3945788                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               38908796                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          440874                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           905624                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.341764                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.476341                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 844039     68.65%     68.65% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 384574     31.28%     99.93% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    840      0.07%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 596992     65.92%     65.92% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 307754     33.98%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    878      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            1229453                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          827244513                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             905624                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          871666747                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           355623                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           356120                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         603608816                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         657174901                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         273833055                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         205942747                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    2086                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1875                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2733                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2747                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 886ff6be1..d68f4bed9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.832619                       # Number of seconds simulated
-sim_ticks                                2832618668500                       # Number of ticks simulated
-final_tick                               2832618668500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.832918                       # Number of seconds simulated
+sim_ticks                                2832917624000                       # Number of ticks simulated
+final_tick                               2832917624000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  90415                       # Simulator instruction rate (inst/s)
-host_op_rate                                   109666                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2263800643                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 628336                       # Number of bytes of host memory used
-host_seconds                                  1251.27                       # Real time elapsed on the host
-sim_insts                                   113133035                       # Number of instructions simulated
-sim_ops                                     137220830                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  90340                       # Simulator instruction rate (inst/s)
+host_op_rate                                   109574                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2263201768                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 628644                       # Number of bytes of host memory used
+host_seconds                                  1251.73                       # Real time elapsed on the host
+sim_insts                                   113081477                       # Number of instructions simulated
+sim_ops                                     137157144                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         1600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1321728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9386216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1316032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9392488                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10710952                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1321728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1321728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8026688                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10711336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1316032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1316032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8002368                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8044212                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           25                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22899                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147180                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8019892                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22810                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             147278                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170126                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          125417                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170132                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          125037                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129798                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            565                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker            158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               466610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3313618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               129418                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            474                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            181                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               464550                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3315482                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3781290                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          466610                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             466610                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2833663                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data                6187                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2839850                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2833663                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           565                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker           158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              466610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3319804                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 3781026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          464550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             464550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2824780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2830965                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2824780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           181                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              464550                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3321668                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6621140                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170127                       # Number of read requests accepted
-system.physmem.writeReqs                       129798                       # Number of write requests accepted
-system.physmem.readBursts                      170127                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129798                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10879424                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8704                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8056320                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10711016                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8044212                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      136                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6611992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170133                       # Number of read requests accepted
+system.physmem.writeReqs                       129418                       # Number of write requests accepted
+system.physmem.readBursts                      170133                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129418                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10877696                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10816                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8031936                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10711400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8019892                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      169                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          40796                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11277                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10595                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11086                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11282                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12957                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9975                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10510                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10855                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10363                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10082                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10269                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9303                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9940                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11053                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10302                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10142                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8501                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7938                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8637                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8770                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7610                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7376                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7709                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8071                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7782                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7594                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7680                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6982                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7590                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8396                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7757                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7487                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          48557                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11298                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10506                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10925                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11199                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12883                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10202                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10845                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11219                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10577                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10527                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10037                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8948                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9970                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10631                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9988                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10209                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8496                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7860                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8364                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8532                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7663                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7568                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8029                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8274                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8070                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7909                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7508                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6646                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7551                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8006                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7465                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7558                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832618457500                       # Total gap between requests
+system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2832917392000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166575                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166581                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125417                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150718                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16419                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 125037                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150592                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16496                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
@@ -159,155 +159,156 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5703                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7853                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7455                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6629                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      279                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      165                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2033                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5707                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7704                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7922                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7435                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7511                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6870                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6611                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6539                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       47                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      304.834026                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.217682                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.637512                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23314     37.53%     37.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14709     23.68%     61.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6728     10.83%     72.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3491      5.62%     77.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2622      4.22%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1595      2.57%     84.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1577      2.54%     86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1006      1.62%     88.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7076     11.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62118                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6287                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.034993                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      563.024200                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6286     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::59                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        62145                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      304.281406                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.810971                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.663684                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23300     37.49%     37.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14989     24.12%     61.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6559     10.55%     72.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3523      5.67%     77.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2511      4.04%     81.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1609      2.59%     84.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1592      2.56%     87.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1065      1.71%     88.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6997     11.26%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62145                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6266                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.121768                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      563.971651                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6265     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6287                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6287                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.022268                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.451800                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.249481                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5461     86.86%     86.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             111      1.77%     88.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              41      0.65%     89.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             176      2.80%     92.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              30      0.48%     92.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             149      2.37%     94.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              46      0.73%     95.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               9      0.14%     95.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              13      0.21%     96.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              18      0.29%     96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.08%     96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.05%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             163      2.59%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.06%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               8      0.13%     99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              20      0.32%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.05%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.67% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6266                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6266                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.028567                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.454463                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.210745                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5460     87.14%     87.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             110      1.76%     88.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              30      0.48%     89.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             168      2.68%     92.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              26      0.41%     92.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             137      2.19%     94.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              53      0.85%     95.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              15      0.24%     95.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              11      0.18%     95.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              21      0.34%     96.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.10%     96.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.11%     96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             165      2.63%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.08%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              23      0.37%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.66% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-115             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            13      0.21%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             4      0.06%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6287                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2109686750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5297018000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849955000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12410.58                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            12      0.19%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6266                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2116809750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5303634750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849820000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12454.46                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31160.58                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31204.46                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.78                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.84                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.83                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.90                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139766                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93986                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.22                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.64                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9444422.63                       # Average gap between requests
-system.physmem.pageHitRate                      79.00                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  244301400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  133299375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 690588600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                418685760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185012602320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83544770610                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626283896000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896328144065                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.462100                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705327267750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94587220000                       # Time in different power states
+system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139542                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93775                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.70                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9457212.27                       # Average gap between requests
+system.physmem.pageHitRate                      78.96                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  246546720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  134524500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 694792800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                419813280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           185031927600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            83588992920                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626422631000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1896539228820                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.466691                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705562728250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94597100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32700163500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32757782250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  225310680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  122937375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 635333400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                397016640                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185012602320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            82147816890                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627509294000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896050311305                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.364017                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2707380849000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94587220000                       # Time in different power states
+system.physmem_1.actEnergy                  223269480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  121823625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 630918600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                393420240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           185031927600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            81878542335                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1627923026250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1896202928130                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.347979                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2708066096500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94597100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30650586000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30247332250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
@@ -327,15 +328,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46909632                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24036779                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233520                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29533462                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21344460                       # Number of BTB hits
+system.cpu.branchPred.lookups                46858822                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24018425                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1233385                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29501817                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21322160                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.272123                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11742450                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33774                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.274057                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11724285                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33905                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -366,79 +367,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     71741                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                71741                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29467                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22287                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19987                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        51754                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   426.227924                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2584.933278                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-8191        50562     97.70%     97.70% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-16383          857      1.66%     99.35% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::16384-24575          291      0.56%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::24576-32767           20      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-40959           10      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::40960-49151            9      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::49152-57343            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-73727            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::81920-90111            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::90112-98303            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        51754                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17702                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9865.120013                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8642.768996                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17474     98.71%     98.71% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535          221      1.25%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                     71435                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                71435                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29241                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22400                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19794                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        51641                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   426.153638                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2576.445985                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        49864     96.56%     96.56% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          585      1.13%     97.69% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          525      1.02%     98.71% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383          340      0.66%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::16384-20479           52      0.10%     99.47% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          220      0.43%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::24576-28671           14      0.03%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::28672-32767           10      0.02%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            8      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151           11      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::53248-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::57344-61439            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::61440-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        51641                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17522                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11533.700491                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9159.086359                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8173.463802                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        17339     98.96%     98.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535          177      1.01%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-360447            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17702                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131083168816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.618031                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.493607                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131025996816     99.96%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      38371000      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       7847500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6991500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1099000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11       491500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13      1479000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15       882500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        17522                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131382086816                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.616564                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.493575                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  131327318816     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      37570000      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       7000000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6185500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1198500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11       643000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13      1366500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15       794500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::16-17        10000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131083168816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6361     82.57%     82.57% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1343     17.43%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7704                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71741                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131382086816                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6381     82.69%     82.69% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1336     17.31%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7717                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71435                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71741                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7704                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71435                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7717                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7704                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        79445                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7717                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        79152                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25458814                       # DTB read hits
-system.cpu.dtb.read_misses                      61805                       # DTB read misses
-system.cpu.dtb.write_hits                    19912938                       # DTB write hits
-system.cpu.dtb.write_misses                      9936                       # DTB write misses
+system.cpu.dtb.read_hits                     25445516                       # DTB read hits
+system.cpu.dtb.read_misses                      61525                       # DTB read misses
+system.cpu.dtb.write_hits                    19906341                       # DTB write hits
+system.cpu.dtb.write_misses                      9910                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4319                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       361                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   2196                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4317                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                       358                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   2185                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1314                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25520619                       # DTB read accesses
-system.cpu.dtb.write_accesses                19922874                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1330                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 25507041                       # DTB read accesses
+system.cpu.dtb.write_accesses                19916251                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45371752                       # DTB hits
-system.cpu.dtb.misses                           71741                       # DTB misses
-system.cpu.dtb.accesses                      45443493                       # DTB accesses
+system.cpu.dtb.hits                          45351857                       # DTB hits
+system.cpu.dtb.misses                           71435                       # DTB misses
+system.cpu.dtb.accesses                      45423292                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -468,54 +474,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     11944                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                11944                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3964                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         7740                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore          240                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11704                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   651.102187                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2927.030280                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        11135     95.14%     95.14% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::4096-8191          148      1.26%     96.40% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          183      1.56%     97.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383           77      0.66%     98.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479          110      0.94%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           40      0.34%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::28672-32767            6      0.05%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-36863            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11704                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3569                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 13485.850378                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  8473.200886                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         2612     73.19%     73.19% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          916     25.67%     98.85% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151           38      1.06%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-147455            3      0.08%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3569                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  23708925416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.962784                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.189405                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       882867000      3.72%      3.72% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     22825544916     96.27%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2          513500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  23708925416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          3010     90.42%     90.42% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           319      9.58%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3329                       # Table walker page sizes translated
+system.cpu.itb.walker.walks                     11899                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                11899                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3941                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         7737                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore          221                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples        11678                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   616.629560                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2880.318774                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        11122     95.24%     95.24% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::4096-8191          159      1.36%     96.60% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          193      1.65%     98.25% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383           62      0.53%     98.78% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           98      0.84%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           32      0.27%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total        11678                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3549                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12870.386024                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10191.624224                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  8688.844550                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         2600     73.26%     73.26% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          892     25.13%     98.39% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151           55      1.55%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3549                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  24007842416                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.962955                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.189019                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       889977000      3.71%      3.71% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     23117314916     96.29%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2          493000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3           57500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  24007842416                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          3008     90.38%     90.38% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           320      9.62%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3328                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11944                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        11944                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11899                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        11899                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3329                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3329                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        15273                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66274552                       # ITB inst hits
-system.cpu.itb.inst_misses                      11944                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3328                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3328                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        15227                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66219818                       # ITB inst hits
+system.cpu.itb.inst_misses                      11899                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -524,143 +531,143 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3096                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3095                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2199                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2205                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66286496                       # ITB inst accesses
-system.cpu.itb.hits                          66274552                       # DTB hits
-system.cpu.itb.misses                           11944                       # DTB misses
-system.cpu.itb.accesses                      66286496                       # DTB accesses
-system.cpu.numCycles                        277645869                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66231717                       # ITB inst accesses
+system.cpu.itb.hits                          66219818                       # DTB hits
+system.cpu.itb.misses                           11899                       # DTB misses
+system.cpu.itb.accesses                      66231717                       # DTB accesses
+system.cpu.numCycles                        278809396                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104816225                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184723631                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46909632                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33086910                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     160672113                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6155878                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     195967                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 9078                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        333869                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       563276                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          182                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66274743                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1128462                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5280                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          269668649                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.835474                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.219488                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104752228                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184594753                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46858822                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33046445                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     161837102                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6149420                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     189977                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 9772                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        357687                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       560902                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          181                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66220013                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1133469                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5179                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          270782559                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.831431                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.217897                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                170383279     63.18%     63.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29238814     10.84%     74.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14077384      5.22%     79.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55969172     20.75%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                171565839     63.36%     63.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29222654     10.79%     74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14067780      5.20%     79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55926286     20.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            269668649                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168955                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.665321                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77872075                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             120737431                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64613956                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3845227                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2599960                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3423402                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                486431                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157413712                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3694235                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2599960                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83719189                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11483136                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       75823110                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62612793                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33430461                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146780851                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                948885                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                459435                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  64832                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  17222                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30677805                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150464365                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678641295                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164414257                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10882                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141779508                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8684854                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2843849                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2647501                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13873635                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26407527                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21301019                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1697624                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2214062                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143514940                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2121406                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143299756                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            270446                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8415512                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14711754                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125531                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     269668649                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.531392                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.866832                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            270782559                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.168068                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.662082                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77849645                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             121907615                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64584092                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3844418                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2596789                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3423202                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                486322                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157325754                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3698413                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2596789                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83693975                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11775859                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76672657                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62585691                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33457588                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146699029                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                957260                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                452831                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  63761                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  16550                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30707740                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150373398                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678238170                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164317610                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10889                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             141712294                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8661101                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2840653                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2644485                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13863116                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26394295                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21292545                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1689185                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2215742                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143439670                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2121732                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143229007                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            270292                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8404254                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14686510                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125844                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270782559                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.528945                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.865530                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           181393020     67.27%     67.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45154562     16.74%     84.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            32029362     11.88%     95.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10280384      3.81%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              811287      0.30%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                  34      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           182544969     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45137079     16.67%     84.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32020155     11.83%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10269839      3.79%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              810484      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       269668649                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270782559                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7353326     32.78%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     31      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5633689     25.11%     57.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9445566     42.11%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7336568     32.74%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     32      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5631848     25.13%     57.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9441706     42.13%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95980665     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113853      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95930740     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               113813      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -684,101 +691,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.06% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           8580      0.01%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26189090     18.28%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21005231     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           8576      0.01%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26175663     18.28%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20997878     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143299756                       # Type of FU issued
-system.cpu.iq.rate                           0.516124                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22432612                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156543                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          578935614                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         154057233                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140187198                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               35605                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              13116                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        11364                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165706663                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   23368                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           323603                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              143229007                       # Type of FU issued
+system.cpu.iq.rate                           0.513717                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22410154                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156464                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          579885434                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153971015                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140120635                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               35585                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              13122                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        11367                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              165613479                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   23345                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           322744                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1496259                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          507                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18537                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       706534                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1495175                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          502                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18526                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       703988                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        88309                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6292                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        87827                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6407                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2599960                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1252151                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                541403                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145836919                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2596789                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1243570                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                532137                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145762333                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26407527                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21301019                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096274                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  18146                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                505783                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18537                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317326                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471404                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               788730                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142356745                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25786743                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            871381                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26394295                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21292545                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1096246                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17995                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                497968                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18526                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317449                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471196                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               788645                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142286885                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25773498                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            870795                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200573                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46662722                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26519669                       # Number of branches executed
-system.cpu.iew.exec_stores                   20875979                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.512728                       # Inst execution rate
-system.cpu.iew.wb_sent                      141970613                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140198562                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63271886                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95802115                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        200931                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46642508                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26501737                       # Number of branches executed
+system.cpu.iew.exec_stores                   20869010                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.510337                       # Inst execution rate
+system.cpu.iew.wb_sent                      141900432                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140132002                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63223126                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95712973                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.504955                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660444                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.502609                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660549                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7621436                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995875                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755541                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    266730475                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.515036                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.120154                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7603118                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995888                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755464                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    267848804                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.512648                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.117834                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    193314140     72.48%     72.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43245727     16.21%     88.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15468136      5.80%     94.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4389606      1.65%     96.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6355153      2.38%     98.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1682348      0.63%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       799161      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       412032      0.15%     99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1064172      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    194453826     72.60%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43232556     16.14%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15468323      5.78%     94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4394328      1.64%     96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6341907      2.37%     98.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1685586      0.63%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       800919      0.30%     99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       412081      0.15%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1059278      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    266730475                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113287940                       # Number of instructions committed
-system.cpu.commit.committedOps              137375735                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    267848804                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113236382                       # Number of instructions committed
+system.cpu.commit.committedOps              137312049                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45505753                       # Number of memory references committed
-system.cpu.commit.loads                      24911268                       # Number of loads committed
-system.cpu.commit.membars                      814898                       # Number of memory barriers committed
-system.cpu.commit.branches                   26034583                       # Number of branches committed
+system.cpu.commit.refs                       45487677                       # Number of memory references committed
+system.cpu.commit.loads                      24899120                       # Number of loads committed
+system.cpu.commit.membars                      814929                       # Number of memory barriers committed
+system.cpu.commit.branches                   26016406                       # Number of branches committed
 system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120199859                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4887749                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120142081                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4881652                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91748615     66.79%     66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          112788      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91703052     66.78%     66.78% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          112745      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -802,501 +809,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc         8579      0.01%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc         8575      0.01%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24911268     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20594485     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24899120     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20588557     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137375735                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1064172                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    388465780                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292930075                       # The number of ROB writes
-system.cpu.timesIdled                          888709                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7977220                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5387591469                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113133035                       # Number of Instructions Simulated
-system.cpu.committedOps                     137220830                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.454154                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.454154                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.407472                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.407472                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155797969                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88612711                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      9524                       # number of floating regfile reads
+system.cpu.commit.op_class_0::total         137312049                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1059278                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    389547304                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292761659                       # The number of ROB writes
+system.cpu.timesIdled                          892855                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         8026837                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5387025853                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113081477                       # Number of Instructions Simulated
+system.cpu.committedOps                     137157144                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.465562                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.465562                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.405587                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.405587                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155726558                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88564579                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      9527                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502896975                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53174784                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               347572280                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521694                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            840044                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.925899                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40105851                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            840556                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.713479                       # Average number of references to valid blocks.
+system.cpu.cc_regfile_reads                 502647570                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53157224                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               348272878                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521665                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            837515                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.925653                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40092431                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            838027                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.841455                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.925899                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.925653                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179336842                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179336842                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23308523                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23308523                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15546666                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15546666                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       346021                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        346021                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441431                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441431                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460353                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460353                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38855189                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38855189                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39201210                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39201210                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       708825                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        708825                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3606988                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3606988                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177865                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177865                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27388                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27388                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4315813                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4315813                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4493678                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4493678                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11757743000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11757743000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232345213174                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232345213174                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    375611000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    375611000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       278000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       278000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244102956174                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244102956174                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244102956174                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244102956174                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24017348                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24017348                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19153654                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19153654                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523886                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523886                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468819                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468819                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460358                       # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::cpu.data     43171002                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43171002                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43694888                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43694888                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029513                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029513                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188319                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188319                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339511                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339511                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.058419                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.058419                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000011                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099970                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099970                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102842                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102842                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16587.652806                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16587.652806                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64415.299739                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64415.299739                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13714.436980                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13714.436980                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55600                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55600                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56560.132743                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56560.132743                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54321.416927                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54321.416927                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       869823                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses         179262738                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179262738                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23296604                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23296604                       # number of ReadReq hits
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+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057868                       # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000015                       # miss rate for StoreCondReq accesses
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+system.cpu.dcache.demand_miss_rate::total     0.099913                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102788                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102788                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16514.488582                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16514.488582                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64546.479282                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64546.479282                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13811.191389                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13811.191389                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56650.632401                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56650.632401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54405.469557                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54405.469557                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       871729                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6812                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6864                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.689812                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.000146                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       698262                       # number of writebacks
-system.cpu.dcache.writebacks::total            698262                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       293573                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       293573                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307033                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3307033                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18933                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18933                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3600606                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3600606                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3600606                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3600606                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       415252                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       415252                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299955                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299955                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119671                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119671                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8455                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8455                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       715207                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       715207                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       834878                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       834878                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks       695593                       # number of writebacks
+system.cpu.dcache.writebacks::total            695593                       # number of writebacks
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+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18735                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18735                       # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_misses::total       299628                       # number of WriteReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total       119644                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8393                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8393                       # number of LoadLockedReq MSHR misses
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 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6403711500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6403711500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19964415469                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19964415469                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1698297000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1698297000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126773500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126773500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       273000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       273000                       # number of StoreCondReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total  26368126969                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28066423969                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28066423969                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5935894500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5935894500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4789947462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4789947462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10725841962                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  10725841962                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017290                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017290                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015660                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015660                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228429                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228429                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018035                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018035                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016567                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016567                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019107                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019107                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15421.265882                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15421.265882                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66558.035269                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66558.035269                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14191.383042                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14191.383042                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14993.908930                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14993.908930                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54600                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54600                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513                       # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6386936500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6386936500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19975151483                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19975151483                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1701142500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1701142500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126808000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126808000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       298000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       298000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26362087983                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26362087983                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28063230483                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28063230483                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277199000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277199000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075698951                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075698951                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11352897951                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11352897951                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017210                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017210                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015648                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015648                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228392                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228392                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017904                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017904                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000015                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016517                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016517                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019058                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019058                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15459.459361                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15459.459361                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66666.504743                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66666.504743                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14218.368660                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14218.368660                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15108.781127                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15108.781127                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36985.458098                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36985.458098                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33713.109338                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33713.109338                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201651.161297                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201651.161297                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.137067                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.137067                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193359.300184                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193359.300184                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1889050                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.157898                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64290369                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1889562                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             34.023953                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       16212707500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.157898                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.998355                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.998355                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1886833                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.154154                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64237730                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1887345                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             34.036029                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       16318088500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.154154                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          197                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68161321                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68161321                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64290369                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64290369                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64290369                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64290369                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64290369                       # number of overall hits
-system.cpu.icache.overall_hits::total        64290369                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1981370                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1981370                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1981370                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1981370                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1981370                       # number of overall misses
-system.cpu.icache.overall_misses::total       1981370                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28130756994                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28130756994                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28130756994                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28130756994                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28130756994                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28130756994                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66271739                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66271739                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66271739                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66271739                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66271739                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66271739                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029898                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029898                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029898                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029898                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029898                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029898                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14197.629415                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14197.629415                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14197.629415                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14197.629415                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14197.629415                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14197.629415                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4834                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68104377                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68104377                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64237730                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64237730                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64237730                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64237730                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total        64237730                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1979279                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1979279                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1979279                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1979279                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1979279                       # number of overall misses
+system.cpu.icache.overall_misses::total       1979279                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  28148050491                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  28148050491                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  28148050491                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  28148050491                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  28148050491                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  28148050491                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66217009                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66217009                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66217009                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66217009                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66217009                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66217009                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029891                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029891                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029891                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029891                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029891                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029891                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14221.365705                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14221.365705                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14221.365705                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14221.365705                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14221.365705                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14221.365705                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         4340                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               167                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               160                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    28.946108                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    27.125000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91786                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91786                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91786                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91786                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        91786                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        91786                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1889584                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1889584                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1889584                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1889584                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1889584                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1889584                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1886833                       # number of writebacks
+system.cpu.icache.writebacks::total           1886833                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91909                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        91909                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        91909                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91909                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        91909                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        91909                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887370                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1887370                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1887370                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1887370                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1887370                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1887370                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25162612496                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25162612496                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25162612496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25162612496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25162612496                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25162612496                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377653500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377653500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377653500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    377653500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028513                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028513                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028513                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028513                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028513                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028513                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13316.482621                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13316.482621                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13316.482621                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13316.482621                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13316.482621                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13316.482621                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125716.877497                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125716.877497                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125716.877497                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125716.877497                       # average overall mshr uncacheable latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13343.019118                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average ReadReq mshr uncacheable latency
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+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96843                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65028.531062                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5011588                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           162159                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.905395                       # Average number of references to valid blocks.
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+system.cpu.l2cache.tags.tagsinuse        65023.762629                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4997690                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           161869                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            30.874905                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49578.198261                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    11.786082                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     3.639229                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10379.582130                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5055.325361                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.756503                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000180                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000056                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.158380                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.077138                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996399                       # Percentage of cache occupancy per task id
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-system.cpu.l2cache.Writeback_hits::writebacks       698262                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       698262                       # number of Writeback hits
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-system.cpu.l2cache.UpgradeReq_hits::total           35                       # number of UpgradeReq hits
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-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2716                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2716                       # number of UpgradeReq misses
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+system.cpu.l2cache.tags.occ_blocks::cpu.data  5143.256214                       # Average occupied blocks per requestor
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+system.cpu.l2cache.WritebackDirty_hits::writebacks       695593                       # number of WritebackDirty hits
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+system.cpu.l2cache.WritebackClean_hits::writebacks      1846839                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1846839                       # number of WritebackClean hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.ReadExReq_misses::total       135463                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19932                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        19932                       # number of ReadCleanReq misses
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       928500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2641157500                       # number of overall miss cycles
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-system.cpu.l2cache.overall_miss_latency::total  22044321500                       # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::total        68793                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       698262                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       698262                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2751                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2751                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       297333                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       297333                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1889536                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1889536                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       543249                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       543249                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        56150                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        12643                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1889536                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       840582                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2798911                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        56150                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        12643                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1889536                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       840582                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2798911                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000445                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000554                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000465                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.987277                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.987277                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.455594                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.455594                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010549                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010549                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024672                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024672                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000445                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000554                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010549                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.177099                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.060320                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000445                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000554                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010549                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.177099                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.060320                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker       139420                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132642.857143                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 137937.500000                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1040.132548                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1040.132548                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  17607551500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  17607551500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2626802500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2626802500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1813838000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1813838000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2920500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker      1140500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2626802500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  19421389500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  22052253000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2920500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker      1140500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2626802500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  19421389500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  22052253000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        54138                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        11855                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        65993                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       695593                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       695593                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1846839                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1846839                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            7                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            7                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       297002                       # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1887324                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1887324                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       541048                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       541048                       # number of ReadSharedReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        54138                       # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000388                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000675                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000439                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988026                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988026                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.428571                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.428571                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.456330                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.456330                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010514                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010514                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024859                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024859                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000388                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000675                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010514                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.177771                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.060491                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000388                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000675                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010514                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.177771                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060491                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 142562.500000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 140034.482759                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   830.150569                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   830.150569                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        54000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        54000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129877.497915                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129877.497915                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132508.403572                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132508.403572                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134682.869507                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134682.869507                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker       139420                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132642.857143                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132508.403572                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130310.144694                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 130571.115915                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker       139420                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132642.857143                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132508.403572                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130310.144694                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 130571.115915                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129915.307199                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129915.307199                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132379.302525                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132379.302525                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134857.843866                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134857.843866                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 142562.500000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132379.302525                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130361.519254                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 130600.303222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 142562.500000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132379.302525                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130361.519254                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 130600.303222                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1305,8 +1318,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        89227                       # number of writebacks
-system.cpu.l2cache.writebacks::total            89227                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        88877                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88877                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
@@ -1317,29 +1330,29 @@ system.cpu.l2cache.demand_mshr_hits::total          138                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           26                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total          138                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           25                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total           32                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2716                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2716                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           21                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            8                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total           29                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2723                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2723                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135463                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       135463                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19906                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19906                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13291                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13291                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           25                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19906                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       148754                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168692                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           25                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19906                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       148754                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168692                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135531                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       135531                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19817                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19817                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13338                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13338                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           21                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            8                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        19817                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       148869                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168715                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           21                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            8                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19817                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       148869                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168715                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34133                       # number of ReadReq MSHR uncacheable
@@ -1348,148 +1361,149 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27585
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61718                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3235500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       858500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      4094000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    192221500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    192221500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       213500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       213500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16238965500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16238965500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2439385500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2439385500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1658508500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1658508500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3235500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       858500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2439385500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17897474000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20340953500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3235500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       858500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2439385500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17897474000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20340953500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340103000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5546780500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5886883500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4471146500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4471146500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340103000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10017927000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10358030000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000445                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000554                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000465                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.987277                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.987277                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455594                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455594                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010535                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010535                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024466                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024466                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000445                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000554                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010535                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.176965                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060271                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000445                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000554                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010535                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.176965                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060271                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker       129420                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122642.857143                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127937.500000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70773.748159                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70773.748159                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71166.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119877.497915                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119877.497915                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       129420                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       129420                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172468.974306                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162086.151894                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162086.151894                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113216.711052                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170622.458017                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167828.348294                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker      1060500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3771000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    192695000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    192695000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16252241500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16252241500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2425990000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2425990000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1667259500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1667259500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker      1060500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2425990000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17919501000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20349262000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker      1060500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2425990000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17919501000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20349262000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340117000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888077000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6228194000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756881000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756881000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340117000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644958000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10985075000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000439                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988026                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988026                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.456330                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.456330                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010500                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024652                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024652                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177637                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060442                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177637                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060442                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130034.482759                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70765.699596                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70765.699596                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119915.307199                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119915.307199                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122419.639703                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125000.712251                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125000.712251                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120370.936864                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120613.235338                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120370.936864                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120613.235338                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189150.856115                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182468.403012                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172444.480696                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172444.480696                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181301.870082                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177988.188211                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5492109                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2761974                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        46577                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          382                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          382                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5484076                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758688                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        47112                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          381                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          381                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         127618                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2560581                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         127589                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2556141                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       823684                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1992109                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2751                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2756                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297333                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297333                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1889584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       543472                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5634635                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2637259                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        32087                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       130191                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8434172                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    120978240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98677545                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        50572                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       224600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          219930957                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      194580                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5786927                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.021369                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.144611                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty       820637                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1846839                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       142823                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2757                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2763                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       297002                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       297002                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887370                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       541297                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq        36194                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5627539                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2629603                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31270                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128179                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8416591                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    239034368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98344937                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        47420                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       216552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          337643277                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      197136                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3052848                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025905                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.158851                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5663267     97.86%     97.86% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             123660      2.14%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2973765     97.41%     97.41% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              79083      2.59%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5786927                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3520664000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       259127                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3052848                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5400072997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy       264877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2838013223                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2834880345                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1307328687                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1303595064                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19448990                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19421986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74088903                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74092896                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1514,9 +1528,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
@@ -1539,207 +1553,209 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             43091000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                99500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                29000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                91000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               647500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6192000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              167000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            33054500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              126000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186319025                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           186395016                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36413                       # number of replacements
-system.iocache.tags.tagsinuse                1.005013                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256397447000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005013                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062813                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062813                       # Average percentage of cache occupancy
+system.iocache.tags.replacements                36409                       # number of replacements
+system.iocache.tags.tagsinuse                1.005392                       # Cycle average of tags in use
+system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         256608771000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.005392                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062837                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062837                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
-system.iocache.tags.data_accesses              328023                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          223                       # number of overall misses
-system.iocache.overall_misses::total              223                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28159877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28159877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4697532148                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4697532148                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28159877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28159877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28159877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28159877                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
+system.iocache.tags.tag_accesses               328227                       # Number of tag accesses
+system.iocache.tags.data_accesses              328227                       # Number of data accesses
+system.iocache.WriteLineReq_hits::realview.ide           29                       # number of WriteLineReq hits
+system.iocache.WriteLineReq_hits::total            29                       # number of WriteLineReq hits
+system.iocache.ReadReq_misses::realview.ide          249                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              249                       # number of ReadReq misses
+system.iocache.WriteLineReq_misses::realview.ide        36195                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total        36195                       # number of WriteLineReq misses
+system.iocache.demand_misses::realview.ide          249                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          249                       # number of overall misses
+system.iocache.overall_misses::total              249                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     31311876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31311876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4715518140                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4715518140                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31311876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31311876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31311876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31311876                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          249                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             249                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          249                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            249                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide     0.999199                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total     0.999199                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126277.475336                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 126277.475336                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126277.475336                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126277.475336                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126277.475336                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.506024                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125750.506024                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130280.926647                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130280.926647                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125750.506024                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125750.506024                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125750.506024                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125750.506024                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           725                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   77                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.415584                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36190                       # number of writebacks
-system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          223                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17009877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17009877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2886332148                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2886332148                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17009877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17009877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17009877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17009877                       # number of overall MSHR miss cycles
+system.iocache.writebacks::writebacks           36160                       # number of writebacks
+system.iocache.writebacks::total                36160                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          249                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          249                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        36195                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        36195                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide          249                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18861876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18861876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2905768140                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2905768140                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18861876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18861876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18861876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18861876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.999199                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76277.475336                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76277.475336                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.506024                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.506024                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.926647                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.926647                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.506024                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75750.506024                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.506024                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75750.506024                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               34133                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67584                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67565                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::Writeback            125417                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7628                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4571                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       125037                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7766                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4596                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4574                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133608                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133608                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33452                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4599                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133659                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133659                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33433                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp        36194                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455251                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562821                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108888                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108888                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 671709                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455099                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562669                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108826                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108826                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 671495                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16438044                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16601449                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18918569                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              487                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402837                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16416028                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16579433                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18894633                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              513                       # Total snoops (count)
+system.membus.snoop_fanout::samples            402650                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402837    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402650    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402837                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83606500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402650                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83677500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1745500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1748500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           875905157                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           874312374                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          988369672                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          988164899                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64470242                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64093300                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index d7415aa23..8c271cc38 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -1,164 +1,160 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.824718                       # Number of seconds simulated
-sim_ticks                                2824717821500                       # Number of ticks simulated
-final_tick                               2824717821500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.824799                       # Number of seconds simulated
+sim_ticks                                2824799320500                       # Number of ticks simulated
+final_tick                               2824799320500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 249146                       # Simulator instruction rate (inst/s)
-host_op_rate                                   302232                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5724351305                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 631692                       # Number of bytes of host memory used
-host_seconds                                   493.46                       # Real time elapsed on the host
-sim_insts                                   122942928                       # Number of instructions simulated
-sim_ops                                     149138280                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 251577                       # Simulator instruction rate (inst/s)
+host_op_rate                                   305184                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5777436345                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 631984                       # Number of bytes of host memory used
+host_seconds                                   488.94                       # Real time elapsed on the host
+sim_insts                                   123005008                       # Number of instructions simulated
+sim_ops                                     149215388                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           536420                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4179876                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           121792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           910464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         1984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           318592                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          1655680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker         4032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst           408768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data          3010752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           540900                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4166756                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           103808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           925440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           328256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          1677824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker         4416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst           415296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data          3014912                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11149640                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       536420                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       121792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       318592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst       408768                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1385572                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8394624                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11180680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       540900                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       103808                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       328256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst       415296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1388260                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8418624                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8412148                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8436148                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            3                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             16835                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             65830                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1903                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             14226                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           31                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4978                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             25870                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker           63                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst              6387                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data             47043                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             16905                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             65625                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1622                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             14460                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           29                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5129                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             26216                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker           69                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst              6489                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data             47108                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                183186                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131166                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                183671                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131541                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               135547                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               135922                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            68                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              189902                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1479750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               43117                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              322320                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              112787                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              586140                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1427                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst              144711                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             1065859                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              191483                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1475063                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               36749                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              327613                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           657                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              116205                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              593962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst              147018                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             1067301                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3947169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         189902                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          43117                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         112787                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst         144711                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             490517                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2971845                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3958044                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         191483                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          36749                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         116205                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst         147018                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             491454                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2980256                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2978049                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2971845                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2986459                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2980256                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             189902                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1485954                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              43117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             322320                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          702                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             112787                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             586140                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1427                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst             144711                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            1065859                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             191483                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1481266                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              36749                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             327613                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          657                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             116205                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             593962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1563                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst             147018                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            1067301                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6925218                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        100502                       # Number of read requests accepted
-system.physmem.writeReqs                        68912                       # Number of write requests accepted
-system.physmem.readBursts                      100502                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      68912                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6426176                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5952                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4409728                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6432128                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4410368                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       93                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6944503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        101122                       # Number of read requests accepted
+system.physmem.writeReqs                        69399                       # Number of write requests accepted
+system.physmem.readBursts                      101122                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      69399                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  6464000                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7808                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4440192                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   6471808                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4441536                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      122                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          17980                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6920                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                6286                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                6764                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6403                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                6105                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5950                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                6704                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6701                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6487                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6589                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               6182                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5526                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5641                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6650                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6151                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               5350                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4550                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4246                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4783                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4329                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4133                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4124                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4743                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4271                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4451                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4796                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4218                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               3947                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               3851                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4779                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4130                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               3551                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          22992                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                7206                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                6389                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                6982                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                6703                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                6109                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                6146                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                6610                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6743                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6516                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6576                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               6052                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5500                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5540                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6495                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6075                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               5358                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4814                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4268                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4976                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4599                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4151                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4285                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4619                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4309                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4473                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4780                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4110                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               3894                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3790                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4672                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               4032                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               3606                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2823151552500                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2823233051500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  100502                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  101122                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  68912                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     76732                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     21067                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2057                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  69399                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     77320                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     20991                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       572                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,170 +182,170 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4087                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4893                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3651                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                        73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1494                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3943                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4040                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5011                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     3894                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     3804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     3619                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       86                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39319                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      275.584628                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.263333                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     308.433492                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16168     41.12%     41.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9688     24.64%     65.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3830      9.74%     75.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2076      5.28%     80.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1590      4.04%     84.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          981      2.49%     87.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          594      1.51%     88.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          552      1.40%     90.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3840      9.77%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39319                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3599                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.894137                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      471.050714                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           3597     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::36                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       32                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        39537                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      275.792296                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     163.681718                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     307.680924                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16252     41.11%     41.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9627     24.35%     65.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3980     10.07%     75.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2061      5.21%     80.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1623      4.11%     84.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1029      2.60%     87.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          580      1.47%     88.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          548      1.39%     90.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3837      9.70%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          39537                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3613                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.947135                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      470.013093                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           3611     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.03%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3599                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3599                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.144762                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.954400                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       10.164866                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                 6      0.17%      0.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 2      0.06%      0.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                1      0.03%      0.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               5      0.14%      0.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3182     88.41%     88.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              82      2.28%     91.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              48      1.33%     92.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              63      1.75%     94.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              10      0.28%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              54      1.50%     95.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              28      0.78%     96.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               5      0.14%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               9      0.25%     97.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              17      0.47%     97.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.11%     97.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               3      0.08%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67              52      1.44%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.14%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               2      0.06%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              13      0.36%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.03%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.06%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             3      0.08%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3599                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1312823000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                3195491750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    502045000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13074.75                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            3613                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3613                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.202325                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.997759                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       10.552053                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                 4      0.11%      0.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 2      0.06%      0.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                2      0.06%      0.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               5      0.14%      0.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3178     87.96%     88.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             101      2.80%     91.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              43      1.19%     92.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31              66      1.83%     94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              15      0.42%     94.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              55      1.52%     96.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              32      0.89%     96.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.17%     97.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               5      0.14%     97.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              12      0.33%     97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.06%     97.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               3      0.08%     97.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67              56      1.55%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               2      0.06%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               1      0.03%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              11      0.30%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.03%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.03%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             8      0.22%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3613                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1315778000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                3209528000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    505000000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13027.50                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31824.75                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.27                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31777.50                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.57                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.91                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      80981                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     49010                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.65                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.12                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16664216.37                       # Average gap between requests
-system.physmem.pageHitRate                      76.77                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  156287880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   85152375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 404274000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                227959920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           179773417200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            73215548100                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1622782125750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1876644765225                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.446746                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2640312790250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     91908700000                       # Time in different power states
+system.physmem.avgWrQLen                        30.16                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      81477                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     49363                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.13                       # Row buffer hit rate for writes
+system.physmem.avgGap                     16556512.40                       # Average gap between requests
+system.physmem.pageHitRate                      76.78                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  159508440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   86917875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 412503000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                233416080                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           179779011360                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            73304297100                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1624538062500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1878513716355                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.386003                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2640260933000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     91911560000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     20242228250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     20369491500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  140963760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   76741500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 378892800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                218525040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           179773417200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            72451612440                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1618075692000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1871115844740                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.608024                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2641479820250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     91908700000                       # Time in different power states
+system.physmem_1.actEnergy                  139391280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   75900000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 375273600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                216153360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           179779011360                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            72455887440                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1616321661750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1869363278790                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.677649                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2641542244250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     91911560000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     19062807500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     19077733750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -399,47 +395,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     4993                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                4993                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples         4993                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           4993    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         4993                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples  57346094376                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.255415                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -14647046374    -25.54%    -25.54% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    71993140750    125.54%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  57346094376                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         2743     66.90%     66.90% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1357     33.10%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         4100                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         4993                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                     4963                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                4963                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         4963                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           4963    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         4963                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples  53087691330                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.356118                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -18905470420    -35.61%    -35.61% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    71993161750    135.61%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  53087691330                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         2701     66.40%     66.40% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1367     33.60%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         4068                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         4963                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         4993                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4100                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         4963                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4068                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4100                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total         9093                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4068                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total         9031                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12030030                       # DTB read hits
-system.cpu0.dtb.read_misses                      4190                       # DTB read misses
-system.cpu0.dtb.write_hits                    9398007                       # DTB write hits
-system.cpu0.dtb.write_misses                      803                       # DTB write misses
+system.cpu0.dtb.read_hits                    11938297                       # DTB read hits
+system.cpu0.dtb.read_misses                      4171                       # DTB read misses
+system.cpu0.dtb.write_hits                    9295240                       # DTB write hits
+system.cpu0.dtb.write_misses                      792                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         171                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     352                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     345                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2915                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    2875                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   721                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   692                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      173                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12034220                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9398810                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      167                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                11942468                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9296032                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         21428037                       # DTB hits
-system.cpu0.dtb.misses                           4993                       # DTB misses
-system.cpu0.dtb.accesses                     21433030                       # DTB accesses
+system.cpu0.dtb.hits                         21233537                       # DTB hits
+system.cpu0.dtb.misses                           4963                       # DTB misses
+system.cpu0.dtb.accesses                     21238500                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -469,648 +465,650 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     2307                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                2307                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples         2307                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           2307    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         2307                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples  57346094376                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.255417                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -14647174874    -25.54%    -25.54% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    71993269250    125.54%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  57346094376                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1275     74.08%     74.08% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          446     25.92%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         1721                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                     2305                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                2305                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         2305                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           2305    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         2305                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples  53087691330                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.356120                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -18905570920    -35.61%    -35.61% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    71993262250    135.61%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  53087691330                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1266     73.91%     73.91% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          447     26.09%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         1713                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2307                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2307                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2305                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2305                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1721                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1721                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         4028                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    57257258                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2307                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1713                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1713                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         4018                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    57022290                       # ITB inst hits
+system.cpu0.itb.inst_misses                      2305                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         171                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     352                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     345                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1727                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1719                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                57259565                       # ITB inst accesses
-system.cpu0.itb.hits                         57257258                       # DTB hits
-system.cpu0.itb.misses                           2307                       # DTB misses
-system.cpu0.itb.accesses                     57259565                       # DTB accesses
-system.cpu0.numCycles                        69320920                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                57024595                       # ITB inst accesses
+system.cpu0.itb.hits                         57022290                       # DTB hits
+system.cpu0.itb.misses                           2305                       # DTB misses
+system.cpu0.itb.accesses                     57024595                       # DTB accesses
+system.cpu0.numCycles                        68977361                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   55846469                       # Number of instructions committed
-system.cpu0.committedOps                     67799019                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             59476753                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4636                       # Number of float alu accesses
-system.cpu0.num_func_calls                    5739649                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7404981                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    59476753                       # number of integer instructions
-system.cpu0.num_fp_insts                         4636                       # number of float instructions
-system.cpu0.num_int_register_reads          109855675                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          41239490                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3530                       # number of times the floating registers were read
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                    3088                       # number of quiesce instructions executed
+system.cpu0.committedInsts                   55612915                       # Number of instructions committed
+system.cpu0.committedOps                     67456889                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             59167201                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4525                       # Number of float alu accesses
+system.cpu0.num_func_calls                    5730859                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7383240                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    59167201                       # number of integer instructions
+system.cpu0.num_fp_insts                         4525                       # number of float instructions
+system.cpu0.num_int_register_reads          109233677                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          41018104                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3419                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1108                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           206363052                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           25211275                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     21994746                       # number of memory refs
-system.cpu0.num_load_insts                   12174830                       # Number of load instructions
-system.cpu0.num_store_insts                   9819916                       # Number of store instructions
-system.cpu0.num_idle_cycles              65448484.972740                       # Number of idle cycles
-system.cpu0.num_busy_cycles              3872435.027260                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.055862                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.944138                       # Percentage of idle cycles
-system.cpu0.Branches                         13529823                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                 2175      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 46835768     67.99%     67.99% # Class of executed instruction
-system.cpu0.op_class::IntMult                   49875      0.07%     68.07% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              3855      0.01%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.07% # Class of executed instruction
-system.cpu0.op_class::MemRead                12174830     17.67%     85.74% # Class of executed instruction
-system.cpu0.op_class::MemWrite                9819916     14.26%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads           205348706                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           25186036                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     21795373                       # number of memory refs
+system.cpu0.num_load_insts                   12079832                       # Number of load instructions
+system.cpu0.num_store_insts                   9715541                       # Number of store instructions
+system.cpu0.num_idle_cycles              65194671.854537                       # Number of idle cycles
+system.cpu0.num_busy_cycles              3782689.145463                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.054840                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.945160                       # Percentage of idle cycles
+system.cpu0.Branches                         13504260                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                 2176      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 46697221     68.12%     68.13% # Class of executed instruction
+system.cpu0.op_class::IntMult                   49891      0.07%     68.20% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              3798      0.01%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.20% # Class of executed instruction
+system.cpu0.op_class::MemRead                12079832     17.62%     85.83% # Class of executed instruction
+system.cpu0.op_class::MemWrite                9715541     14.17%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  68886419                       # Class of executed instruction
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3088                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements           833472                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.996601                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           46054787                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           833984                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            55.222627                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  68548459                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           833427                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.996688                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           46067752                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           833939                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            55.241153                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   479.685791                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.479753                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.026378                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data    14.804679                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.936886                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.022421                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.011770                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.028915                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   476.386497                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data    11.984373                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.249015                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data    17.376803                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.930442                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.023407                       # Average percentage of cache occupancy
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 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
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 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        193142781                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       193142781                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11422254                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      3666502                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4281798                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data      6456449                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25827003                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      9049094                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      2626435                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      3309918                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data      3942780                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18928227                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       169795                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        55205                       # number of SoftPFReq hits
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-system.cpu0.dcache.SoftPFReq_hits::total       386107                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       210372                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        75336                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        77039                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data        87626                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       450373                       # number of LoadLockedReq hits
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-system.cpu0.dcache.StoreCondReq_hits::cpu3.data        91425                       # number of StoreCondReq hits
+system.cpu0.dcache.tags.tag_accesses        193252454                       # Number of tag accesses
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 system.cpu0.dcache.StoreCondReq_hits::total       460083                       # number of StoreCondReq hits
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-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3575                       # number of LoadLockedReq misses
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-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   1024208500                       # number of ReadReq miss cycles
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-system.cpu0.dcache.LoadLockedReq_miss_latency::total    198180500                       # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.overall_miss_latency::total  92408954451                       # number of overall miss cycles
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13923.356643                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14432.795699                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11038.236605                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 34739.130435                       # average StoreCondReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 49443.204921                       # average overall miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 61021.296059                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 46033.623432                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       512704                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        36990                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            12419                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            546                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    41.283839                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    67.747253                       # average number of cycles each access was blocked
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+system.cpu0.dcache.overall_hits::total       45154317                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       159917                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        57186                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data        95818                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu3.data       208300                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       521221                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       127063                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        30733                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data        96540                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data      1107405                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1361741                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        49178                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        18079                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data        32233                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu3.data        39331                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       138821                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         3393                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2705                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3823                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data         8106                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        18027                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu3.data           29                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           29                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       286980                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data        87919                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       192358                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data      1315705                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1882962                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       336158                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       105998                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data       224591                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data      1355036                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2021783                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   1032258500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   1431084000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data   3747083500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6210426000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1867667000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6551048997                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  78333004406                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  86751720403                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     38521500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     54466000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data    117948000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    210935500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data      1108500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      1108500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   2899925500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data   7982132997                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data  82080087906                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  92962146403                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   2899925500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data   7982132997                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data  82080087906                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  92962146403                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     11500789                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      3722272                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4442968                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data      6700394                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26366423                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9078832                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      2658656                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      3453800                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data      5093633                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     20284921                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       217841                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        72816                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       107065                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       127034                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       524756                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       210035                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        77860                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        82637                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data        97879                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       468411                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       207452                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        77217                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        81680                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data        93763                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460112                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     20579621                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      6380928                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7896768                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     11794027                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     46651344                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     20797462                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      6453744                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      8003833                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     11921061                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     47176100                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013905                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.015363                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.021566                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.031088                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.019768                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013996                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.011560                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.027952                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.217410                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.067131                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.225752                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.248283                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.301060                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.309610                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.264544                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.016154                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.034742                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.046263                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.082817                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.038485                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000309                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000063                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013945                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.013778                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.024359                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.111557                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.040362                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.016163                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.016424                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.028060                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.113667                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.042856                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18050.895324                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14935.440105                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17988.879021                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11915.149236                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60770.735041                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67858.390273                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70735.642702                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 63706.476050                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14240.850277                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14246.926498                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14550.703183                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11701.087258                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 38224.137931                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 38224.137931                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32984.059191                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41496.236169                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62384.871917                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 49370.165942                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27358.303930                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35540.751842                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 60574.101283                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 45980.278993                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       506256                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        34118                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            12382                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            560                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.886448                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    60.925000                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       692075                       # number of writebacks
-system.cpu0.dcache.writebacks::total           692075                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           65                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        15172                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data        93547                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       108784                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        43736                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1006705                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1050441                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1618                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2327                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5382                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9327                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data           65                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data        58908                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      1100252                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1159225                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data           65                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data        58908                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      1100252                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1159225                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        56510                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        79447                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       111104                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       247061                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        30419                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        52213                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        88157                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       170789                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        17367                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        21997                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        28240                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total        67604                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1022                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1248                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         2430                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4700                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           23                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           23                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        86929                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       131660                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data       199261                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       417850                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       104296                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       153657                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data       227501                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       485454                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3591                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         5668                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         8430                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17689                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2928                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4375                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6667                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        13970                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         6519                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        10043                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        15097                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31659                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    966240500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1154098000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1729828000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3850166500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1810886000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3506727500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   6410528421                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11728141921                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    228034000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    306929500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    499195000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1034158500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     15604000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     21310500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     39501500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     76416000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       776000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       776000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2777126500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   4660825500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   8140356421                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  15578308421                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3005160500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   4967755000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   8639551421                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16612466921                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    597998000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1071505000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1718751500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3388254500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    486771500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    812532000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1333957452                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2633260952                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1084769500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1884037000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   3052708952                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6021515452                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015178                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018153                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016680                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009377                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011449                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015330                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017500                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008422                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.238417                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.207372                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.225980                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.128883                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.013107                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.015481                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.025462                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.010036                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000252                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000050                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013625                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.016918                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.017033                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.008962                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.016163                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019479                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019241                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.010296                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17098.575473                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14526.640402                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15569.448445                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15583.869975                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59531.411289                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 67161.961580                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72717.179816                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68670.358870                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13130.304601                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13953.243624                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17676.876771                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15297.297497                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15268.101761                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17075.721154                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16255.761317                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16258.723404                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 33739.130435                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33739.130435                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31947.065996                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35400.467112                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40852.732953                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37282.059162                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28813.765629                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32330.157429                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37975.883275                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34220.475928                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166526.872737                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 189044.636556                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203885.112693                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191545.847702                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166247.096995                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185721.600000                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200083.613619                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188493.983679                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166401.211842                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 187597.032759                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 202206.329204                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190199.167756                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks       692230                       # number of writebacks
+system.cpu0.dcache.writebacks::total           692230                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           73                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        15389                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data        95422                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       110884                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        43862                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      1018548                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1062410                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1613                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2364                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data         5475                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         9452                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data           73                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data        59251                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      1113970                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1173294                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data           73                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data        59251                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      1113970                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1173294                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        57113                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data        80429                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data       112878                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       250420                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        30733                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        52678                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data        88857                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       172268                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        17812                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        22623                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data        28947                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total        69382                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1092                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         1459                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data         2631                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5182                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data           29                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           29                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        87846                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       133107                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data       201735                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       422688                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       105658                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       155730                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data       230682                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       492070                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         3488                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         5443                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         8526                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17457                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2835                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4201                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6746                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        13782                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         6323                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         9644                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        15272                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31239                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    973626500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1170429000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data   1752405000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3896460500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1836934000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3551134500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data   6426494942                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11814563442                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    237039500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    314888500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data    508808000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1060736000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     18701500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     25087500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data     42425000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     86214000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data      1079500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1079500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2810560500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   4721563500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data   8178899942                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  15711023942                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3047600000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   5036452000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data   8687707942                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16771759942                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    617743500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1078938000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1840814500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3537496000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    506139500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    824481000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1437530452                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2768150952                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1123883000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1903419000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   3278344952                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6305646952                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.015344                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018103                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.016846                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.009498                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011560                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015252                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.017445                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008492                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.244617                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.211302                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.227868                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.132218                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.014025                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.017656                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.026880                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.011063                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000309                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000063                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.013767                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.016856                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.017105                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.009061                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.016372                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.019457                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.019351                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.010430                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17047.371001                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14552.325654                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15524.770106                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15559.701701                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59770.735041                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 67412.098030                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72324.014338                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68582.461293                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13307.854256                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13918.954162                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17577.227347                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15288.345680                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17125.915751                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17194.996573                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16125.047510                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16637.205712                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 37224.137931                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 37224.137931                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31994.177310                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35471.939868                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40542.790998                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37169.316238                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28844.006133                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32340.923393                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37660.970262                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34084.093609                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177105.361239                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198224.875988                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215905.993432                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202640.545340                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178532.451499                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196258.271840                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213093.752149                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200852.630387                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 177745.215879                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197368.208212                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214663.760608                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201851.754282                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1975887                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.441259                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           94009429                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1976399                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            47.566017                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      12738207000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   433.789749                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    10.948279                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    27.353975                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst    39.349255                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.847246                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.021383                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.053426                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.076854                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998909                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1980846                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.437171                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           93844389                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1981358                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            47.363671                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      12780860000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   431.192789                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    10.885225                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    29.403855                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst    39.955303                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.842173                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.021260                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.057429                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.078038                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998901                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          175                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          173                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         98005721                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        98005721                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     56526239                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     17926561                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     10330491                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst      9226138                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       94009429                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     56526239                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     17926561                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     10330491                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst      9226138                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        94009429                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     56526239                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     17926561                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     10330491                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst      9226138                       # number of overall hits
-system.cpu0.icache.overall_hits::total       94009429                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       732740                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       203961                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       495572                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst       587581                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2019854                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       732740                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       203961                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       495572                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst       587581                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2019854                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       732740                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       203961                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       495572                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst       587581                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2019854                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2885533500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   7058023000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   8404858487                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  18348414987                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2885533500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   7058023000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst   8404858487                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  18348414987                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2885533500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   7058023000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst   8404858487                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  18348414987                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     57258979                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     18130522                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     10826063                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst      9813719                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     96029283                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     57258979                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     18130522                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     10826063                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst      9813719                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     96029283                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     57258979                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     18130522                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     10826063                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst      9813719                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     96029283                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012797                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011250                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.045776                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.059873                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.021034                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012797                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011250                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.045776                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.059873                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.021034                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012797                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011250                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.045776                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst     0.059873                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.021034                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14147.476723                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14242.174699                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14304.169956                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9084.030324                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14147.476723                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14242.174699                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14304.169956                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9084.030324                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14147.476723                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14242.174699                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14304.169956                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9084.030324                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         7750                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         97851139                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        97851139                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     56302251                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     17886257                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst     10425215                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst      9230666                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       93844389                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     56302251                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     17886257                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst     10425215                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu3.inst      9230666                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        93844389                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     56302251                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     17886257                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst     10425215                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu3.inst      9230666                       # number of overall hits
+system.cpu0.icache.overall_hits::total       93844389                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       721752                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       203984                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       502026                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst       597588                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2025350                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       721752                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       203984                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       502026                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu3.inst       597588                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2025350                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       721752                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       203984                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       502026                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu3.inst       597588                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2025350                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2853769000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   7161787500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst   8596388489                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  18611944989                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2853769000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   7161787500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst   8596388489                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  18611944989                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2853769000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   7161787500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst   8596388489                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  18611944989                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     57024003                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     18090241                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst     10927241                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu3.inst      9828254                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     95869739                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     57024003                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     18090241                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst     10927241                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst      9828254                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     95869739                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     57024003                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     18090241                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst     10927241                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst      9828254                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     95869739                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012657                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011276                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.045943                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.060803                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.021126                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012657                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011276                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.045943                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst     0.060803                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.021126                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012657                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011276                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.045943                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst     0.060803                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.021126                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13990.160993                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14265.770100                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14385.142421                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9189.495637                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13990.160993                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14265.770100                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14385.142421                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9189.495637                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13990.160993                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14265.770100                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14385.142421                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9189.495637                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         6745                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              322                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              318                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.068323                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    21.210692                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        43415                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        43415                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst        43415                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        43415                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst        43415                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        43415                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       203961                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       495572                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       544166                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1243699                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       203961                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       495572                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst       544166                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1243699                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       203961                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       495572                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst       544166                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1243699                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2681572500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6562452000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7336863488                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  16580887988                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2681572500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6562452000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7336863488                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  16580887988                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2681572500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6562452000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7336863488                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  16580887988                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011250                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.045776                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.055450                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012951                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011250                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.045776                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.055450                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.012951                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011250                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.045776                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.055450                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.012951                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13147.476723                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13242.176717                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13482.767185                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13331.913902                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13147.476723                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13242.176717                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13482.767185                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13331.913902                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13147.476723                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13242.176717                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13482.767185                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13331.913902                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks      1980846                       # number of writebacks
+system.cpu0.icache.writebacks::total          1980846                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst        43949                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        43949                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst        43949                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        43949                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst        43949                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        43949                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       203984                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       502026                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst       553639                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1259649                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       203984                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       502026                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst       553639                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1259649                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       203984                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       502026                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst       553639                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1259649                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2649785000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   6659762500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst   7509042490                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  16818589990                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2649785000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   6659762500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst   7509042490                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  16818589990                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2649785000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   6659762500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst   7509042490                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  16818589990                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011276                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.045943                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.056331                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013139                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011276                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.045943                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.056331                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.013139                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011276                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.045943                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.056331                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.013139                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12990.160993                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13265.772091                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13563.066348                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13351.806726                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12990.160993                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13265.772091                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13563.066348                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13351.806726                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12990.160993                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13265.772091                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13563.066348                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13351.806726                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1141,55 +1139,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     1988                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                1988                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          507                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1481                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         1988                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           1988    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         1988                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1694                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 13442.148760                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11640.659125                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7340.460279                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         1298     76.62%     76.62% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          395     23.32%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1694                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                     1928                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                1928                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          500                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1428                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         1928                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           1928    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         1928                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1628                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 13253.992629                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11553.834233                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  6560.213470                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-6143          361     22.17%     22.17% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::6144-8191           74      4.55%     26.72% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::10240-12287          476     29.24%     55.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-14335          145      8.91%     64.86% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::14336-16383          172     10.57%     75.43% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-18431           41      2.52%     77.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::22528-24575          347     21.31%     99.26% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-26623           12      0.74%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1628                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples   1000016000                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0     1000016000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total   1000016000                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1189     70.19%     70.19% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          505     29.81%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1694                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1988                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         1130     69.41%     69.41% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          498     30.59%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1628                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1928                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1988                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1694                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1928                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1628                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1694                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         3682                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1628                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         3556                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3877487                       # DTB read hits
-system.cpu1.dtb.read_misses                      1782                       # DTB read misses
-system.cpu1.dtb.write_hits                    2737174                       # DTB write hits
-system.cpu1.dtb.write_misses                      206                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         151                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     141                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                     3876436                       # DTB read hits
+system.cpu1.dtb.read_misses                      1705                       # DTB read misses
+system.cpu1.dtb.write_hits                    2738772                       # DTB write hits
+system.cpu1.dtb.write_misses                      223                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         150                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     142                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1170                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1110                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   242                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   221                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                       64                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3879269                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2737380                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3878141                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2738995                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6614661                       # DTB hits
-system.cpu1.dtb.misses                           1988                       # DTB misses
-system.cpu1.dtb.accesses                      6616649                       # DTB accesses
+system.cpu1.dtb.hits                          6615208                       # DTB hits
+system.cpu1.dtb.misses                           1928                       # DTB misses
+system.cpu1.dtb.accesses                      6617136                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1219,130 +1222,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     1030                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                1030                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          184                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2          846                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         1030                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           1030    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         1030                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples          746                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12997.319035                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11244.232149                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  6525.015841                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-6143          210     28.15%     28.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::6144-8191            1      0.13%     28.28% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287          183     24.53%     52.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335           68      9.12%     61.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::14336-16383          130     17.43%     79.36% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575          152     20.38%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-26623            2      0.27%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total          746                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                      970                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                 970                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          180                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2          790                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples          970                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0            970    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total          970                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          698                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12663.323782                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 10953.370627                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  6428.547911                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143          206     29.51%     29.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::6144-8191            1      0.14%     29.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287          176     25.21%     54.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335           64      9.17%     64.04% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383          123     17.62%     81.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575          124     17.77%     99.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-26623            4      0.57%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          698                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          562     75.34%     75.34% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          184     24.66%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          746                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K          518     74.21%     74.21% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          180     25.79%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          698                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1030                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1030                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          970                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total          970                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          746                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          746                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         1776                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    18130522                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1030                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          698                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          698                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         1668                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    18090241                       # ITB inst hits
+system.cpu1.itb.inst_misses                       970                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         151                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     141                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         150                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     142                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     779                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     729                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                18131552                       # ITB inst accesses
-system.cpu1.itb.hits                         18130522                       # DTB hits
-system.cpu1.itb.misses                           1030                       # DTB misses
-system.cpu1.itb.accesses                     18131552                       # DTB accesses
-system.cpu1.numCycles                       144010279                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                18091211                       # ITB inst accesses
+system.cpu1.itb.hits                         18090241                       # DTB hits
+system.cpu1.itb.misses                            970                       # DTB misses
+system.cpu1.itb.accesses                     18091211                       # DTB accesses
+system.cpu1.numCycles                       144011692                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   17464166                       # Number of instructions committed
-system.cpu1.committedOps                     20951836                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             18623353                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  1244                       # Number of float alu accesses
-system.cpu1.num_func_calls                    2002453                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2238605                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    18623353                       # number of integer instructions
-system.cpu1.num_fp_insts                         1244                       # number of float instructions
-system.cpu1.num_int_register_reads           34462753                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          13064497                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                 984                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                260                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            76266638                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            7592351                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      6809095                       # number of memory refs
-system.cpu1.num_load_insts                    3920028                       # Number of load instructions
-system.cpu1.num_store_insts                   2889067                       # Number of store instructions
-system.cpu1.num_idle_cycles              136641410.332873                       # Number of idle cycles
-system.cpu1.num_busy_cycles              7368868.667127                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.051169                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.948831                       # Percentage of idle cycles
-system.cpu1.Branches                          4354761                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                   27      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 14731476     68.33%     68.33% # Class of executed instruction
-system.cpu1.op_class::IntMult                   16530      0.08%     68.41% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc               936      0.00%     68.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.42% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.42% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3920028     18.18%     86.60% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2889067     13.40%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  21558064                       # Class of executed instruction
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups                5764695                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          2966106                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           506808                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             3301109                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                2388086                       # Number of BTB hits
+system.cpu1.committedInsts                   17421387                       # Number of instructions committed
+system.cpu1.committedOps                     20908811                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             18586966                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  1243                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1994388                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2228706                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    18586966                       # number of integer instructions
+system.cpu1.num_fp_insts                         1243                       # number of float instructions
+system.cpu1.num_int_register_reads           34395717                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          13039867                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                1047                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes                196                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            76120282                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            7571334                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      6808450                       # number of memory refs
+system.cpu1.num_load_insts                    3918979                       # Number of load instructions
+system.cpu1.num_store_insts                   2889471                       # Number of store instructions
+system.cpu1.num_idle_cycles              136781206.784887                       # Number of idle cycles
+system.cpu1.num_busy_cycles              7230485.215113                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.050208                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.949792                       # Percentage of idle cycles
+system.cpu1.Branches                          4335876                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                   24      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 14685914     68.27%     68.27% # Class of executed instruction
+system.cpu1.op_class::IntMult                   16370      0.08%     68.35% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc               946      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.35% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3918979     18.22%     86.57% # Class of executed instruction
+system.cpu1.op_class::MemWrite                2889471     13.43%    100.00% # Class of executed instruction
+system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+system.cpu1.op_class::total                  21511704                       # Class of executed instruction
+system.cpu2.branchPred.lookups                5805237                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          2994100                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           512421                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             3358874                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                2415611                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            72.341931                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                1613052                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            330539                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            71.917285                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                1615920                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            333124                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1372,60 +1375,55 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                    12898                       # Table walker walks requested
-system.cpu2.dtb.walker.walksShort               12898                       # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         8122                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4776                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        12898                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          12898    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        12898                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples         2175                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 12233.103448                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 10576.406558                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev  6350.387588                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::2048-4095           16      0.74%      0.74% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::4096-6143          627     28.83%     29.56% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::6144-8191            3      0.14%     29.70% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::10240-12287          777     35.72%     65.43% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::12288-14335          187      8.60%     74.02% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::14336-16383          174      8.00%     82.02% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::22528-24575          386     17.75%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::24576-26623            5      0.23%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total         2175                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks                    12664                       # Table walker walks requested
+system.cpu2.dtb.walker.walksShort               12664                       # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1         8020                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2         4644                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        12664                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          12664    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        12664                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples         2157                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 12096.893834                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 10423.094509                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev  6904.169413                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-16383         1795     83.22%     83.22% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::16384-32767          361     16.74%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-147455            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total         2157                       # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walksPending::samples   2000052000                       # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::0     2000052000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::total   2000052000                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K         1361     62.57%     62.57% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M          814     37.43%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total         2175                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        12898                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K         1306     60.55%     60.55% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M          851     39.45%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total         2157                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        12664                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        12898                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2175                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        12664                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         2157                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2175                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total        15073                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         2157                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total        14821                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                     4607133                       # DTB read hits
-system.cpu2.dtb.read_misses                     11539                       # DTB read misses
-system.cpu2.dtb.write_hits                    3514721                       # DTB write hits
-system.cpu2.dtb.write_misses                     1359                       # DTB write misses
-system.cpu2.dtb.flush_tlb                         153                       # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva                     151                       # Number of times TLB was flushed by MVA
+system.cpu2.dtb.read_hits                     4677262                       # DTB read hits
+system.cpu2.dtb.read_misses                     11320                       # DTB read misses
+system.cpu2.dtb.write_hits                    3564595                       # DTB write hits
+system.cpu2.dtb.write_misses                     1344                       # DTB write misses
+system.cpu2.dtb.flush_tlb                         154                       # Number of times complete TLB was flushed
+system.cpu2.dtb.flush_tlb_mva                     157                       # Number of times TLB was flushed by MVA
 system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    1512                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      194                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   312                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries                    1473                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      212                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   332                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      112                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                 4618672                       # DTB read accesses
-system.cpu2.dtb.write_accesses                3516080                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      121                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                 4688582                       # DTB read accesses
+system.cpu2.dtb.write_accesses                3565939                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                          8121854                       # DTB hits
-system.cpu2.dtb.misses                          12898                       # DTB misses
-system.cpu2.dtb.accesses                      8134752                       # DTB accesses
+system.cpu2.dtb.hits                          8241857                       # DTB hits
+system.cpu2.dtb.misses                          12664                       # DTB misses
+system.cpu2.dtb.accesses                      8254521                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1455,81 +1453,81 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                     1355                       # Table walker walks requested
-system.cpu2.itb.walker.walksShort                1355                       # Table walker walks initiated with short descriptors
-system.cpu2.itb.walker.walksShortTerminationLevel::Level1          252                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1103                       # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples         1355                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0           1355    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total         1355                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples          885                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 12701.694915                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 10970.308006                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev  6476.484391                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::4096-6143          261     29.49%     29.49% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::10240-12287          244     27.57%     57.06% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::12288-14335           68      7.68%     64.75% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::14336-16383          134     15.14%     79.89% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::22528-24575          177     20.00%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::24576-26623            1      0.11%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total          885                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks                     1329                       # Table walker walks requested
+system.cpu2.itb.walker.walksShort                1329                       # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1          263                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2         1066                       # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples         1329                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0           1329    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total         1329                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples          852                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 12299.295775                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 10742.634902                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev  6145.721581                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::4096-6143          262     30.75%     30.75% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::10240-12287          255     29.93%     60.68% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::12288-14335           38      4.46%     65.14% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::14336-16383          163     19.13%     84.27% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::22528-24575          131     15.38%     99.65% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::24576-26623            3      0.35%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total          852                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000037500                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000037500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000037500                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K          640     72.32%     72.32% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M          245     27.68%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total          885                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K          589     69.13%     69.13% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M          263     30.87%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total          852                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1355                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1355                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         1329                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total         1329                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          885                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total          885                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total         2240                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    10827992                       # ITB inst hits
-system.cpu2.itb.inst_misses                      1355                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst          852                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total          852                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total         2181                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    10929097                       # ITB inst hits
+system.cpu2.itb.inst_misses                      1329                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                         153                       # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva                     151                       # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb                         154                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb_mva                     157                       # Number of times TLB was flushed by MVA
 system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                     895                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                     862                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                     1816                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                     1732                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                10829347                       # ITB inst accesses
-system.cpu2.itb.hits                         10827992                       # DTB hits
-system.cpu2.itb.misses                           1355                       # DTB misses
-system.cpu2.itb.accesses                     10829347                       # DTB accesses
-system.cpu2.numCycles                      1394813628                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                10930426                       # ITB inst accesses
+system.cpu2.itb.hits                         10929097                       # DTB hits
+system.cpu2.itb.misses                           1329                       # DTB misses
+system.cpu2.itb.accesses                     10930426                       # DTB accesses
+system.cpu2.numCycles                      1393382531                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                   20299204                       # Number of instructions committed
-system.cpu2.committedOps                     24561296                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                      1454329                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                      560                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                  4254632682                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                             68.712725                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.014553                       # IPC: instructions per cycle
+system.cpu2.committedInsts                   20580093                       # Number of instructions committed
+system.cpu2.committedOps                     24901206                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                      1467300                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                      567                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                  4256226860                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                             67.705356                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.014770                       # IPC: instructions per cycle
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                       42192180                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                     1352621448                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               13267477                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted          7218148                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect           306932                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups             7331192                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                6244117                       # Number of BTB hits
+system.cpu2.tickCycles                       42624758                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                     1350757773                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               13301320                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted          7249235                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect           312069                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups             8284814                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                6256612                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            85.171920                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                3106613                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect             16022                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct            75.519040                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                3109270                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect             16225                       # Number of incorrect RAS predictions.
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1559,89 +1557,88 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.walks                    32594                       # Table walker walks requested
-system.cpu3.dtb.walker.walksShort               32594                       # Table walker walks initiated with short descriptors
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11131                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         7720                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore        13743                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples        18851                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean   550.607395                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev  4115.669871                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-16383        18669     99.03%     99.03% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::16384-32767          132      0.70%     99.73% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::32768-49151           28      0.15%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::49152-65535           10      0.05%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-81919            5      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::81920-98303            1      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::98304-114687            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::114688-131071            2      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-147455            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walks                    33037                       # Table walker walks requested
+system.cpu3.dtb.walker.walksShort               33037                       # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1        11464                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level2         7705                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore        13868                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples        19169                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean   496.400438                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev  3535.731274                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-16383        19002     99.13%     99.13% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::16384-32767          134      0.70%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-49151           21      0.11%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::49152-65535            6      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-81919            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::81920-98303            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::98304-114687            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::114688-131071            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu3.dtb.walker.walkWaitTime::147456-163839            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total        18851                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples         6073                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 12561.337066                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 10324.019552                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev  7892.573788                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-16383         4743     78.10%     78.10% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::16384-32767         1245     20.50%     98.60% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-49151           80      1.32%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::49152-65535            1      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-81919            1      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::81920-98303            1      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-147455            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkWaitTime::total        19169                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples         6102                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 13023.926581                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 10629.521640                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev  8508.049417                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-16383         4638     76.01%     76.01% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::16384-32767         1335     21.88%     97.89% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-49151          115      1.88%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::49152-65535            9      0.15%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-81919            1      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::81920-98303            1      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-147455            2      0.03%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu3.dtb.walker.walkCompletionTime::147456-163839            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total         6073                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples  -8078927064                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     0.145347                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::stdev     0.140537                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-1  -8125083564    100.57%    100.57% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::2-3     32811500     -0.41%    100.17% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-5      7062500     -0.09%    100.08% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::6-7      2662500     -0.03%    100.04% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-9      1263000     -0.02%    100.03% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::10-11       812000     -0.01%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-13       353000     -0.00%    100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::14-15       734000     -0.01%    100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-17       142000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::18-19       166000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-21        33500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::22-23        14500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-25        66000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::26-27         5000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkCompletionTime::total         6102                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples  -8042044064                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean     0.800774                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::stdev     0.238438                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1  -8088297564    100.58%    100.58% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::2-3     32871500     -0.41%    100.17% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-5      7478500     -0.09%    100.07% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::6-7      2286500     -0.03%    100.04% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-9      1244500     -0.02%    100.03% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::10-11       730000     -0.01%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-13       408500     -0.01%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::14-15       765000     -0.01%    100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-17       196000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::18-19       177000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-21        43000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::22-23        10500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-25        11000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::26-27         4500     -0.00%    100.00% # Table walker pending requests distribution
 system.cpu3.dtb.walker.walksPending::28-29         3500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::30-31        27500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total  -8078927064                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K         1773     69.37%     69.37% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::1M          783     30.63%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total         2556                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        32594                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walksPending::30-31        23500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total  -8042044064                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K         1824     68.91%     68.91% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::1M          823     31.09%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total         2647                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data        33037                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        32594                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2556                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total        33037                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data         2647                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2556                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total        35150                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total         2647                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total        35684                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                     7207975                       # DTB read hits
-system.cpu3.dtb.read_misses                     28184                       # DTB read misses
-system.cpu3.dtb.write_hits                    5370312                       # DTB write hits
-system.cpu3.dtb.write_misses                     4410                       # DTB write misses
+system.cpu3.dtb.read_hits                     7253561                       # DTB read hits
+system.cpu3.dtb.read_misses                     28594                       # DTB read misses
+system.cpu3.dtb.write_hits                    5432397                       # DTB write hits
+system.cpu3.dtb.write_misses                     4443                       # DTB write misses
 system.cpu3.dtb.flush_tlb                         161                       # Number of times complete TLB was flushed
 system.cpu3.dtb.flush_tlb_mva                     273                       # Number of times TLB was flushed by MVA
 system.cpu3.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu3.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                    1876                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                      480                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                   811                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_entries                    1945                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                      458                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                   789                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                      348                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                 7236159                       # DTB read accesses
-system.cpu3.dtb.write_accesses                5374722                       # DTB write accesses
+system.cpu3.dtb.perms_faults                      336                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                 7282155                       # DTB read accesses
+system.cpu3.dtb.write_accesses                5436840                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                         12578287                       # DTB hits
-system.cpu3.dtb.misses                          32594                       # DTB misses
-system.cpu3.dtb.accesses                     12610881                       # DTB accesses
+system.cpu3.dtb.hits                         12685958                       # DTB hits
+system.cpu3.dtb.misses                          33037                       # DTB misses
+system.cpu3.dtb.accesses                     12718995                       # DTB accesses
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1671,67 +1668,69 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.walks                     4409                       # Table walker walks requested
-system.cpu3.itb.walker.walksShort                4409                       # Table walker walks initiated with short descriptors
-system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1513                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2804                       # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore           92                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples         4317                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1474.635163                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev  6438.514221                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-8191         4058     94.00%     94.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::8192-16383          112      2.59%     96.59% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::16384-24575           78      1.81%     98.40% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::24576-32767           36      0.83%     99.24% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-40959           12      0.28%     99.51% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::40960-49151            6      0.14%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::49152-57343            4      0.09%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::57344-65535            4      0.09%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-73727            1      0.02%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::73728-81919            1      0.02%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::81920-90111            3      0.07%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::90112-98303            1      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::106496-114687            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total         4317                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples         1329                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 13040.632054                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 10790.250081                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev  7776.712895                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-4095           24      1.81%      1.81% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::4096-8191          403     30.32%     32.13% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::8192-12287          359     27.01%     59.14% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::12288-16383          209     15.73%     74.87% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::16384-20479           19      1.43%     76.30% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::20480-24575          282     21.22%     97.52% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::24576-28671           11      0.83%     98.34% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::28672-32767            1      0.08%     98.42% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-36863            1      0.08%     98.50% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::36864-40959            9      0.68%     99.17% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::40960-45055            7      0.53%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::45056-49151            3      0.23%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::53248-57343            1      0.08%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total         1329                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples  -8082078064                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     1.066049                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0      536728704     -6.64%     -6.64% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1    -8620989268    106.67%    100.03% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2        1669000     -0.02%    100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3         344000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         120000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5          49500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total  -8082078064                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K          894     72.27%     72.27% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::1M          343     27.73%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total         1237                       # Table walker page sizes translated
+system.cpu3.itb.walker.walks                     4585                       # Table walker walks requested
+system.cpu3.itb.walker.walksShort                4585                       # Table walker walks initiated with short descriptors
+system.cpu3.itb.walker.walksShortTerminationLevel::Level1         1570                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksShortTerminationLevel::Level2         2921                       # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore           94                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples         4491                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1433.533734                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev  6108.583355                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-8191         4220     93.97%     93.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::8192-16383          132      2.94%     96.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::16384-24575           81      1.80%     98.71% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::24576-32767           32      0.71%     99.42% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-40959            7      0.16%     99.58% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::40960-49151            7      0.16%     99.73% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::49152-57343            2      0.04%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::57344-65535            2      0.04%     99.82% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-73727            2      0.04%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::73728-81919            2      0.04%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::81920-90111            1      0.02%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::90112-98303            2      0.04%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-106495            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total         4491                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples         1402                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 13658.345221                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 11345.191727                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev  7983.067706                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-4095           20      1.43%      1.43% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::4096-8191          403     28.74%     30.17% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::8192-12287          331     23.61%     53.78% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::12288-16383          266     18.97%     72.75% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::16384-20479           21      1.50%     74.25% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::20480-24575          301     21.47%     95.72% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::24576-28671           32      2.28%     98.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::28672-32767            5      0.36%     98.36% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-36863            3      0.21%     98.57% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::36864-40959            5      0.36%     98.93% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::40960-45055           11      0.78%     99.71% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::45056-49151            2      0.14%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::53248-57343            1      0.07%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::57344-61439            1      0.07%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total         1402                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples  -8073456064                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.704569                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.455286                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0    -2382514092     29.51%     29.51% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1    -5692999972     70.52%    100.03% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2        1707500     -0.02%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3         179000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4         115500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5          56000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total  -8073456064                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K          964     73.70%     73.70% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::1M          344     26.30%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total         1308                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4409                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4409                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst         4585                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total         4585                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1237                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1237                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total         5646                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                     9814748                       # ITB inst hits
-system.cpu3.itb.inst_misses                      4409                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst         1308                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total         1308                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total         5893                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                     9829313                       # ITB inst hits
+system.cpu3.itb.inst_misses                      4585                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
@@ -1740,318 +1739,318 @@ system.cpu3.itb.flush_tlb                         161                       # Nu
 system.cpu3.itb.flush_tlb_mva                     273                       # Number of times TLB was flushed by MVA
 system.cpu3.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu3.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                    1248                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_entries                    1305                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                      724                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                      736                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                 9819157                       # ITB inst accesses
-system.cpu3.itb.hits                          9814748                       # DTB hits
-system.cpu3.itb.misses                           4409                       # DTB misses
-system.cpu3.itb.accesses                      9819157                       # DTB accesses
-system.cpu3.numCycles                        57366661                       # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses                 9833898                       # ITB inst accesses
+system.cpu3.itb.hits                          9829313                       # DTB hits
+system.cpu3.itb.misses                           4585                       # DTB misses
+system.cpu3.itb.accesses                      9833898                       # DTB accesses
+system.cpu3.numCycles                        58255672                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles          20761268                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                      52178877                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   13267477                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches           9350730                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                     33698249                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                1591212                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                     69410                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                1107                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles              256                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles       135306                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        74302                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles          555                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                  9813722                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes               210476                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                   2135                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples          55536037                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.135538                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.278414                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles          20975785                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                      52339111                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   13301320                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches           9365882                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                     34230578                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                1600984                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                     75110                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles                 679                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles              249                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles       165248                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        76892                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles          429                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                  9828258                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes               213311                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                   2192                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples          56325440                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.124081                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.271401                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                41384973     74.52%     74.52% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                 1837710      3.31%     77.83% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                 1169547      2.11%     79.93% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 3702482      6.67%     86.60% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                  911101      1.64%     88.24% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                  554699      1.00%     89.24% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 2918405      5.25%     94.50% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                  606250      1.09%     95.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                 2450870      4.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                42135738     74.81%     74.81% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                 1842427      3.27%     78.08% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                 1174880      2.09%     80.16% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 3692209      6.56%     86.72% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                  916764      1.63%     88.35% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                  558692      0.99%     89.34% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 2925255      5.19%     94.53% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                  602319      1.07%     95.60% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                 2477156      4.40%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total            55536037                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.231275                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.909568                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                14514304                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles             31619877                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                  7786036                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles               908366                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                707244                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved              976635                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred                89470                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts              44785495                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts               293014                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles                707244                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                15002070                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                3712166                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles      21623767                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                  8198323                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles              6292235                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts              42920389                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                  988                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents                999285                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                100726                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents               4827959                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.RenamedOperands           44612381                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            197148279                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups        47945794                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups             3725                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps             37230904                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                 7381477                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts            716136                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts        666620                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                  5136604                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads             7692057                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores            5940620                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          1092936                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         1536247                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                  41290259                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded             501894                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                 39299013                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued            52056                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined        5966024                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     13660779                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved         53087                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples     55536037                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.707631                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.411142                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total            56325440                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.228327                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.898438                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                14665639                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles             32213939                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                  7840695                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles               894660                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                710284                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved              980840                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred                91372                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts              45017968                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts               299154                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles                710284                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                15152191                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                3825257                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles      22150592                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                  8241060                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles              6245828                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts              43133854                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                  881                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents                923199                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                 93585                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents               4851932                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands           44760576                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            198184537                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups        48159961                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups             3993                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps             37280661                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                 7479915                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts            724518                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts        673070                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                  5055817                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads             7747142                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores            6009339                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          1097938                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         1536830                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                  41471519                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded             515844                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                 39457989                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued            52603                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined        6038881                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     13851448                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved         54585                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples     56325440                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.700536                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.407802                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0           39933168     71.90%     71.90% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1            5154759      9.28%     81.19% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2            3998218      7.20%     88.39% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3            3241689      5.84%     94.22% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4            1260306      2.27%     96.49% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5             769738      1.39%     97.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6             826217      1.49%     99.37% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7             240001      0.43%     99.80% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8             111941      0.20%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0           40673603     72.21%     72.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1            5189038      9.21%     81.42% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2            3994905      7.09%     88.52% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3            3229029      5.73%     94.25% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4            1266179      2.25%     96.50% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5             777932      1.38%     97.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6             838695      1.49%     99.37% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7             242964      0.43%     99.80% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8             113095      0.20%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total       55536037                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total       56325440                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                  56634      9.59%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      9.59% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                279182     47.28%     56.87% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite               254722     43.13%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                  56406      9.38%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      9.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                283401     47.13%     56.51% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite               261530     43.49%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass               79      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu             26205156     66.68%     66.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult               29936      0.08%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc          2339      0.01%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.76% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead             7421328     18.88%     85.65% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite            5640175     14.35%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass               83      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu             26250639     66.53%     66.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult               29940      0.08%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.60% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc          2415      0.01%     66.61% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     66.61% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     66.61% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.61% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead             7470638     18.93%     85.54% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite            5704269     14.46%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total              39299013                       # Type of FU issued
-system.cpu3.iq.rate                          0.685050                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                     590538                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.015027                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads         134768668                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes         47782568                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses     38141743                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads               7989                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes              4328                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses         3477                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses              39885201                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                   4271                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads          170012                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total              39457989                       # Type of FU issued
+system.cpu3.iq.rate                          0.677324                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                     601337                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.015240                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads         135886575                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes         48050717                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses     38292520                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads               8783                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes              4710                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses         3829                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses              40054524                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                   4719                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads          171660                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      1165546                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses         1325                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation        29357                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores       600603                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      1179297                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses         1335                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation        29850                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores       609995                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads       108801                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked        44606                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads       109451                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked        43922                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                707244                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                3069413                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles               520763                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts           41839488                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts            76423                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts              7692057                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts             5940620                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts            259410                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                 22603                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents               492210                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents         29357                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect        139025                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect       123161                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts              262186                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts             38971879                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts              7290710                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts           294612                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles                710284                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                3184032                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles               520990                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts           42035728                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts            77277                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts              7747142                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts             6009339                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts            266862                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                 22482                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents               492410                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents         29850                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect        141082                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect       125238                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts              266320                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts             39125976                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts              7338106                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts           299066                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        47335                       # number of nop insts executed
-system.cpu3.iew.exec_refs                    12872001                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                 7242885                       # Number of branches executed
-system.cpu3.iew.exec_stores                   5581291                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.679347                       # Inst execution rate
-system.cpu3.iew.wb_sent                      38686705                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                     38145220                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                 19984457                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                 34832102                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        48365                       # number of nop insts executed
+system.cpu3.iew.exec_refs                    12982427                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                 7264644                       # Number of branches executed
+system.cpu3.iew.exec_stores                   5644321                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.671625                       # Inst execution rate
+system.cpu3.iew.wb_sent                      38838436                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                     38296349                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                 20014644                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                 34860024                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      0.664937                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.573737                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      0.657384                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.574143                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts        5981270                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls         448807                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts           218548                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples     54250638                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.660854                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.552983                       # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts        6055415                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls         461259                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts           221839                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples     55029535                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.653724                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.548863                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0     40430906     74.53%     74.53% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1      6113695     11.27%     85.80% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2      3127574      5.77%     91.56% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      1326177      2.44%     94.01% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4       716812      1.32%     95.33% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5       505346      0.93%     96.26% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6       950559      1.75%     98.01% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7       229517      0.42%     98.43% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8       850052      1.57%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0     41164710     74.80%     74.80% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1      6174910     11.22%     86.03% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2      3105944      5.64%     91.67% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      1319292      2.40%     94.07% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4       711711      1.29%     95.36% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5       496248      0.90%     96.26% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6       960829      1.75%     98.01% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7       230731      0.42%     98.43% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8       865160      1.57%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total     54250638                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts            29358701                       # Number of instructions committed
-system.cpu3.commit.committedOps              35851741                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total     55029535                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts            29416260                       # Number of instructions committed
+system.cpu3.commit.committedOps              35974129                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      11866528                       # Number of memory references committed
-system.cpu3.commit.loads                      6526511                       # Number of loads committed
-system.cpu3.commit.membars                     173804                       # Number of memory barriers committed
-system.cpu3.commit.branches                   6837387                       # Number of branches committed
-system.cpu3.commit.fp_insts                      3456                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                 31324780                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             1241793                       # Number of function calls committed.
+system.cpu3.commit.refs                      11967189                       # Number of memory references committed
+system.cpu3.commit.loads                      6567845                       # Number of loads committed
+system.cpu3.commit.membars                     179077                       # Number of memory barriers committed
+system.cpu3.commit.branches                   6853829                       # Number of branches committed
+system.cpu3.commit.fp_insts                      3808                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                 31432423                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             1245286                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu        23953965     66.81%     66.81% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult          28909      0.08%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.89% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc         2339      0.01%     66.90% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.90% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.90% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.90% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead        6526511     18.20%     85.11% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite       5340017     14.89%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu        23975618     66.65%     66.65% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult          28907      0.08%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv               0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc         2415      0.01%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.73% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead        6567845     18.26%     84.99% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite       5399344     15.01%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total         35851741                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events               850052                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                    89574127                       # The number of ROB reads
-system.cpu3.rob.rob_writes                   84953819                       # The number of ROB writes
-system.cpu3.timesIdled                         222816                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                        1830624                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                  5161214707                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                   29333089                       # Number of Instructions Simulated
-system.cpu3.committedOps                     35826129                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.955698                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.955698                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.511326                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.511326                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                42472744                       # number of integer regfile reads
-system.cpu3.int_regfile_writes               24152717                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                    14290                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                   12064                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                137731283                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                14845540                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads               75477983                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                336291                       # number of misc regfile writes
+system.cpu3.commit.op_class_0::total         35974129                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events               865160                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                    90545687                       # The number of ROB reads
+system.cpu3.rob.rob_writes                   85357421                       # The number of ROB writes
+system.cpu3.timesIdled                         228818                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                        1930232                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                  5160394940                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                   29390613                       # Number of Instructions Simulated
+system.cpu3.committedOps                     35948482                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.982118                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.982118                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.504511                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.504511                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                42625892                       # number of integer regfile reads
+system.cpu3.int_regfile_writes               24241203                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                    14445                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                   12329                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                138329125                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                14829178                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads               76422783                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes                345191                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30181                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30181                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59010                       # Transaction distribution
@@ -2106,45 +2105,45 @@ system.iobus.pkt_size_system.bridge.master::total       159093
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480317                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             22360000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             27670500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               101500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                18000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                20000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                16500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               32000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               40500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             3278000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             3858000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy               84000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy               90500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            19060000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            22212000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               90000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              114500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy            78461015                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy            78391042                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            48730000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            48071000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            15512000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36409                       # number of replacements
-system.iocache.tags.tagsinuse                1.005075                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.005312                       # Cycle average of tags in use
 system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         249186259009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005075                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062817                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062817                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         249222416009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.005312                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062832                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062832                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2160,14 +2159,14 @@ system.iocache.demand_misses::realview.ide          249                       #
 system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          249                       # number of overall misses
 system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     17563919                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     17563919                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   1966288096                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   1966288096                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     17563919                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     17563919                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     17563919                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     17563919                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     17512919                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     17512919                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   1978574123                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   1978574123                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     17512919                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     17512919                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     17512919                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     17512919                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2184,19 +2183,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 70537.827309                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 70537.827309                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 54324.854151                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 54324.854151                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 70537.827309                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 70537.827309                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 70537.827309                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 70537.827309                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 70333.008032                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 54664.294046                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 54664.294046                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 70333.008032                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 70333.008032                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 70333.008032                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 70333.008032                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           378                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.217391                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -2210,14 +2209,14 @@ system.iocache.demand_mshr_misses::realview.ide          148
 system.iocache.demand_mshr_misses::total          148                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          148                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          148                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     10163919                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     10163919                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   1206938096                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1206938096                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     10163919                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     10163919                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     10163919                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     10163919                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     10112919                       # number of ReadReq MSHR miss cycles
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+system.iocache.WriteLineReq_mshr_miss_latency::total   1219224123                       # number of WriteLineReq MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total     10112919                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.594378                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.594378                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.419252                       # mshr miss rate for WriteLineReq accesses
@@ -2226,392 +2225,382 @@ system.iocache.demand_mshr_miss_rate::realview.ide     0.594378
 system.iocache.demand_mshr_miss_rate::total     0.594378                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide     0.594378                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total     0.594378                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68675.128378                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68675.128378                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79471.791401                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79471.791401                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68675.128378                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68675.128378                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68675.128378                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68675.128378                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68330.533784                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 68330.533784                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.774544                       # average WriteLineReq mshr miss latency
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+system.iocache.demand_avg_mshr_miss_latency::realview.ide 68330.533784                       # average overall mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::total 68330.533784                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   103711                       # number of replacements
-system.l2c.tags.tagsinuse                65095.024716                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5145934                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168963                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.455981                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              80077044000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48951.707616                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.971864                       # Average occupied blocks per requestor
+system.l2c.tags.replacements                   104195                       # number of replacements
+system.l2c.tags.tagsinuse                65091.017513                       # Cycle average of tags in use
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+system.l2c.tags.warmup_cycle              80140567000                       # Cycle when the warmup percentage was hit.
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 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4249.334624                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2262.984305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.967017                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      905.000363                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      870.835112                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    20.993332                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2120.702185                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data      746.628994                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    47.189745                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     3231.570243                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     1686.139222                       # Average occupied blocks per requestor
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-system.l2c.ReadReq_hits::cpu1.itb.walker          966                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu3.itb.walker         4342                       # number of ReadReq hits
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-system.l2c.Writeback_hits::writebacks          692075                       # number of Writeback hits
-system.l2c.Writeback_hits::total               692075                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              10                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data               3                       # number of UpgradeReq hits
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-system.l2c.overall_hits::cpu1.inst             202055                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              90380                       # number of overall hits
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-system.l2c.overall_hits::cpu2.itb.walker         1202                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             490576                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             128067                       # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker        20190                       # number of overall hits
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-system.l2c.overall_hits::cpu3.inst             537675                       # number of overall hits
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+system.l2c.tags.data_accesses                45555294                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4129                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         2050                       # number of ReadReq hits
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 system.l2c.ReadReq_misses::cpu0.dtb.walker            3                       # number of ReadReq misses
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-system.l2c.demand_accesses::cpu3.data          229146                       # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.dtb.walker         4174                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         2070                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         732734                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         345587                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         1848                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker          966                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         203958                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         104919                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        13811                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker         1202                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         495561                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         154357                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker        20253                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.itb.walker         4342                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst         544067                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data         229146                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2858995                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000719                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000483                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000541                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002245                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003111                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.002034                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.991031                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992481                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.979927                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.950318                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.977871                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.304348                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.304348                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.471709                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.398967                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.470387                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.496166                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.471321                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010670                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.009330                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.010059                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.011749                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.010675                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.027411                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.034206                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.019349                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.030155                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.027542                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000719                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000483                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000541                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.009330                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.138574                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002245                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.010059                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.170319                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003111                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.011749                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.207859                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.061460                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000719                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000483                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.010670                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.191144                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000541                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.009330                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.138574                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002245                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.010059                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.170319                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003111                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.011749                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.207859                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.061460                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker       132500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 144919.354839                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 133984.126984                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 131979.797980                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   407.828283                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   901.303538                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data   864.611260                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   463.541667                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        57500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        57500                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 128895.508057                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127375.797227                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132572.194672                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74347.312290                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131107.724645                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 132175.225677                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 133917.318523                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 83628.353398                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131438.719750                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 132292.400604                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 137612.631579                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 80231.325138                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.data 129343.661875                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu2.data 127747.394447                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 133984.126984                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu3.data 133024.595843                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 129343.661875                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu2.data 127747.394447                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu3.data 133024.595843                       # average overall miss latency
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+system.l2c.UpgradeReq_miss_latency::cpu2.data       323500                       # number of UpgradeReq miss cycles
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+system.l2c.overall_accesses::cpu2.inst         502016                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         156629                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker        20679                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker         4601                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst         553534                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data         232548                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2863958                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000726                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000488                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002148                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003337                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.002094                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.991993                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.997449                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.978571                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.954248                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.979937                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.344828                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.344828                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.476294                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.400316                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.472304                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.492713                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.472696                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010929                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007952                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.010231                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.011732                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010670                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.027597                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.034137                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.019529                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.029810                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.027548                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000726                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000488                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.010929                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.194571                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.007952                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.138598                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002148                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.010231                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.170192                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003337                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.011732                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.205175                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.061524                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000726                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000488                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.010929                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.194571                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.007952                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.138598                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002148                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.010231                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.170192                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003337                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.011732                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.205175                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.061524                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 133034.482759                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 138202.898551                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 131313.725490                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   411.764706                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   590.328467                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data  1104.794521                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   463.721264                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        41600                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total        41600                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 129075.992096                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 127432.381378                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 132617.089410                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74640.874616                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130435.265105                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 131964.077103                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 133045.580382                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 82939.049149                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131897.687861                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 131897.109260                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 136799.233627                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 81084.290153                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 130435.265105                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 129572.722339                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 133034.482759                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 131964.077103                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 127774.224406                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 138202.898551                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 133045.580382                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 132994.519313                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 76210.702544                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 130435.265105                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 129572.722339                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 133034.482759                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 131964.077103                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 127774.224406                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 138202.898551                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 133045.580382                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 132994.519313                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 76210.702544                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2620,280 +2609,268 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95006                       # number of writebacks
-system.l2c.writebacks::total                    95006                       # number of writebacks
+system.l2c.writebacks::writebacks               95381                       # number of writebacks
+system.l2c.writebacks::total                    95381                       # number of writebacks
 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            3                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            5                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data           20                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3.data           39                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           59                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data           17                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3.data           44                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           61                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data             20                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data             17                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.data             39                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 67                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.data             44                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 69                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data            20                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data            17                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.data            39                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                67                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           31                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker           63                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total              95                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          396                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          537                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data          746                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1679                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            7                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            7                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        11977                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        24303                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data        43355                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         79635                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1903                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         4982                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst         6387                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        13272                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2562                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data         1967                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data         4236                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total         8765                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1903                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        14539                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           31                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         4982                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        26270                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.dtb.walker           63                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst         6387                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data        47591                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           101767                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1903                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        14539                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           31                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         4982                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        26270                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.dtb.walker           63                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst         6387                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data        47591                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          101767                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3591                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         5668                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3.data         8430                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        17689                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2928                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4375                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6667                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        13970                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         6519                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data        10043                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3.data        15097                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        31659                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      4182500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker      7811000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     12116000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     28029000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     37997000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     52790000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    118816000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data       496500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       496500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1424011500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2852584000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   5314117500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   9590713000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    230468000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    608913000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst    791511500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1630892500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    311126000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    240626500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data    541295500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   1093048000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    230468000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1735137500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      4182500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    608913000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3093210500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker      7811000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst    791511500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data   5855413000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  12326769500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    230468000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1735137500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      4182500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    608913000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   3093210500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker      7811000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst    791511500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data   5855413000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  12326769500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    553110500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1000651500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1613374500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3167136500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    453099500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    762218000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1257223000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2472540500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1006210000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1762869500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2870597500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   5639677000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000541                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002245                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003111                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.001952                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992481                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.979927                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.950318                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.589744                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.304348                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.304348                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.398967                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.470387                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.496166                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.268654                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.009330                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.010053                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.011739                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006716                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.034206                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.019155                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.029880                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016304                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000541                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009330                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.138574                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002245                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010053                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.170190                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003111                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.011739                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.207689                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.035595                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000541                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009330                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.138574                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010053                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.170190                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu3.data     0.207689                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.035595                       # mshr miss rate for overall accesses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 134919.354839                       # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::total 127536.842105                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70780.303030                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70757.914339                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70764.075067                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70765.932102                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 70928.571429                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70928.571429                       # average SCUpgradeReq mshr miss latency
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+system.l2c.overall_mshr_miss_latency::cpu3.data   5863841000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  12396854999                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    574124000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1010894500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1734230000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3319248500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    473518500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    776166500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1359879000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2609564000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1047642500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1787061000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   3094109000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   5928812500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002148                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003337                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.002012                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.997449                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.978571                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.954248                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.587469                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.344828                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.344828                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.400316                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.472304                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.492713                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.270387                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007952                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.010225                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.011723                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.006685                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.034137                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.019367                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.029505                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.016524                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007952                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.138598                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002148                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010225                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.170083                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003337                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.011723                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.204986                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.035752                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007952                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.138598                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002148                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010225                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.170083                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003337                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.011723                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.204986                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.035752                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 123034.482759                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128202.898551                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 126673.469388                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70765.984655                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70745.437956                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70789.726027                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70769.622528                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        72150                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        72150                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 119075.992096                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117432.381378                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122617.089410                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 120488.624032                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120435.265105                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122009.935710                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123076.128679                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122339.474404                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121897.687861                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122035.079051                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127029.798217                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124391.904065                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120435.265105                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119572.722339                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123034.482759                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122009.935710                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117782.075826                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128202.898551                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123076.128679                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123011.621809                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 121072.495888                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120435.265105                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119572.722339                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123034.482759                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122009.935710                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117782.075826                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128202.898551                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123076.128679                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123011.621809                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 121072.495888                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164599.770642                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 185723.773654                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203404.879193                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190138.540414                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167025.925926                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184757.557724                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201583.012155                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189345.813380                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 165687.569192                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185302.882621                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202600.117863                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 189788.805660                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40114                       # Transaction distribution
-system.membus.trans_dist::ReadResp              76298                       # Transaction distribution
+system.membus.trans_dist::ReadResp              76341                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27565                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27565                       # Transaction distribution
-system.membus.trans_dist::Writeback            131166                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8718                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4548                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              7                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4555                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137947                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137947                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         36184                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131541                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8827                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4550                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq             10                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4560                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138388                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138388                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36227                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36194                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105436                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2006                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       488332                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       595784                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       489795                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       597247                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108913                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108913                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 704697                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 706160                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159093                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4012                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17254780                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17417905                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17309820                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17472945                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2320704                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2320704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19738609                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              305                       # Total snoops (count)
-system.membus.snoop_fanout::samples            422679                       # Request fanout histogram
+system.membus.pkt_size::total                19793649                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              304                       # Total snoops (count)
+system.membus.snoop_fanout::samples            423653                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  422679    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  423653    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              422679                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            54961500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              423653                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            54148500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              673000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              680000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           481696064                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           485362066                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          584907455                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          587517958                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           27319765                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           27144297                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2936,59 +2913,60 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5650262                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2839838                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        45471                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            619                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          619                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5660019                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2844678                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        45590                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            617                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          617                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             112063                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2626235                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             111923                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2630935                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27565                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27565                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           760987                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2076983                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2848                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            23                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       761630                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1942576                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          139089                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2842                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            29                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp           2870                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296422                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296422                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1976439                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       537735                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296497                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296497                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1981401                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       537613                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        15186                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5908570                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2617393                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26301                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       100850                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8653114                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    126520888                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97861689                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        42712                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       178096                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              224603385                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          193657                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          5938870                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.020066                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.140226                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5923303                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2617283                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26505                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       100543                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8667634                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    251163000                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97868601                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        43100                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       177856                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              349252557                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          193970                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          4194071                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.021768                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.145924                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5819701     97.99%     97.99% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 119169      2.01%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4102776     97.82%     97.82% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  91295      2.18%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            5938870                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2186534999                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            4194071                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3475552499                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           260919                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1866037017                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1890152632                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         758288292                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         768668207                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11457495                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          11579475                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          47843740                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          47680705                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index b05a1c47b..d53614d95 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.823216                       # Number of seconds simulated
-sim_ticks                                2823215630500                       # Number of ticks simulated
-final_tick                               2823215630500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.823500                       # Number of seconds simulated
+sim_ticks                                2823500156000                       # Number of ticks simulated
+final_tick                               2823500156000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 103983                       # Simulator instruction rate (inst/s)
-host_op_rate                                   126208                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2510129357                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 634500                       # Number of bytes of host memory used
-host_seconds                                  1124.73                       # Real time elapsed on the host
-sim_insts                                   116952239                       # Number of instructions simulated
-sim_ops                                     141949733                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 104004                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126232                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2512003120                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 633188                       # Number of bytes of host memory used
+host_seconds                                  1124.00                       # Real time elapsed on the host
+sim_insts                                   116900784                       # Number of instructions simulated
+sim_ops                                     141885276                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         3840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         3904                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           675712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5138656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         4160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           695680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4658888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           658624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5296736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         4992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           714240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4509448                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11177960                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       675712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       695680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1371392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8449664                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11188968                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       658624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       714240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1372864                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8441728                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8467188                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           60                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8459252                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           61                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10558                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             80810                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           65                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10870                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             72797                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10291                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             83280                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           78                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             11160                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             70462                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175176                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          132026                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175348                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131902                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136407                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               136283                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1383                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              239341                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1820143                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1473                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              246414                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1650206                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              233265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1875947                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              252963                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1597113                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3959301                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         239341                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         246414                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             485755                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2992922                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3962801                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         233265                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         252963                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             486228                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2989810                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2999129                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2992922                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2996016                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2989810                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1383                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             239341                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1826347                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1473                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             246414                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1650209                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             233265                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1882150                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1768                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             252963                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1597116                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6958430                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175177                       # Number of read requests accepted
-system.physmem.writeReqs                       136407                       # Number of write requests accepted
-system.physmem.readBursts                      175177                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     136407                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11201984                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9344                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8480320                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11178024                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8467188                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      146                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6958817                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175349                       # Number of read requests accepted
+system.physmem.writeReqs                       136283                       # Number of write requests accepted
+system.physmem.readBursts                      175349                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     136283                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11214592                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7744                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8471552                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11189032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8459252                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      121                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          40863                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11773                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10998                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11169                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10855                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11706                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11087                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11923                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11611                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10970                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11831                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10190                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9677                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10224                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10941                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10213                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9863                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8674                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8377                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8725                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8463                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8546                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8273                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8696                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8627                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8420                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9181                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7887                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7530                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7884                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8402                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7675                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7145                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          49584                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11393                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10987                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11434                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11274                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11014                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10539                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11403                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11330                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11251                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11289                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10499                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10072                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10665                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11522                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10554                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10002                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8625                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8280                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8885                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8791                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7852                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7876                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8450                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8527                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8486                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8687                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7873                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7718                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8233                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8873                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7886                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7326                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2823215466500                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2823499978000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  174621                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  174793                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 132026                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    103839                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     62706                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6721                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1745                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131902                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    107531                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     59234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      6725                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1718                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
@@ -161,133 +161,132 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                        91                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       88                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::11                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2406                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4769                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     8079                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8538                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8423                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6865                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      199                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::38                      197                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::41                      133                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::46                       77                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::50                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       29                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       23                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65918                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      298.586729                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     176.315744                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     322.746281                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          25059     38.02%     38.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16073     24.38%     62.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6703     10.17%     72.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3821      5.80%     78.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2972      4.51%     82.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1599      2.43%     85.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1035      1.57%     86.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1073      1.63%     88.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7583     11.50%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65918                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6682                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.191410                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      482.907115                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6680     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::6144-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::36864-38911            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6682                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6682                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.830141                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.245831                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.832578                       # Writes before turning the bus around for reads
+system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65648                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      299.873263                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.206399                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.323909                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24801     37.78%     37.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        16133     24.58%     62.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6704     10.21%     72.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3735      5.69%     78.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2850      4.34%     82.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1672      2.55%     85.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1116      1.70%     86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1095      1.67%     88.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7542     11.49%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65648                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6665                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.286122                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      483.294559                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6663     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6665                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6665                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.860165                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.266089                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.031195                       # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::0-3                16      0.24%      0.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 5      0.07%      0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                6      0.09%      0.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               9      0.13%      0.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5722     85.63%     86.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             190      2.84%     89.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              49      0.73%     89.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             177      2.65%     92.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              24      0.36%     92.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             142      2.13%     94.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              60      0.90%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               8      0.12%     95.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              19      0.28%     96.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              22      0.33%     96.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.09%     96.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               9      0.13%     96.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             156      2.33%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.09%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               8      0.12%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              20      0.30%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.04%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.03%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.01%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.16%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6682                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2754544250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                6036375500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    875155000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15737.47                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::4-7                 4      0.06%      0.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                5      0.08%      0.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              10      0.15%      0.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5719     85.81%     86.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             154      2.31%     88.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              55      0.83%     89.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             202      3.03%     92.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              36      0.54%     93.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             143      2.15%     95.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              45      0.68%     95.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               9      0.14%     95.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              15      0.23%     96.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              23      0.35%     96.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.06%     96.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.09%     96.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             162      2.43%     99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.08%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              18      0.27%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.02%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.03%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            17      0.26%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6665                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2742857501                       # Total ticks spent queuing
+system.physmem.totMemAccLat                6028382501                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    876140000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15653.08                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34487.47                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  34403.08                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
@@ -296,41 +295,41 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.81                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.48                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     143966                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97651                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.69                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9060848.65                       # Average gap between requests
-system.physmem.pageHitRate                      78.56                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  261734760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  142811625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 710751600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                443108880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           184398261840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80170181370                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1623600588000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1889727438075                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.354462                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2700891551000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94273140000                       # Time in different power states
+system.physmem.avgRdQLen                         1.46                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        13.09                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144250                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97697                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.32                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9060366.00                       # Average gap between requests
+system.physmem.pageHitRate                      78.65                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  255936240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  139647750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 697117200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                436013280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184417078560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80003561535                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1623919600500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1889868955065                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.336286                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2701419954000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94282760000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     28044170250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     27794238500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  236605320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  129100125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 654482400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                415523520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           184398261840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            79085731860                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1624551859500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1889471564565                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.263829                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2702486818500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94273140000                       # Time in different power states
+system.physmem_1.actEnergy                  240362640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  131150250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 669653400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                421731360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184417078560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            79168489875                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1624652119500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1889700585585                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.276655                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2702647601500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94282760000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     26455661500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     26569784000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
@@ -350,15 +349,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               26494710                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13632658                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           507079                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            16292260                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               12421928                       # Number of BTB hits
+system.cpu0.branchPred.lookups               26581187                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13736110                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           501433                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            16012084                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               12431439                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            76.244352                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6636932                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             27006                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            77.637858                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6636300                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             27516                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -389,92 +388,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    55575                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               55575                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17227                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        13739                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        24609                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        30966                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   596.880450                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  3694.116884                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        30106     97.22%     97.22% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          526      1.70%     98.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          216      0.70%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767           59      0.19%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959           17      0.05%     99.86% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           19      0.06%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-57343            8      0.03%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535            3      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-73727            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::73728-81919            2      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::90112-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::106496-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::114688-122879            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        30966                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        13159                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 13974.808116                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11468.359848                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  9225.442290                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         9399     71.43%     71.43% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3482     26.46%     97.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151          252      1.92%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            8      0.06%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-147455           15      0.11%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                    56625                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               56625                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17270                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        13837                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        25518                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        31107                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   865.432218                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  5323.916597                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-16383        30633     98.48%     98.48% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-32767          331      1.06%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-49151           76      0.24%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-65535           30      0.10%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-81919           18      0.06%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::81920-98303            4      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-114687            5      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-147455            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        31107                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        12481                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 13577.197340                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10994.614021                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  9335.319316                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         9132     73.17%     73.17% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3098     24.82%     97.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151          222      1.78%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535            8      0.06%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-81919            4      0.03%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-147455           14      0.11%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::147456-163839            3      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        13159                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  78337685356                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.743824                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.461899                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  78259560856     99.90%     99.90% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     54393500      0.07%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5     11721500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      4062000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      2302000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11      1574000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13       883500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15      2122500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       542000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19       148500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21        83000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23        91000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25        86000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27        15500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29        21000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31        78500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  78337685356                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3804     69.37%     69.37% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1680     30.63%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5484                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        55575                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total        12481                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  91900460244                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.603534                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.511861                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  91817471744     99.91%     99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     56263000      0.06%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5     12793000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      5164500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      2519500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11      1396500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13      1020000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      2514500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       435000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19       355500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21        97000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23        44500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25       171000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27        35500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29        18000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31       161000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  91900460244                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3454     69.05%     69.05% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1548     30.95%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5002                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        56625                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        55575                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5484                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        56625                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5002                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5484                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        61059                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5002                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        61627                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    13854800                       # DTB read hits
-system.cpu0.dtb.read_misses                     47874                       # DTB read misses
-system.cpu0.dtb.write_hits                   10355704                       # DTB write hits
-system.cpu0.dtb.write_misses                     7701                       # DTB write misses
-system.cpu0.dtb.flush_tlb                         184                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     458                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    13967095                       # DTB read hits
+system.cpu0.dtb.read_misses                     47255                       # DTB read misses
+system.cpu0.dtb.write_hits                   10501947                       # DTB write hits
+system.cpu0.dtb.write_misses                     9370                       # DTB write misses
+system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3595                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      904                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1404                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3287                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      776                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1257                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      604                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                13902674                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10363405                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      595                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14014350                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10511317                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24210504                       # DTB hits
-system.cpu0.dtb.misses                          55575                       # DTB misses
-system.cpu0.dtb.accesses                     24266079                       # DTB accesses
+system.cpu0.dtb.hits                         24469042                       # DTB hits
+system.cpu0.dtb.misses                          56625                       # DTB misses
+system.cpu0.dtb.accesses                     24525667                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -504,802 +499,805 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     7385                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                7385                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2112                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5086                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          187                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         7198                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1405.946096                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  5932.758848                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-8191         6773     94.10%     94.10% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-16383          190      2.64%     96.74% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-24575          140      1.94%     98.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-32767           47      0.65%     99.33% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-40959           11      0.15%     99.49% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-49151           16      0.22%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-57343            7      0.10%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::57344-65535            6      0.08%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-73727            3      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::81920-90111            4      0.06%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         7198                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2651                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 14423.425123                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 12051.974959                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  8640.644527                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         1863     70.28%     70.28% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          733     27.65%     97.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           46      1.74%     99.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535            4      0.15%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-81919            4      0.15%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     7362                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                7362                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2261                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4952                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          149                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         7213                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1612.505199                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  6472.144246                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-8191         6729     93.29%     93.29% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-16383          210      2.91%     96.20% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-24575          172      2.38%     98.59% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-32767           48      0.67%     99.25% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-40959           20      0.28%     99.53% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::40960-49151           11      0.15%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-57343            8      0.11%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::57344-65535            3      0.04%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-73727            4      0.06%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::90112-98303            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::106496-114687            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         7213                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2374                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 13966.512216                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11737.528521                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  8158.100835                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         1734     73.04%     73.04% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          597     25.15%     98.19% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           40      1.68%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2651                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  35368734396                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.609046                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.488267                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    13831462500     39.11%     39.11% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    21534286896     60.89%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        2356000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         358500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         226000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          44500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  35368734396                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1897     76.99%     76.99% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          567     23.01%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2464                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         2374                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  23180714008                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.929856                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.256422                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     1630643500      7.03%      7.03% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    21546495508     92.95%     99.98% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        2812000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         517500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         174500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          71000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  23180714008                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1663     74.74%     74.74% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          562     25.26%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2225                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7385                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7385                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7362                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7362                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2464                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2464                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         9849                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    20114587                       # ITB inst hits
-system.cpu0.itb.inst_misses                      7385                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2225                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2225                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         9587                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    20128372                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7362                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                         184                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     458                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2409                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2149                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1479                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1237                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                20121972                       # ITB inst accesses
-system.cpu0.itb.hits                         20114587                       # DTB hits
-system.cpu0.itb.misses                           7385                       # DTB misses
-system.cpu0.itb.accesses                     20121972                       # DTB accesses
-system.cpu0.numCycles                       110325192                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                20135734                       # ITB inst accesses
+system.cpu0.itb.hits                         20128372                       # DTB hits
+system.cpu0.itb.misses                           7362                       # DTB misses
+system.cpu0.itb.accesses                     20135734                       # DTB accesses
+system.cpu0.numCycles                       111789846                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          39212585                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     103212139                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   26494710                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19058860                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     65985336                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3113233                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    120421                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                6405                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              451                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       171105                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       126190                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          599                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 20113194                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               349758                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3372                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         107179671                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.158056                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.272689                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          39393717                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     103942274                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   26581187                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19067739                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     67197572                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3104883                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    120313                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                4808                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              429                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       187538                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       119721                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          669                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 20127335                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               349524                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3480                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         108577171                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.150570                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.270138                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                78729483     73.46%     73.46% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3807123      3.55%     77.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2383498      2.22%     79.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 8002443      7.47%     86.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1574194      1.47%     88.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 1068807      1.00%     89.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 5993116      5.59%     94.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1028903      0.96%     95.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4592104      4.28%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                80014629     73.69%     73.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3810733      3.51%     77.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2393612      2.20%     79.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 7999548      7.37%     86.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1536045      1.41%     88.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 1088578      1.00%     89.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6047569      5.57%     94.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1035127      0.95%     95.72% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4651330      4.28%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           107179671                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.240151                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.935526                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26754853                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             62165032                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15379945                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1465673                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1413940                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1877729                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               144724                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              85569568                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               471665                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1413940                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                27587165                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6832428                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      44962784                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 16009333                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10373762                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              81846595                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 4353                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1036687                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                217532                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               8369836                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           84011397                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            377628674                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        91338127                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             6488                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             71240050                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                12771347                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1555221                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1457428                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8538957                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            14623040                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11507305                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1985956                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2777400                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  78787811                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1106001                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 75754836                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            87181                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10581035                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23286965                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        104667                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    107179671                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.706802                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.408587                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           108577171                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.237778                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.929801                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26873328                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             63362554                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15407826                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1524257                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1408897                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1872466                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               145547                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              86353471                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               470061                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1408897                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27727925                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6705409                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      45853663                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 16073761                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             10807193                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              82639232                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 2272                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1128991                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                256935                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               8662593                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           84875469                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            381763695                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        92641306                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             5587                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             72346979                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                12528482                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1562352                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1465023                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8851459                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            14739399                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11667463                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          2112364                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2804310                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  79594677                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1116242                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 76600031                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            88073                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10385869                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     23123923                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        102217                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    108577171                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.705489                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.406693                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           76952421     71.80%     71.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10093269      9.42%     81.21% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7647177      7.13%     88.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6479607      6.05%     94.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2319282      2.16%     96.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1495618      1.40%     97.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1437164      1.34%     99.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             490874      0.46%     99.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             264259      0.25%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           77873399     71.72%     71.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10449451      9.62%     81.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7708887      7.10%     88.45% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6446636      5.94%     94.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2344597      2.16%     96.54% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1520287      1.40%     97.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1484500      1.37%     99.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             489237      0.45%     99.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             260177      0.24%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      107179671                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      108577171                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 115831     10.14%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     2      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.14% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                518494     45.41%     55.55% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               507518     44.45%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 112335      9.77%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                528670     45.98%     55.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               508787     44.25%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass              661      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             50460858     66.61%     66.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               56393      0.07%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   2      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4124      0.01%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14247837     18.81%     85.50% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           10984955     14.50%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass              225      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             51038212     66.63%     66.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               57114      0.07%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4060      0.01%     66.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14356873     18.74%     85.45% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           11143544     14.55%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              75754836                       # Type of FU issued
-system.cpu0.iq.rate                          0.686650                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1141845                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.015073                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         259903837                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         90518348                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     73472782                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              14532                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              7678                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         6317                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              76888224                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   7796                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          347025                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              76600031                       # Type of FU issued
+system.cpu0.iq.rate                          0.685215                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1149793                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.015010                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         263002604                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         91143035                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     74349830                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              12495                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              6612                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         5504                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              77742883                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   6716                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          356237                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2039138                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2398                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        52342                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1081901                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1997626                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2287                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        54048                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1072719                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       214750                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       120180                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       202075                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       121659                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1413940                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5391499                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1208860                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           80024251                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           117807                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             14623040                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11507305                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            566411                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 44037                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              1152589                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         52342                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        226715                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       204902                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              431617                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             75186689                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             14022863                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           512703                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1408897                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5279939                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1209588                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           80840958                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           118727                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             14739399                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11667463                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            570481                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 45640                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1151814                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         54048                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        221570                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       202811                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              424381                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             76042804                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             14136234                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           500738                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       130439                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    24907066                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                13969302                       # Number of branches executed
-system.cpu0.iew.exec_stores                  10884203                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.681501                       # Inst execution rate
-system.cpu0.iew.wb_sent                      74615293                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     73479099                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 38405173                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 66942375                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       130039                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    25177582                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14081958                       # Number of branches executed
+system.cpu0.iew.exec_stores                  11041348                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.680230                       # Inst execution rate
+system.cpu0.iew.wb_sent                      75486871                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     74355334                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 38977390                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 68370260                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.666023                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.573705                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.665135                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.570093                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       10599640                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1001334                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           364365                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    104754954                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.662419                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.562446                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       10422774                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1014025                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           357851                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    106178823                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.663049                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.560671                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     77896212     74.36%     74.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12060503     11.51%     85.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6064743      5.79%     91.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2632493      2.51%     94.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1283946      1.23%     95.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       809122      0.77%     96.17% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1758606      1.68%     97.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       423456      0.40%     98.26% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1825873      1.74%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     78820889     74.23%     74.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12387005     11.67%     85.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6099262      5.74%     91.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2661518      2.51%     94.15% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1365099      1.29%     95.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       835592      0.79%     96.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1729906      1.63%     97.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       422537      0.40%     98.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1857015      1.75%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    104754954                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            57128680                       # Number of instructions committed
-system.cpu0.commit.committedOps              69391674                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    106178823                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            58051307                       # Number of instructions committed
+system.cpu0.commit.committedOps              70401754                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      23009306                       # Number of memory references committed
-system.cpu0.commit.loads                     12583902                       # Number of loads committed
-system.cpu0.commit.membars                     411216                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13247589                       # Number of branches committed
-system.cpu0.commit.fp_insts                      6270                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 60931939                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2625183                       # Number of function calls committed.
+system.cpu0.commit.refs                      23336517                       # Number of memory references committed
+system.cpu0.commit.loads                     12741773                       # Number of loads committed
+system.cpu0.commit.membars                     415885                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13388774                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5482                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 61799925                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2627242                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        46323475     66.76%     66.76% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          54770      0.08%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4123      0.01%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.84% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12583902     18.13%     84.98% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10425404     15.02%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        47005628     66.77%     66.77% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55549      0.08%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4060      0.01%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12741773     18.10%     84.95% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10594744     15.05%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         69391674                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1825873                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   170570043                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  162411378                       # The number of ROB writes
-system.cpu0.timesIdled                         376879                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3145521                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3401736013                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   57049783                       # Number of Instructions Simulated
-system.cpu0.committedOps                     69312777                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.933841                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.933841                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.517106                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.517106                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                81821198                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               46866866                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    17105                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   13418                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                265587152                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                27327021                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              147986326                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                766351                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           853611                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.969012                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42370591                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           854123                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.607130                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total         70401754                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1857015                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   172799952                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  164051440                       # The number of ROB writes
+system.cpu0.timesIdled                         381792                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3212675                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2095454483                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   57974599                       # Number of Instructions Simulated
+system.cpu0.committedOps                     70325046                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.928256                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.928256                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.518603                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.518603                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                83013564                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               47348236                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    16364                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13356                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                268593239                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                27791636                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              149451268                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                777954                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           855224                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.968896                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42357273                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           855736                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.498061                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        186702500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   245.218931                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   266.750082                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.478943                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.520996                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   250.010146                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   261.958750                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.488301                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.511638                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999939                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189281396                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189281396                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12194786                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12990656                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25185442                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7797154                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      8115139                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15912293                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       180462                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       183787                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       364249                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       226816                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       219266                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       446082                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       233369                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       225947                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459316                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     19991940                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     21105795                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41097735                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20172402                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21289582                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41461984                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       443820                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       393552                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       837372                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1867983                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1822110                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3690093                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       116689                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        67398                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       184087                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13736                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14086                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27822                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           22                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           37                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           59                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2311803                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2215662                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4527465                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2428492                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2283060                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4711552                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7869813000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6681390000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14551203000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133422309506                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 119214285196                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 252636594702                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    223256500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    190032500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    413289000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       642500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1203500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      1846000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 141292122506                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 125895675196                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 267187797702                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 141292122506                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 125895675196                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 267187797702                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     12638606                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13384208                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26022814                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9665137                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9937249                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19602386                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       297151                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       251185                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       548336                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       240552                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       233352                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       473904                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       233391                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       225984                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459375                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22303743                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23321457                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45625200                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     22600894                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23572642                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46173536                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.035116                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.029404                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032178                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.193270                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.183362                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188247                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.392693                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.268320                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335719                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.057102                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.060364                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058708                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000094                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000164                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000128                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.103651                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.095005                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.099232                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.107451                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.096852                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.102040                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17731.992700                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16977.146603                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17377.226609                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71425.869243                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 65426.502898                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 68463.476314                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16253.385265                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13490.877467                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14854.755230                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 29204.545455                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 32527.027027                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 31288.135593                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61117.717429                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 56820.794506                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 59014.878680                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 58181.012129                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 55143.393164                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 56709.083907                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1668942                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       344724                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            52797                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           2974                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.610546                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   115.912576                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses        189272310                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189272310                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12310382                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     12874546                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       25184928                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      7941393                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total      15899589                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       183968                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180294                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       364262                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       229947                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       216143                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       446090                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236320                       # number of StoreCondReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total       459301                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20251775                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     20832742                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41084517                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20435743                       # number of overall hits
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+system.cpu0.dcache.overall_hits::total       41448779                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       435921                       # number of ReadReq misses
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+system.cpu0.dcache.ReadReq_misses::total       840807                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1879167                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1817887                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      3697054                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       117369                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        66831                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       184200                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13653                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14181                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        27834                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data           33                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data           38                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           71                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2315088                       # number of demand (read+write) misses
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+system.cpu0.dcache.demand_misses::total       4537861                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2432457                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      2289604                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4722061                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7255753500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7425105000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  14680858500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137676029415                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 114829611127                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 252505640542                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    218997000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    196633500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    415630500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       943000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1495500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      2438500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 144931782915                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 122254716127                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 267186499042                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 144931782915                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 122254716127                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 267186499042                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     12746303                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     13279432                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     26025735                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9820560                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9776083                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19596643                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       301337                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       247125                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       548462                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       243600                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       230324                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       473924                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236353                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223019                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       459372                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     22566863                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     23055515                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     45622378                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     22868200                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     23302640                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     46170840                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034200                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030490                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.032307                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191350                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.185952                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188658                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.389494                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.270434                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335848                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056047                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061570                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058731                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000140                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000170                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000155                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102588                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096410                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.099466                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106369                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098255                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.102274                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16644.652357                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18338.754612                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17460.438008                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73264.392901                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63166.528572                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 68299.148604                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16040.210943                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13865.982653                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14932.474671                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28575.757576                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 39355.263158                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 34345.070423                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62603.142047                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 55000.990262                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 58879.392525                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59582.464527                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 53395.572390                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 56582.602182                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1675298                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       341272                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            52888                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           3016                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.676335                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   113.153846                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       704529                       # number of writebacks
-system.cpu0.dcache.writebacks::total           704529                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       234419                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       177315                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       411734                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1718052                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1672745                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3390797                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         8852                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9685                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18537                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1952471                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1850060                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3802531                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1952471                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1850060                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3802531                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       209401                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       216237                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       425638                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       149931                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       149365                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299296                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74210                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48624                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       122834                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4884                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4401                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9285                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           22                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           37                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           59                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       359332                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       365602                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       724934                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       433542                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       414226                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       847768                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14882                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16247                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.writebacks::writebacks       704987                       # number of writebacks
+system.cpu0.dcache.writebacks::total           704987                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       227007                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       186874                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       413881                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1727391                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1670069                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3397460                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         8885                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9612                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18497                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1954398                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1856943                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3811341                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1954398                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1856943                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3811341                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       208914                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       218012                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       426926                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151776                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       147818                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       299594                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74095                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48646                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       122741                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4768                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4569                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9337                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           33                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           38                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           71                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       360690                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       365830                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       726520                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       434785                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       414476                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       849261                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14744                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16385                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15129                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12459                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15212                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12376                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30011                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28706                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        29956                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28761                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3375153500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3319848000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6695001500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10890989929                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  10174119354                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21065109283                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1087064000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    772421000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1859485000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96297500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     58981000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    155278500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       620500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1166500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1787000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14266143429                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13493967354                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  27760110783                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15353207429                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  14266388354                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  29619595783                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2817683000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3126439500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5944122500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2431141924                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2360887452                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4792029376                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5248824924                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5487326952                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10736151876                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016568                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016156                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016356                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015513                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015031                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015268                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.249738                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.193578                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224012                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.020303                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.018860                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019593                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000094                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000164                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000128                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016111                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015677                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015889                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019183                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017572                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018360                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.134584                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15352.821210                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15729.332202                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 72640.013933                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 68115.819328                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70382.194493                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14648.484032                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15885.591477                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15138.194637                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19716.932842                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13401.726880                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16723.586430                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 28204.545455                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 31527.027027                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30288.135593                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39701.845171                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36908.899169                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38293.293987                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35413.425756                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34441.074085                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34938.327211                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189334.968418                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192431.802794                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190951.283369                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160694.158504                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189492.531664                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173699.774395                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174896.702009                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191156.098098                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182845.715483                       # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3330300500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3396411500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6726712000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11231056881                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9824685455                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21055742336                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1111837000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    752623000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1864460000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96489000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     61648000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    158137000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       910000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1457500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2367500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14561357381                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13221096955                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  27782454336                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15673194381                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  13973719955                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  29646914336                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2960669500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3341308500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301978000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2589197924                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2495038452                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084236376                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5549867424                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5836346952                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11386214376                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016390                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016417                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016404                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015455                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015120                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015288                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.245887                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.196848                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223791                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019573                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019837                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019701                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000140                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000170                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000155                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015983                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015867                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015925                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019013                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017787                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018394                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15941.011612                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.011706                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15756.154462                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73997.581179                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66464.743502                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70280.921300                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15005.560429                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15471.426222                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15190.197245                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20236.786913                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13492.667980                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16936.596337                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27575.757576                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 38355.263158                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33345.070423                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40370.837509                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36140.002064                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38240.453581                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36048.148811                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33714.183584                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34909.073107                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200805.039338                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203924.839792                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.171448                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170207.594268                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201602.977699                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184291.589677                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185267.306182                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202925.731094                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193916.827767                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1936695                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.472430                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           38860636                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1937207                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            20.060136                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      11042568500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   296.854540                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   214.617890                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.579794                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.419176                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998970                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          1936787                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.471074                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           38830098                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1937299                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            20.043420                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      11154875500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   205.082456                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   306.388618                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.400552                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.598415                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998967                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          162                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         42883011                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        42883011                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     19112796                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19747840                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       38860636                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     19112796                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19747840                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        38860636                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     19112796                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19747840                       # number of overall hits
-system.cpu0.icache.overall_hits::total       38860636                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       999725                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1085355                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2085080                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       999725                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1085355                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2085080                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       999725                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1085355                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2085080                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14134312480                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15390349487                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  29524661967                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14134312480                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  15390349487                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  29524661967                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14134312480                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  15390349487                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  29524661967                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     20112521                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20833195                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     40945716                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     20112521                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20833195                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     40945716                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     20112521                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     20833195                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     40945716                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.049707                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.052097                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050923                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.049707                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.052097                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.050923                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.049707                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.052097                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050923                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14138.200485                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14180.014361                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14159.966029                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14138.200485                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14180.014361                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14159.966029                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14138.200485                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14180.014361                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14159.966029                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        20835                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         42853283                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42853283                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     19119269                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     19710829                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       38830098                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     19119269                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     19710829                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        38830098                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     19119269                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     19710829                       # number of overall hits
+system.cpu0.icache.overall_hits::total       38830098                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1007396                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1078417                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2085813                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1007396                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      1078417                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2085813                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1007396                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1078417                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2085813                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14294314981                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15434234486                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  29728549467                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14294314981                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  15434234486                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  29728549467                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14294314981                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  15434234486                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  29728549467                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     20126665                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     20789246                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     40915911                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     20126665                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     20789246                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     40915911                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     20126665                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     20789246                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     40915911                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050053                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.051874                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.050978                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050053                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.051874                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.050978                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050053                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.051874                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.050978                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14189.370398                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14311.935444                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14252.739563                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14189.370398                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14311.935444                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14252.739563                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14189.370398                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14311.935444                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14252.739563                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        19244                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              782                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              808                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    26.643223                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.816832                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        70586                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        77198                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       147784                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        70586                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        77198                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       147784                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        70586                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        77198                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       147784                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       929139                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1008157                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1937296                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       929139                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1008157                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1937296                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       929139                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1008157                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1937296                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1936787                       # number of writebacks
+system.cpu0.icache.writebacks::total          1936787                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71558                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76882                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       148440                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        71558                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        76882                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       148440                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        71558                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        76882                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       148440                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       935838                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1001535                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1937373                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       935838                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      1001535                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1937373                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       935838                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      1001535                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1937373                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total          668                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total          668                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12404793984                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13457356489                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  25862150473                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12404793984                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13457356489                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  25862150473                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12404793984                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13457356489                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  25862150473                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86442500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86442500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86442500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total     86442500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046197                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048392                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047314                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046197                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048392                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047314                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046197                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048392                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047314                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13350.848456                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13348.472995                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13349.612281                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13350.848456                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13348.472995                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13349.612281                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13350.848456                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13348.472995                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13349.612281                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129404.940120                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129404.940120                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129404.940120                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129404.940120                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12537948486                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13509677989                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  26047626475                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12537948486                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13509677989                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  26047626475                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12537948486                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13509677989                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  26047626475                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86506500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total     86506500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047350                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047350                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047350                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13444.817531                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13444.817531                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13444.817531                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups               27956882                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14656819                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           538960                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17404345                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               13151851                       # Number of BTB hits
+system.cpu1.branchPred.lookups               27828831                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14541667                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           548498                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            17325081                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               13118302                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            75.566481                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6863409                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             29253                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            75.718561                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6848129                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             29493                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1329,82 +1327,86 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    58688                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               58688                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18912                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13793                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore        25983                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        32705                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   608.026296                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3710.555117                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383        32390     99.04%     99.04% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767          251      0.77%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151           38      0.12%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535           12      0.04%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-81919           10      0.03%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::147456-163839            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        32705                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        12474                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 12069.344236                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean  9799.859677                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7714.985856                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191         4605     36.92%     36.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383         5236     41.98%     78.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575         2264     18.15%     97.04% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767          177      1.42%     98.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959           81      0.65%     99.11% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151          107      0.86%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-57343            2      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        12474                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  91615628244                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.688499                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.485401                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3  91592721244     99.97%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7     15376000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11      3652500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15      2610000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19       561000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23       145500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27       138500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31       418000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35         5500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  91615628244                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3400     68.01%     68.01% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1599     31.99%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         4999                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58688                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                    57586                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               57586                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19035                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13643                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore        24908                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        32678                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   702.995899                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  4885.704946                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-16383        32257     98.71%     98.71% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-32767          309      0.95%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-49151           56      0.17%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-65535           25      0.08%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-81919           12      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::81920-98303            4      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-114687            5      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-147455            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        32678                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        13208                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 14797.811932                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 12463.368567                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  8508.122633                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        12903     97.69%     97.69% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535          300      2.27%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303            3      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        13208                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  91471142744                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.733221                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.463957                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1  91384673244     99.91%     99.91% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3     60550000      0.07%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5     13658500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7      4816000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9      2368000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11      1256000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13       753000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15      2182000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       292000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19       158000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21        50500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23        28500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25       277000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27        11000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29         7500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31        61500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  91471142744                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3746     68.55%     68.55% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1719     31.45%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5465                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        57586                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58688                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         4999                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        57586                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5465                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         4999                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        63687                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5465                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        63051                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14526505                       # DTB read hits
-system.cpu1.dtb.read_misses                     49054                       # DTB read misses
-system.cpu1.dtb.write_hits                   10631798                       # DTB write hits
-system.cpu1.dtb.write_misses                     9634                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         178                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     459                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    14412138                       # DTB read hits
+system.cpu1.dtb.read_misses                     49815                       # DTB read misses
+system.cpu1.dtb.write_hits                   10474078                       # DTB write hits
+system.cpu1.dtb.write_misses                     7771                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         185                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3274                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      667                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1336                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    3611                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      776                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  1282                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      600                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14575559                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10641432                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      647                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14461953                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10481849                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         25158303                       # DTB hits
-system.cpu1.dtb.misses                          58688                       # DTB misses
-system.cpu1.dtb.accesses                     25216991                       # DTB accesses
+system.cpu1.dtb.hits                         24886216                       # DTB hits
+system.cpu1.dtb.misses                          57586                       # DTB misses
+system.cpu1.dtb.accesses                     24943802                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1434,382 +1436,386 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     7824                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                7824                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2815                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4844                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          165                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         7659                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1312.247030                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  5391.308444                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-8191         7206     94.09%     94.09% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-16383          209      2.73%     96.81% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-24575          155      2.02%     98.84% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-32767           49      0.64%     99.48% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-40959           13      0.17%     99.65% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-49151           13      0.17%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-57343            4      0.05%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::57344-65535            6      0.08%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-73727            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-90111            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         7659                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         2378                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 12869.007569                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10590.567886                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  8075.239006                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          829     34.86%     34.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383          979     41.17%     76.03% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575          513     21.57%     97.60% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767           16      0.67%     98.28% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959           11      0.46%     98.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151           27      1.14%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         2378                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  31482348100                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.924096                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.265389                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     2393427520      7.60%      7.60% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    29085771080     92.39%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2        2580000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3         481500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4          88000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  31482348100                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1649     74.51%     74.51% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          564     25.49%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2213                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     7940                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                7940                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2768                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4984                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          188                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         7752                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1436.661507                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  6120.056353                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191         7301     94.18%     94.18% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383          193      2.49%     96.67% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575          153      1.97%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767           37      0.48%     99.12% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959           27      0.35%     99.47% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151           16      0.21%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343           11      0.14%     99.82% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535            4      0.05%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727            5      0.06%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::90112-98303            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-106495            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         7752                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2623                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 14933.282501                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 12692.719494                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  8120.359954                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          585     22.30%     22.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383         1248     47.58%     69.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575          629     23.98%     93.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767          104      3.96%     97.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959           23      0.88%     98.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151           26      0.99%     99.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343            4      0.15%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::57344-65535            3      0.11%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::73728-81919            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2623                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  31327211100                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.898331                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.302824                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     3189472000     10.18%     10.18% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    28134324100     89.81%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2        2583000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         637000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         160000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          35000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  31327211100                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1850     75.98%     75.98% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          585     24.02%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2435                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7824                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7824                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7940                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7940                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2213                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2213                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        10037                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    20834938                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7824                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2435                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2435                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        10375                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    20791300                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7940                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         178                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     459                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                         185                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2128                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2403                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1257                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1472                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20842762                       # ITB inst accesses
-system.cpu1.itb.hits                         20834938                       # DTB hits
-system.cpu1.itb.misses                           7824                       # DTB misses
-system.cpu1.itb.accesses                     20842762                       # DTB accesses
-system.cpu1.numCycles                       114249199                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20799240                       # ITB inst accesses
+system.cpu1.itb.hits                         20791300                       # DTB hits
+system.cpu1.itb.misses                           7940                       # DTB misses
+system.cpu1.itb.accesses                     20799240                       # DTB accesses
+system.cpu1.numCycles                       114309908                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          41440028                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     108062066                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27956882                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          20015260                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     67364504                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3251122                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    125092                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                4580                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              348                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       238931                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       130362                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          479                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20833198                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               375306                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3528                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         110929848                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.171009                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.281658                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          41263279                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     107226594                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27828831                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19966431                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     67413560                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3261213                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    132884                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                6791                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              371                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       251452                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       126014                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          455                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20789251                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               378310                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3605                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         110825375                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.163723                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.274017                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                81198239     73.20%     73.20% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3985157      3.59%     76.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2477511      2.23%     79.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8258795      7.45%     86.47% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1633809      1.47%     87.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1136557      1.02%     88.97% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6389922      5.76%     94.73% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1173130      1.06%     95.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4676728      4.22%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                81246984     73.31%     73.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3970774      3.58%     76.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2468449      2.23%     79.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8233318      7.43%     86.55% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1681631      1.52%     88.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1117562      1.01%     89.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6321498      5.70%     94.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1162226      1.05%     95.83% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4622933      4.17%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           110929848                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.244701                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.945845                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                28438107                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             63381229                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 15870082                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1769017                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1471120                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1958077                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               156563                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              89815738                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               503200                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1471120                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                29385148                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                6578856                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      46582606                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16681881                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             10229932                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              85972606                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 3235                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1759145                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                332326                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               7382577                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           89179456                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            395930491                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        95980229                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             5368                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             75492279                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13687169                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1580321                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1483697                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 10084798                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15398688                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11726928                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2180756                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2876636                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  82789954                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1104868                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 79357586                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            91701                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       11257862                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     24898946                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        112169                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    110929848                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.715385                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.405643                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           110825375                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.243451                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.938034                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                28317279                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             63485741                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15848519                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1697419                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1476110                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1966949                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               156570                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              88997857                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               507653                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1476110                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                29247785                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                7012026                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      46712417                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16603449                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              9773269                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              85151296                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 3883                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1655595                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                301575                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               7069337                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           88292342                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            391615779                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        94636441                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             6205                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             74317970                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13974372                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1570590                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1473246                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  9761371                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15285949                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11554817                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2153118                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2760852                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  81958519                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1096065                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 78473689                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            91016                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       11494354                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     25135429                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        116024                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    110825375                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.708084                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.398689                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           79077492     71.29%     71.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10621201      9.57%     80.86% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8213587      7.40%     88.27% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6738763      6.07%     94.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2479052      2.23%     96.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1519430      1.37%     97.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1589812      1.43%     99.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             483396      0.44%     99.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             207115      0.19%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           79269169     71.53%     71.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10544902      9.51%     81.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8143493      7.35%     88.39% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6684211      6.03%     94.42% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2457263      2.22%     96.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1495236      1.35%     97.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1542850      1.39%     99.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             479172      0.43%     99.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             209079      0.19%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      110929848                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      110825375                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  95512      8.42%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     5      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                536739     47.33%     55.75% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               501765     44.25%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                 101177      9.01%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                523345     46.61%     55.62% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               498385     44.38%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             1676      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             53175622     67.01%     67.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               60064      0.08%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              1      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4456      0.01%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14922442     18.80%     85.90% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11193322     14.10%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             2112      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             52572793     66.99%     67.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               59372      0.08%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  1      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4520      0.01%     67.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     67.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14812673     18.88%     85.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11022213     14.05%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              79357586                       # Type of FU issued
-system.cpu1.iq.rate                          0.694601                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1134021                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014290                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         270859048                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         95198962                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     77052102                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              11694                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              6328                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5212                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              80483666                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   6265                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          368068                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              78473689                       # Type of FU issued
+system.cpu1.iq.rate                          0.686499                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1122913                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014309                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         268972635                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         94593002                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     76135780                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              14047                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              7316                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6000                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              79586882                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7608                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          356462                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2171413                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2447                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        53780                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1110791                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2228793                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2378                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        52565                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1113544                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       197752                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        83861                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       209799                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        80325                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1471120                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                5242635                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1056196                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           84025940                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           131684                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15398688                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11726928                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            568087                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 44365                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               998937                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         53780                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        246243                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       216797                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              463040                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             78768106                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14688147                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           530926                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1476110                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                5644573                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1066657                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           83187752                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           132087                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15285949                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11554817                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            564046                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 44633                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              1008979                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         52565                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        252953                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       220957                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              473910                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             77870409                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14572543                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           545823                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       131118                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25774139                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14898432                       # Number of branches executed
-system.cpu1.iew.exec_stores                  11085992                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.689441                       # Inst execution rate
-system.cpu1.iew.wb_sent                      78239059                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     77057314                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 40452895                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 70755105                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       133168                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25490059                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14772585                       # Number of branches executed
+system.cpu1.iew.exec_stores                  10917516                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.681222                       # Inst execution rate
+system.cpu1.iew.wb_sent                      77325591                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     76141780                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 39859971                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 69277952                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.674467                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.571731                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.666100                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.575363                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       11247994                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         992699                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           384482                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    108382892                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.670890                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.556432                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       11469730                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         980041                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           393964                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    108246213                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.661810                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.544617                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     80053687     73.86%     73.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12617943     11.64%     85.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6573081      6.06%     91.57% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2685794      2.48%     94.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1383289      1.28%     95.32% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       946585      0.87%     96.20% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1968943      1.82%     98.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       416822      0.38%     98.40% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1736748      1.60%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     80231551     74.12%     74.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12503324     11.55%     85.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6520168      6.02%     91.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2652912      2.45%     94.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1399925      1.29%     95.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       915869      0.85%     96.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1908410      1.76%     98.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       405906      0.37%     98.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1708148      1.58%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    108382892                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            59978464                       # Number of instructions committed
-system.cpu1.commit.committedOps              72712964                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    108246213                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            59004382                       # Number of instructions committed
+system.cpu1.commit.committedOps              71638427                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      23843412                       # Number of memory references committed
-system.cpu1.commit.loads                     13227275                       # Number of loads committed
-system.cpu1.commit.membars                     402801                       # Number of memory barriers committed
-system.cpu1.commit.branches                  14144728                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5158                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 63547368                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2716364                       # Number of function calls committed.
+system.cpu1.commit.refs                      23498429                       # Number of memory references committed
+system.cpu1.commit.loads                     13057156                       # Number of loads committed
+system.cpu1.commit.membars                     398159                       # Number of memory barriers committed
+system.cpu1.commit.branches                  13983983                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5946                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 62620951                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2707521                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        48806787     67.12%     67.12% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          58309      0.08%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4456      0.01%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       13227275     18.19%     85.40% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10616137     14.60%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        48077932     67.11%     67.11% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          57547      0.08%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4519      0.01%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       13057156     18.23%     85.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10441273     14.57%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         72712964                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1736748                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   177811075                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  170472987                       # The number of ROB writes
-system.cpu1.timesIdled                         411472                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        3319351                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2020087270                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   59902456                       # Number of Instructions Simulated
-system.cpu1.committedOps                     72636956                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.907254                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.907254                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.524314                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.524314                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                85743042                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               48986759                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    16090                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   13161                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                278464634                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                29701060                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              152671939                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                753578                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
+system.cpu1.commit.op_class_0::total         71638427                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1708148                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   176890222                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  168799668                       # The number of ROB writes
+system.cpu1.timesIdled                         412724                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        3484533                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3325413921                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   58926185                       # Number of Instructions Simulated
+system.cpu1.committedOps                     71560230                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.939883                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.939883                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.515495                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.515495                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                84497448                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               48483083                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    17003                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   13376                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                275324862                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                29228214                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              152523655                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                741987                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
@@ -1834,9 +1840,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72914                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72914                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  178392                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
@@ -1859,95 +1865,95 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321096                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321096                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2480221                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             49500500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                88000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy               613500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               48000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6444000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              168000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            38204000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              128000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186358814                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           186303033                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               37000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36738000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36423                       # number of replacements
-system.iocache.tags.tagsinuse                1.069707                       # Cycle average of tags in use
+system.iocache.tags.replacements                36413                       # number of replacements
+system.iocache.tags.tagsinuse                1.069629                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36439                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         236268040000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.069707                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.066857                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.066857                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         236545551000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.069629                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.066852                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.066852                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328113                       # Number of tag accesses
-system.iocache.tags.data_accesses              328113                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          233                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              233                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328023                       # Number of tag accesses
+system.iocache.tags.data_accesses              328023                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          223                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              223                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          233                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               233                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          233                       # number of overall misses
-system.iocache.overall_misses::total              233                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28976877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28976877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4697901937                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4697901937                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28976877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28976877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28976877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28976877                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          233                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            233                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide          223                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          223                       # number of overall misses
+system.iocache.overall_misses::total              223                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     28112876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28112876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4718729157                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4718729157                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28112876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28112876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28112876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28112876                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          233                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             233                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          233                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            233                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          223                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             223                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          223                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            223                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -1956,40 +1962,40 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124364.278970                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124364.278970                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129690.314074                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129690.314074                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124364.278970                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124364.278970                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124364.278970                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124364.278970                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 126066.708520                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126066.708520                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130265.270456                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130265.270456                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126066.708520                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126066.708520                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126066.708520                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126066.708520                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           790                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   84                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.404762                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           36190                       # number of writebacks
 system.iocache.writebacks::total                36190                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          233                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          233                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide          223                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          223                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          233                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          233                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          233                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          233                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17326877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17326877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2886701937                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2886701937                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17326877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17326877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17326877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17326877                       # number of overall MSHR miss cycles
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+system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     16962876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16962876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2907529157                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2907529157                       # number of WriteLineReq MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::realview.ide     16962876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16962876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1998,270 +2004,274 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74364.278970                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74364.278970                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79690.314074                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79690.314074                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74364.278970                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74364.278970                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74364.278970                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74364.278970                       # average overall mshr miss latency
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+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80265.270456                       # average WriteLineReq mshr miss latency
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+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76066.708520                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76066.708520                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76066.708520                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76066.708520                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104486                       # number of replacements
-system.l2c.tags.tagsinuse                65102.270180                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5137781                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169691                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.277275                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              74417430500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48932.992978                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    44.632841                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000308                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5110.689574                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3054.335380                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    49.005856                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     5438.208710                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2472.404533                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000681                       # Average percentage of cache occupancy
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+system.l2c.tags.avg_refs                    30.320397                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   48973.831139                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    38.132682                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000314                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4850.431967                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2918.348251                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    60.276481                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     5708.347671                       # Average occupied blocks per requestor
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 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1024::2         3230                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8952                       # Occupied blocks per task id
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-system.l2c.tags.occ_task_id_percent::1023     0.001404                       # Percentage of cache occupancy per task id
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-system.l2c.ReadReq_hits::cpu1.itb.walker         7416                       # number of ReadReq hits
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-system.l2c.Writeback_hits::writebacks          704529                       # number of Writeback hits
-system.l2c.Writeback_hits::total               704529                       # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1.data              43                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  89                       # number of UpgradeReq hits
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-system.l2c.overall_hits::cpu0.data             355617                       # number of overall hits
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-system.l2c.overall_hits::total                2697588                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker           60                       # number of ReadReq misses
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+system.l2c.tags.age_task_id_blocks_1024::2         3229                       # Occupied blocks per task id
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+system.l2c.tags.data_accesses                45483372                       # Number of data accesses
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+system.l2c.ReadReq_hits::cpu0.itb.walker         7392                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        36712                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         8266                       # number of ReadReq hits
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+system.l2c.WritebackDirty_hits::writebacks       704987                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          704987                       # number of WritebackDirty hits
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 system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.001525                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.967119                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.971673                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.969489                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.227273                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.270270                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.254237                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.491464                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.453002                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.472277                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010666                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.010793                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.010732                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.029126                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.025553                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.027401                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001780                       # miss rate for demand accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.002120                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.001612                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.967502                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.965314                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.966455                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.212121                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.368421                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.295775                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.502508                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.440850                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.472077                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010307                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011150                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.010743                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.028788                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.026205                       # miss rate for ReadSharedReq accesses
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+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001773                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.010666                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.186281                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010793                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.177086                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.061309                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001780                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001773                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.000135                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.010666                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.186281                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010793                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.177086                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.061309                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker       135800                       # average ReadReq miss latency
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+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 136131.147541                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       132500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 133407.692308                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 134539.682540                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   835.920177                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1150.508475                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total         1000                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        64300                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        48600                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 53833.333333                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 133562.047995                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133894.347904                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 133721.048346                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133839.337976                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132364.325765                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 133067.418703                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 135179.302547                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138288.590116                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 136579.112682                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       135800                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 135403.846154                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total       135700                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1143.456963                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1499.617737                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1313.664596                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 34928.571429                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 46035.714286                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 42333.333333                       # average SCUpgradeReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::total 133554.931055                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133797.749896                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132776.981549                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 133250.060022                       # average ReadCleanReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 133839.337976                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 133728.958359                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 133407.692308                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 132364.325765                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 134303.645890                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 133892.413218                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 133839.337976                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 133728.958359                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 133407.692308                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 132364.325765                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 134303.645890                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 133892.413218                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 134039.269572                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 133795.423112                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2270,251 +2280,251 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95836                       # number of writebacks
-system.l2c.writebacks::total                    95836                       # number of writebacks
-system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            8                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            6                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total           14                       # number of ReadCleanReq MSHR hits
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-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           70                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          144                       # number of ReadSharedReq MSHR hits
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-system.l2c.demand_mshr_hits::cpu0.data             74                       # number of demand (read+write) MSHR hits
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-system.l2c.demand_mshr_hits::cpu1.data             70                       # number of demand (read+write) MSHR hits
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-system.l2c.overall_mshr_hits::cpu1.data            70                       # number of overall MSHR hits
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-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           60                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               95712                       # number of writebacks
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 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1475                       # number of UpgradeReq MSHR misses
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 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
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 system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001908                       # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.971673                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.969489                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.270270                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010725                       # mshr miss rate for ReadCleanReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::total     0.966455                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308                       # average ReadReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70782.711864                       # average UpgradeReq mshr miss latency
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-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        71050                       # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122373.769889                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123093.650717                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125359.570125                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128512.481645                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126777.942925                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       125800                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total       125700                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70801.959412                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70787.077982                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70794.847643                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71142.857143                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70857.142857                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70952.380952                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123570.232343                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123537.033309                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 123554.931055                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123275.736837                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125187.249057                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128821.830084                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126862.455726                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123884.203616                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123746.096439                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122373.769889                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124320.527414                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 123910.475487                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       125800                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123728.914440                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124055.667281                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 123809.733679                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123884.203616                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123746.096439                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122373.769889                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.527414                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 123910.475487                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113688.618263                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176834.901223                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179931.587370                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 177090.590213                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149054.497984                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177987.198009                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162120.777149                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113688.618263                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 162830.378861                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179087.682018                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 170136.187539                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123728.914440                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124055.667281                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 123809.733679                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188303.818502                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191423.314007                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188345.771519                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158568.564291                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190096.477052                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172712.012469                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173203.915743                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190852.369528                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 181082.924931                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               31797                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68067                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68202                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
-system.membus.trans_dist::Writeback            132026                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8663                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131902                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8715                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4626                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq             15                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4641                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138194                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138194                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         36271                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq             21                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4647                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138223                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138223                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36406                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       473134                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       580716                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108899                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108899                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 689615                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       473420                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       581002                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108889                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108889                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 689891                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17328028                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17492021                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17331100                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17495093                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19809141                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              503                       # Total snoops (count)
-system.membus.snoop_fanout::samples            415635                       # Request fanout histogram
+system.membus.pkt_size::total                19812213                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              495                       # Total snoops (count)
+system.membus.snoop_fanout::samples            415719                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  415635    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  415719    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              415635                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            95974000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              415719                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95454500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               17812                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1718000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1728500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           923083346                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           923427409                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1016456858                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1018310336                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64493372                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64109029                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
@@ -2557,59 +2567,60 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5623278                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2831878                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        48082                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            557                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          557                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5625045                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2831932                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        48184                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops            419                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops          419                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             147787                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2643011                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             147963                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2644441                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           836563                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2046694                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2917                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            59                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2976                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296419                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296419                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1937296                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       557950                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       836893                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1896241                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          151625                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2832                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            71                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2903                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296799                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296799                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1937373                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       559190                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5772132                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2677725                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        39632                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       158982                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8648471                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124011712                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     99951221                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        59380                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       271116                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              224293429                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          211232                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          5937467                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.022790                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.149234                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5772018                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2682598                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        40560                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       162458                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8657634                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    245374528                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    100080181                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        62636                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       284772                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              345802117                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          207035                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3148875                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.027211                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.162698                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5802151     97.72%     97.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 135316      2.28%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                3063191     97.28%     97.28% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  85684      2.72%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            5937467                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3598371995                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           378877                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3148875                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         5537375493                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           269876                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2908371640                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2909027051                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1327935857                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1330509019                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          24806959                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          24943913                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          91622154                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          91705109                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index 9d627bc78..27dee726c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,169 +1,169 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.573912                       # Number of seconds simulated
-sim_ticks                                47573912126000                       # Number of ticks simulated
-final_tick                               47573912126000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.381663                       # Number of seconds simulated
+sim_ticks                                47381662864000                       # Number of ticks simulated
+final_tick                               47381662864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125865                       # Simulator instruction rate (inst/s)
-host_op_rate                                   148024                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6578075559                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 723980                       # Number of bytes of host memory used
-host_seconds                                  7232.19                       # Real time elapsed on the host
-sim_insts                                   910282032                       # Number of instructions simulated
-sim_ops                                    1070541696                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 174071                       # Simulator instruction rate (inst/s)
+host_op_rate                                   204726                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9833457902                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 805560                       # Number of bytes of host memory used
+host_seconds                                  4818.41                       # Real time elapsed on the host
+sim_insts                                   838745469                       # Number of instructions simulated
+sim_ops                                     986455629                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       153088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       136640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          7678784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         42964232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     17895808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       154176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       129664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3679616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         16152336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     14975872                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        446400                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            104366616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      7678784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3679616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        11358400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     83323200                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        42368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        41792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          6976384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         35367624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      9096640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        59520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        61888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3056960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         12429456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher      7583744                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        432640                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             75149016                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      6976384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3056960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10033344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     59523200                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          83343784                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2392                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2135                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            119981                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            671329                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       279622                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2409                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2026                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             57494                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            252393                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       233998                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6975                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1630754                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1301925                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          59543784                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          662                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker          653                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            109006                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            552632                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       142135                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          930                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          967                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             47765                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            194223                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       118496                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6760                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1174229                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          930050                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1304499                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3218                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2872                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              161407                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              903105                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       376169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3241                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               77345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              339521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       314792                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2193778                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         161407                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          77345                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             238753                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1751447                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               932624                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           882                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              147238                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              746441                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       191987                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1256                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1306                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               64518                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              262326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       160057                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9131                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1586036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         147238                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          64518                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             211756                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1256250                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1751880                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1751447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3218                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2872                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             161407                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             903537                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       376169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3241                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2726                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              77345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             339521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       314792                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9383                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3945658                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1630754                       # Number of read requests accepted
-system.physmem.writeReqs                      1304499                       # Number of write requests accepted
-system.physmem.readBursts                     1630754                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1304499                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                104327040                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     41216                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  83343168                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 104366616                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               83343784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      644                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         221732                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               95834                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              103052                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               97330                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              103782                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              100129                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              106515                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               99389                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               99717                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               91352                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              148680                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              90509                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              96337                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              96747                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             106196                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              95843                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              98698                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               79474                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               83004                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               79696                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               83932                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               80263                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               85902                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               82233                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               81457                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               76873                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               82502                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              77306                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              81622                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              79893                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              86888                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              78601                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              82591                       # Per bank write bursts
+system.physmem.bw_write::total                1256684                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1256250                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          894                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          882                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             147238                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             746876                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       191987                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1256                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1306                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              64518                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             262326                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       160057                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9131                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2842720                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1174229                       # Number of read requests accepted
+system.physmem.writeReqs                       932624                       # Number of write requests accepted
+system.physmem.readBursts                     1174229                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     932624                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 75113152                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     37504                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  59543040                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  75149016                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               59543784                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      586                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         448232                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               71067                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               73380                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               69314                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               74537                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               66547                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               79030                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               66275                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               68082                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               68948                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              127738                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              63222                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              73993                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              67075                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              69321                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              63089                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              72025                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               57427                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61393                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               59144                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61303                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               56823                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63517                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               54876                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               56576                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               56101                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               62480                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              54750                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              61148                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              54574                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              57375                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              53605                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              59268                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          61                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47573910147500                       # Total gap between requests
+system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47381660751500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1630724                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1174199                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1301925                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::2                     53687                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::4                     33585                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::13                      913                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17                      350                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       81                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 930050                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -188,162 +188,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::61                      114                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::63                      169                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1008532                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      186.082044                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     114.846498                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     242.592795                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         603416     59.83%     59.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       198742     19.71%     79.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        66381      6.58%     86.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35101      3.48%     89.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        23988      2.38%     91.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        15328      1.52%     93.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10269      1.02%     94.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9973      0.99%     95.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        45334      4.50%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1008532                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         74360                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.921678                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      319.874978                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          74357    100.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::total         709891                       # Bytes accessed per row activation
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 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::81920-86015            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           74360                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         74360                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.512601                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.043743                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.433062                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           70224     94.44%     94.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            1905      2.56%     97.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             313      0.42%     97.42% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::76-79             107      0.14%     99.91% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::128-131            20      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             6      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::168-171             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           74360                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    52515283986                       # Total ticks spent queuing
-system.physmem.totMemAccLat               83079846486                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8150550000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       32215.79                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           51534                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    26583019130                       # Total ticks spent queuing
+system.physmem.totMemAccLat               48588825380                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5868215000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22650.00                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  50965.79                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.19                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.75                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.19                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.75                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  41400.00                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.59                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.26                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.59                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.26                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.78                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1305984                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    617830                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.12                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  47.44                       # Row buffer hit rate for writes
-system.physmem.avgGap                     16207771.58                       # Average gap between requests
-system.physmem.pageHitRate                      65.61                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3848576760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2099917875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6284834400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4250627280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3107296514400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1215004983300                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27478552093500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31817337547515                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.798037                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45712218150079                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1588597400000                       # Time in different power states
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.83                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     952385                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    441721                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.15                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  47.48                       # Row buffer hit rate for writes
+system.physmem.avgGap                     22489305.50                       # Average gap between requests
+system.physmem.pageHitRate                      66.26                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2710380960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1478878500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4432209600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3052442880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3094739659440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1177500235590                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27396100823250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31680014630220                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.613444                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45575607610794                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1582177740000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    273094361171                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    223874273456                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3775925160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2060276625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6429961200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4187868480                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3107296514400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1217449094850                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27476408136000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31817607776715                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.803717                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45708592383178                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1588597400000                       # Time in different power states
+system.physmem_1.actEnergy                 2656364760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1449405375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4722003000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               2976166800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3094739659440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1182079758375                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27392083725750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31680707083500                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.628058                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45568857815114                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1582177740000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    276721037822                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    230624127636                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -374,18 +376,18 @@ system.realview.nvmem.bw_total::total              28                       # To
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              141076080                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted        100250771                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6354710                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           105662880                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               77608899                       # Number of BTB hits
+system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
+system.cpu0.branchPred.lookups              125258409                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         88001025                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5802079                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            93100413                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               67841086                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            73.449540                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               16417680                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1072595                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.868727                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15085862                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1028654                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -416,63 +418,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   302583                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               302583                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        11677                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        91984                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       302583                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         302583    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       302583                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       103661                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22488.718033                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 20252.846239                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 20697.815033                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       102356     98.74%     98.74% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          167      0.16%     98.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          962      0.93%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           38      0.04%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           45      0.04%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           22      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           45      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           13      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       103661                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   -910187592                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     -910187592    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   -910187592                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        91984     88.74%     88.74% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11677     11.26%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       103661                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       302583                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   252652                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               252652                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         7537                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        66702                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       252652                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         252652    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       252652                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        74239                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22181.016716                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 20809.120487                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 13879.929548                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        73678     99.24%     99.24% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          179      0.24%     99.49% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          332      0.45%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           14      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           15      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        74239                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   -909613592                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     -909613592    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   -909613592                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        66702     89.85%     89.85% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         7537     10.15%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        74239                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       252652                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       302583                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       103661                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       252652                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        74239                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       103661                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       406244                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        74239                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       326891                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    91224751                       # DTB read hits
-system.cpu0.dtb.read_misses                    252123                       # DTB read misses
-system.cpu0.dtb.write_hits                   79969156                       # DTB write hits
-system.cpu0.dtb.write_misses                    50460                       # DTB write misses
+system.cpu0.dtb.read_hits                    81678885                       # DTB read hits
+system.cpu0.dtb.read_misses                    209727                       # DTB read misses
+system.cpu0.dtb.write_hits                   70936828                       # DTB write hits
+system.cpu0.dtb.write_misses                    42925                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              43397                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   39295                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      989                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                 11229                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              37374                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1001                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   33720                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1491                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  8048                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    11007                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                91476874                       # DTB read accesses
-system.cpu0.dtb.write_accesses               80019616                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9709                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                81888612                       # DTB read accesses
+system.cpu0.dtb.write_accesses               70979753                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        171193907                       # DTB hits
-system.cpu0.dtb.misses                         302583                       # DTB misses
-system.cpu0.dtb.accesses                    171496490                       # DTB accesses
+system.cpu0.dtb.hits                        152615713                       # DTB hits
+system.cpu0.dtb.misses                         252652                       # DTB misses
+system.cpu0.dtb.accesses                    152868365                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -502,187 +502,191 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    69790                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                69790                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          704                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        58261                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        69790                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          69790    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        69790                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        58965                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 25666.514034                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 22346.910344                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 25122.368024                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        57570     97.63%     97.63% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071            8      0.01%     97.65% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         1255      2.13%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           40      0.07%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           50      0.08%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           25      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           12      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        58965                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples   -911302092                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     -911302092    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total   -911302092                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        58261     98.81%     98.81% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          704      1.19%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        58965                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    57977                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                57977                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          503                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        46742                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        57977                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          57977    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        57977                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        47245                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 24873.087099                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23068.832563                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 17067.215870                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        43882     92.88%     92.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         2853      6.04%     98.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303           11      0.02%     98.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839          288      0.61%     99.55% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607          169      0.36%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375            7      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            6      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            4      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679           13      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        47245                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples   -910742092                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     -910742092    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total   -910742092                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        46742     98.94%     98.94% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          503      1.06%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        47245                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        69790                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        69790                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57977                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57977                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        58965                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        58965                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       128755                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   253370493                       # ITB inst hits
-system.cpu0.itb.inst_misses                     69790                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        47245                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        47245                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       105222                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   224840362                       # ITB inst hits
+system.cpu0.itb.inst_misses                     57977                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              43397                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   28357                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              37374                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1001                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24328                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   216294                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   193753                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               253440283                       # ITB inst accesses
-system.cpu0.itb.hits                        253370493                       # DTB hits
-system.cpu0.itb.misses                          69790                       # DTB misses
-system.cpu0.itb.accesses                    253440283                       # DTB accesses
-system.cpu0.numCycles                      1081338531                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               224898339                       # ITB inst accesses
+system.cpu0.itb.hits                        224840362                       # DTB hits
+system.cpu0.itb.misses                          57977                       # DTB misses
+system.cpu0.itb.accesses                    224898339                       # DTB accesses
+system.cpu0.numCycles                       954325944                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  467223626                       # Number of instructions committed
-system.cpu0.committedOps                    548903732                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     48040966                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     5433                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 94067362325                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.314392                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.432079                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  417810947                       # Number of instructions committed
+system.cpu0.committedOps                    490605107                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     41344261                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     4694                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93809718025                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.284109                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.437807                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5510                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      755200178                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      326138353                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements          5943709                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          508.631098                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          162232873                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5944219                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.292546                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       7690193000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.631098                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.993420                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.993420                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        345517845                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       345517845                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     83485003                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       83485003                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     74196086                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      74196086                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       250296                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       250296                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       125849                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       125849                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1837182                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1837182                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1810329                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1810329                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    157681089                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       157681089                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    157931385                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      157931385                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3676950                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3676950                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2497111                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2497111                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       700297                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       700297                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       789920                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       789920                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       172643                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       172643                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       197460                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       197460                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      6174061                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6174061                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      6874358                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      6874358                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  65602264000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  65602264000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  59773944000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  59773944000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  75379073500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  75379073500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2981608500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2981608500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4714245500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4714245500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5404500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5404500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 125376208000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 125376208000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 125376208000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 125376208000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     87161953                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     87161953                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     76693197                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     76693197                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       950593                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       950593                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       915769                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       915769                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2009825                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2009825                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2007789                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2007789                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    163855150                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    163855150                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    164805743                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    164805743                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.042185                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.042185                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.032560                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.032560                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.736695                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.736695                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.862576                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.862576                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085900                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.085900                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098347                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098347                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037680                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.037680                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.041712                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.041712                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17841.489278                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17841.489278                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23937.239474                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23937.239474                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 95426.212148                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 95426.212148                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17270.370070                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17270.370070                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23874.432797                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23874.432797                       # average StoreCondReq miss latency
+system.cpu0.kern.inst.quiesce                    4756                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      674001287                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      280324657                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5190067                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          482.757722                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          144829115                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5190578                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.902310                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       7690769000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   482.757722                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.942886                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.942886                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        307937411                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       307937411                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     74836049                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       74836049                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     65744025                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      65744025                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       248898                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       248898                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       135683                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       135683                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1688860                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1688860                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1659238                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1659238                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    140580074                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       140580074                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    140828972                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      140828972                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3204136                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3204136                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2171939                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2171939                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       583430                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       583430                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       728874                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       728874                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       150550                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       150550                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       178568                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       178568                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      5376075                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5376075                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5959505                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5959505                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  51043675000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  51043675000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  55065851500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  55065851500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  67163849000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  67163849000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2254990500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2254990500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5008928500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5008928500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5076500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5076500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 106109526500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 106109526500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 106109526500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 106109526500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     78040185                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     78040185                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     67915964                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     67915964                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       832328                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       832328                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       864557                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       864557                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1839410                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1839410                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1837806                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1837806                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    145956149                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    145956149                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    146788477                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    146788477                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041058                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.041058                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.031980                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.031980                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.700962                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.700962                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.843061                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.843061                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.081847                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.081847                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.097164                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097164                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.036833                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.036833                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.040599                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.040599                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15930.558191                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15930.558191                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25353.314020                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25353.314020                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92147.406822                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92147.406822                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14978.349386                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14978.349386                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28050.538170                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28050.538170                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20306.927321                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20306.927321                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18238.242466                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18238.242466                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19737.359784                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19737.359784                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17805.090607                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17805.090607                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -691,161 +695,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3994886                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3994886                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       471328                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       471328                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1040644                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1040644                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           61                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total           61                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43748                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43748                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           50                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           50                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1511972                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1511972                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1511972                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1511972                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3205622                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3205622                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1456467                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1456467                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       694705                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       694705                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       789859                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       789859                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       128895                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       128895                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       197410                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       197410                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4662089                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4662089                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5356794                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5356794                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14687                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14687                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15563                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        15563                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30250                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        30250                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  51339121000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  51339121000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  33967610000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33967610000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  18528677500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  18528677500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  74583001500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  74583001500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1907396500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1907396500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4514361000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4514361000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5031000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5031000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  85306731000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  85306731000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103835408500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 103835408500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2448224000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2448224000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2535196500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2535196500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4983420500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4983420500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036778                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036778                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018991                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018991                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.730812                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.730812                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.862509                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.862509                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064132                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064132                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098322                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098322                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028453                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028453                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032504                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032504                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16015.338365                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16015.338365                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23321.922158                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23321.922158                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26671.288533                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26671.288533                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94425.715856                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94425.715856                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14798.064316                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14798.064316                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22867.944886                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22867.944886                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5190079                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5190079                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       389569                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       389569                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       893829                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       893829                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           64                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total           64                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        40085                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        40085                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           63                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           63                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1283398                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1283398                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1283398                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1283398                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2814567                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2814567                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1278110                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1278110                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       581694                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       581694                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       728810                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       728810                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       110465                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       110465                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       178505                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       178505                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4092677                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4092677                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4674371                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4674371                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16748                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16748                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18251                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18251                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34999                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34999                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  40095557000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40095557000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32063318500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  32063318500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14032843000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14032843000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  66427837000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  66427837000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1488538500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1488538500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4826102000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4826102000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      4518500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      4518500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  72158875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  72158875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  86191718500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  86191718500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3021431000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3021431000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3257996500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3257996500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6279427500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6279427500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036066                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036066                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018819                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018819                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.698876                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.698876                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.842987                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.842987                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060055                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060055                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.097129                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097129                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028040                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028040                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031844                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031844                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.728384                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14245.728384                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25086.509377                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25086.509377                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24124.097893                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.097893                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91145.616827                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91145.616827                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13475.204816                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13475.204816                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27036.228677                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27036.228677                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18297.962780                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18297.962780                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19383.871864                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19383.871864                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166693.266154                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166693.266154                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162898.959070                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162898.959070                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164741.173554                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 164741.173554                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17631.216805                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17631.216805                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18439.212142                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18439.212142                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180405.481251                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180405.481251                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178510.574763                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 178510.574763                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179417.340495                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179417.340495                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          9691826                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.890260                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          243455405                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          9692338                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            25.118336                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      41394292000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.890260                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999786                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999786                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          8911456                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.890744                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          215729294                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          8911968                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            24.206695                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      40343615000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.890744                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999787                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          168                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          330                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        515987824                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       515987824                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    243455405                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      243455405                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    243455405                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       243455405                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    243455405                       # number of overall hits
-system.cpu0.icache.overall_hits::total      243455405                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      9692338                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      9692338                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      9692338                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       9692338                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      9692338                       # number of overall misses
-system.cpu0.icache.overall_misses::total      9692338                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102847685000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 102847685000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 102847685000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 102847685000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 102847685000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 102847685000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    253147743                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    253147743                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    253147743                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    253147743                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    253147743                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    253147743                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.038287                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.038287                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.038287                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.038287                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.038287                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.038287                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10611.235906                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10611.235906                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10611.235906                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10611.235906                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10611.235906                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10611.235906                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        458194521                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       458194521                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    215729294                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      215729294                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    215729294                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       215729294                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    215729294                       # number of overall hits
+system.cpu0.icache.overall_hits::total      215729294                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      8911978                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      8911978                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      8911978                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       8911978                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      8911978                       # number of overall misses
+system.cpu0.icache.overall_misses::total      8911978                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  92482342000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  92482342000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  92482342000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  92482342000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  92482342000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  92482342000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    224641272                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    224641272                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    224641272                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    224641272                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    224641272                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    224641272                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039672                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.039672                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039672                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.039672                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039672                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.039672                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10377.308158                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10377.308158                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10377.308158                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10377.308158                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10377.308158                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10377.308158                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -854,506 +858,499 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      9692338                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      9692338                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      9692338                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      9692338                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      9692338                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      9692338                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      8911456                       # number of writebacks
+system.cpu0.icache.writebacks::total          8911456                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8911978                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      8911978                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      8911978                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      8911978                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      8911978                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      8911978                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  98001516000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  98001516000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  98001516000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  98001516000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  98001516000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  98001516000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   7413401000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   7413401000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   7413401000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   7413401000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.038287                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.038287                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.038287                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.038287                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.038287                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.038287                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10111.235906                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10111.235906                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10111.235906                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10111.235906                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10111.235906                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10111.235906                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  88026353500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  88026353500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  88026353500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  88026353500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  88026353500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  88026353500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   7414627000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   7414627000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   7414627000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   7414627000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039672                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039672                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039672                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.039672                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039672                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.039672                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9877.308214                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9877.308214                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9877.308214                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9877.308214                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9877.308214                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9877.308214                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7930582                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7930908                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit          287                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7009428                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7009488                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           54                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1050332                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2927796                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16250.045097                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          27328553                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2943246                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            9.285175                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     38485430000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  6649.492221                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    85.492855                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    83.778044                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4952.378154                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3516.424447                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   962.479377                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.405853                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.005218                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005113                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.302269                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.214626                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.058745                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.991824                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1206                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           86                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14158                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          186                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          762                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          258                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           60                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4796                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6589                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2552                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.073608                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005249                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.864136                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       526684633                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      526684633                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       557343                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       169839                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        727182                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3994885                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3994885                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       109927                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       109927                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36134                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        36134                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       948378                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       948378                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8870174                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      8870174                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2952679                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2952679                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       197136                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       197136                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       557343                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       169839                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      8870174                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3901057                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       13498413                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       557343                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       169839                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      8870174                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3901057                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      13498413                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12614                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8790                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        21404                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       135802                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       135802                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       161268                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       161268                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       273569                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       273569                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       822163                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       822163                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1076215                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1076215                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       591539                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       591539                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12614                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8790                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       822163                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1349784                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2193351                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12614                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8790                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       822163                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1349784                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2193351                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    603588000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    473780500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   1077368500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   4108799000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   4108799000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3792069500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3792069500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4938499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4938499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  19118794000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  19118794000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  30594179000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  30594179000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  46332518496                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  46332518496                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  71985941000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  71985941000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    603588000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    473780500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  30594179000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  65451312496                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  97122859996                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    603588000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    473780500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  30594179000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  65451312496                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  97122859996                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       569957                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       178629                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       748586                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      3994886                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      3994886                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       245729                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       245729                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       197402                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       197402                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1221947                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1221947                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      9692337                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      9692337                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4028894                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      4028894                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       788675                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       788675                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       569957                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       178629                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      9692337                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5250841                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     15691764                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       569957                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       178629                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      9692337                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5250841                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     15691764                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022131                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.049208                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.028593                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.552649                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.552649                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.816952                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.816952                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.prefetcher.pfSpanPage       921168                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2475518                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16200.233462                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          22065601                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2491662                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            8.855776                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      9049945000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15248.600129                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    44.173698                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    44.219033                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   863.240603                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.930701                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002696                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.002699                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.052688                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.988784                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1264                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           48                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14832                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          796                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          176                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          279                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           32                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1045                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5479                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6042                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2161                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.077148                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.002930                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.905273                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       474836128                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      474836128                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       472021                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       147981                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        620002                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3408595                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3408595                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks     10690717                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total     10690717                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          115                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total          115                       # number of UpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       789207                       # number of ReadExReq hits
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+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8250320                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      8250320                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2605662                       # number of ReadSharedReq hits
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+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       165539                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       165539                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       472021                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       147981                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      8250320                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3394869                       # number of demand (read+write) hits
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+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       472021                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       147981                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      8250320                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3394869                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      12265191                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10450                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7208                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        17658                       # number of ReadReq misses
+system.cpu0.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
+system.cpu0.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       242851                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       242851                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       178501                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       178501                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       254335                       # number of ReadExReq misses
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+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       661657                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       661657                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       900762                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       900762                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       561341                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       561341                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10450                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7208                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       661657                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1155097                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      1834412                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10450                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7208                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       661657                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1155097                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1834412                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    323189500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    243712500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    566902000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3278340000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   3278340000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1776981500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1776981500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4439499                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4439499                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  15942119997                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  15942119997                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  24805875000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  24805875000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  33147375490                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  33147375490                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  64101878000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  64101878000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    323189500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    243712500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  24805875000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  49089495487                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  74462272487                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    323189500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    243712500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  24805875000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  49089495487                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  74462272487                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       482471                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       155189                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       637660                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3408595                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      3408595                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks     10690718                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total     10690718                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       242966                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       242966                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       178501                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       178501                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1043542                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1043542                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      8911977                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      8911977                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3506424                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3506424                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       726880                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       726880                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       482471                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       155189                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      8911977                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      4549966                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     14099603                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       482471                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       155189                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      8911977                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      4549966                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     14099603                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021659                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.046447                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.027692                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
+system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999527                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999527                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.223880                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.223880                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.084826                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.084826                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.267124                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.267124                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.750042                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.750042                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022131                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.049208                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.084826                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.257061                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.139777                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022131                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.049208                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.084826                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.257061                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.139777                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47850.642144                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 53899.943117                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 50334.914035                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 30255.806247                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 30255.806247                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23514.085249                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23514.085249                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 617312.375000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 617312.375000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69886.551473                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69886.551473                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37211.816878                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37211.816878                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 43051.359158                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 43051.359158                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 121692.637341                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 121692.637341                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47850.642144                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 53899.943117                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37211.816878                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48490.212135                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 44280.582541                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47850.642144                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 53899.943117                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37211.816878                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48490.212135                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 44280.582541                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          189                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.243723                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.243723                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.074244                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.074244                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.256889                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.256889                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.772261                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.772261                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021659                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.046447                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.074244                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.253869                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.130104                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021659                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.046447                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.074244                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.253869                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.130104                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30927.224880                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33811.390122                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32104.541851                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13499.388514                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13499.388514                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9955.022661                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9955.022661                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1109874.750000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1109874.750000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62681.581367                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62681.581367                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37490.535126                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37490.535126                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36799.260504                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36799.260504                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114194.184996                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114194.184996                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30927.224880                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33811.390122                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37490.535126                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42498.158585                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 40591.902194                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30927.224880                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33811.390122                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37490.535126                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42498.158585                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 40591.902194                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          189                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1489447                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1489447                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.writebacks::writebacks      1435569                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1435569                       # number of writebacks
 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         9633                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         9633                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            6                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         1299                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         1299                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         4123                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         4123                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            7                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          932                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          932                       # number of ReadSharedReq MSHR hits
 system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker            2                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            6                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        10932                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        10941                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            7                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5055                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         5064                       # number of demand (read+write) MSHR hits
 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            6                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        10932                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        10941                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12613                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8788                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        21401                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       120619                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total       120619                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       765315                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       765315                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       135802                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       135802                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       161268                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       161268                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       263936                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       263936                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       822157                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       822157                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1074916                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1074916                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       591539                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       591539                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12613                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8788                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       822157                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1338852                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2182410                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12613                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8788                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       822157                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1338852                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       765315                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2947725                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            7                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5055                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         5064                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10450                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7206                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        17656                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            1                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::total            1                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       688849                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       688849                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       242851                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       242851                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       178501                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       178501                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       250212                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total       250212                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       661650                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       661650                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       899830                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       899830                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       561341                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       561341                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10450                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7206                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       661650                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1150042                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total      1829348                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10450                       # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       661650                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1150042                       # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total      2518197                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        14687                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        66996                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        15563                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        15563                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        16748                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        69057                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18251                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18251                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        30250                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        82559                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    527895500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    421006000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    948901500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  53668708822                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  53668708822                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4760934499                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4760934499                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3014472000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3014472000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4572499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4572499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16016983500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16016983500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  25660880000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  25660880000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  39766543496                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  39766543496                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  68436707000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  68436707000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    527895500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    421006000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  25660880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  55783526996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  82393308496                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    527895500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    421006000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  25660880000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  55783526996                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  53668708822                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 136062017318                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6994929000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2330678000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9325607000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2418455500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2418455500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   6994929000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4749133500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11744062500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022130                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.049197                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.028589                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        34999                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        87308                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    260489500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    200447500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    460937000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  28313104052                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  28313104052                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7480349995                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7480349995                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3483043000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3483043000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4127499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4127499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  13883735997                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  13883735997                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  20835719500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  20835719500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  27673983990                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  27673983990                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  60733832000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  60733832000                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    260489500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    200447500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  20835719500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  41557719987                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  62854376487                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    260489500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    200447500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  20835719500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  41557719987                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  28313104052                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  91167480539                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2887260500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9883415500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3121073500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3121073500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6008334000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  13004489000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021659                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.046434                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027689                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
+system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.552649                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.552649                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.816952                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.816952                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999527                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999527                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.215996                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.215996                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.084825                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.084825                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.266802                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.266802                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.750042                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.750042                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022130                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.049197                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.084825                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.254979                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.139080                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022130                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.049197                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.084825                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.254979                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.239772                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.239772                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.074243                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.074243                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.256623                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.256623                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.772261                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.772261                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021659                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.046434                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.074243                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.252758                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.129745                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021659                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.046434                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.074243                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.252758                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.187852                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44339.119667                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 70126.299396                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35057.911511                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35057.911511                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18692.313416                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18692.313416                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 571562.375000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 571562.375000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60685.103586                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.103586                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31211.654222                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31211.654222                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36995.024259                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36995.024259                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 115692.637341                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 115692.637341                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31211.654222                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41665.193013                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37753.359129                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31211.654222                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41665.193013                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46158.314401                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158689.861783                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139196.474416                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155397.770353                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155397.770353                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 156996.148760                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142250.542037                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.178601                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26106.536022                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41102.047113                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30802.220271                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30802.220271                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19512.736623                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19512.736623                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1031874.750000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031874.750000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55487.890257                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.890257                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31490.545606                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31490.545606                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30754.680317                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30754.680317                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108194.184996                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108194.184996                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31490.545606                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36135.828071                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34358.895348                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31490.545606                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36135.828071                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36203.474366                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172394.345594                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143119.676499                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171008.355707                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171008.355707                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171671.590617                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 148949.569341                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     32152230                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     16420555                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2260                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       569005                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       568969                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           36                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        939547                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     14756064                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        15563                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        15563                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      5525670                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict     13869690                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1023479                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       455350                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       356742                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       509038                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           63                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1302016                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1231079                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      9692338                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5147566                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       792720                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       788675                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     29179671                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19139148                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       387023                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1234112                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         49939954                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    623657344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    598500446                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1429032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4559656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1228146478                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    6651761                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     39123003                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.023394                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.151159                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests     29004574                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     14815953                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2223                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      1990994                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1990568                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          426                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        781840                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     13286786                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        18251                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        18251                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      4847792                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean     10690718                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2645908                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       891756                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       444613                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       320296                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       480335                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           85                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1119465                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1052013                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      8911978                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4503059                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       735449                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       726880                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     26838850                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     16809682                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       328338                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1022103                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         44998973                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1143972032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    629474552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1241512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3859768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1778547864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    6630650                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     21811897                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.104823                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.306390                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          38207781     97.66%     97.66% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            915186      2.34%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2                36      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          19525925     89.52%     89.52% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2285546     10.48%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               426      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      39123003                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   20385491499                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    189810874                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      21811897                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   28866629481                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    172367004                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  14619906616                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  13449935466                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8517245437                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7428549534                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    208413461                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    173196405                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    664225858                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    539756748                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              135994038                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         97681271                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5923294                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups           101767942                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               74881085                       # Number of BTB hits
+system.cpu1.branchPred.lookups              127068265                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89752795                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6099791                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            94409743                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               68319168                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            73.580229                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               15572056                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect           1048784                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            72.364531                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               15069899                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            999135                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1383,62 +1380,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   278179                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               278179                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9856                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        80934                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       278179                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         278179    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       278179                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        90790                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 21983.114880                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 19433.562361                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 21494.492882                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        89574     98.66%     98.66% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          162      0.18%     98.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          899      0.99%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           22      0.02%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           47      0.05%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           21      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           36      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        90790                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   1613488760                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1613488760    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1613488760                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        80934     89.14%     89.14% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         9856     10.86%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        90790                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       278179                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   271482                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               271482                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         7964                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        78105                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       271482                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         271482    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       271482                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        86069                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 22755.010515                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21243.396519                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15660.005020                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        85331     99.14%     99.14% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          168      0.20%     99.34% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          495      0.58%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           14      0.02%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           20      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           15      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           22      0.03%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        86069                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples    527505760                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0      527505760    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total    527505760                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        78105     90.75%     90.75% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         7964      9.25%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        86069                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       271482                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       278179                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        90790                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       271482                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        86069                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        90790                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       368969                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        86069                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       357551                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    86408994                       # DTB read hits
-system.cpu1.dtb.read_misses                    229031                       # DTB read misses
-system.cpu1.dtb.write_hits                   76265809                       # DTB write hits
-system.cpu1.dtb.write_misses                    49148                       # DTB write misses
+system.cpu1.dtb.read_hits                    82675138                       # DTB read hits
+system.cpu1.dtb.read_misses                    225741                       # DTB read misses
+system.cpu1.dtb.write_hits                   73180273                       # DTB write hits
+system.cpu1.dtb.write_misses                    45741                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              43397                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   36480                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1565                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  7972                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              37374                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1001                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   37272                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1666                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8268                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11612                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                86638025                       # DTB read accesses
-system.cpu1.dtb.write_accesses               76314957                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11369                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                82900879                       # DTB read accesses
+system.cpu1.dtb.write_accesses               73226014                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        162674803                       # DTB hits
-system.cpu1.dtb.misses                         278179                       # DTB misses
-system.cpu1.dtb.accesses                    162952982                       # DTB accesses
+system.cpu1.dtb.hits                        155855411                       # DTB hits
+system.cpu1.dtb.misses                         271482                       # DTB misses
+system.cpu1.dtb.accesses                    156126893                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1468,189 +1465,186 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    61280                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                61280                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          546                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        52744                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        61280                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          61280    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        61280                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        53290                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 25110.649278                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 21594.032296                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 25562.060343                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        52075     97.72%     97.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071            7      0.01%     97.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607         1075      2.02%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           37      0.07%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           53      0.10%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           27      0.05%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           12      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    69604                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                69604                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          666                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        61994                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        69604                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          69604    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        69604                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        62660                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 25321.249601                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23483.555874                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 17582.582178                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        61881     98.76%     98.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071           12      0.02%     98.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          712      1.14%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           23      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           20      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        53290                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1612594260                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1612594260    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1612594260                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        52744     98.98%     98.98% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          546      1.02%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        53290                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total        62660                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples    526611260                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0      526611260    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total    526611260                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        61994     98.94%     98.94% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          666      1.06%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        62660                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        61280                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        61280                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        69604                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        69604                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        53290                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        53290                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       114570                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   242169117                       # ITB inst hits
-system.cpu1.itb.inst_misses                     61280                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        62660                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        62660                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       132264                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   226404999                       # ITB inst hits
+system.cpu1.itb.inst_misses                     69604                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              43397                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1058                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   25722                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              37374                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1001                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   26762                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   205735                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   203402                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               242230397                       # ITB inst accesses
-system.cpu1.itb.hits                        242169117                       # DTB hits
-system.cpu1.itb.misses                          61280                       # DTB misses
-system.cpu1.itb.accesses                    242230397                       # DTB accesses
-system.cpu1.numCycles                       953928196                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               226474603                       # ITB inst accesses
+system.cpu1.itb.hits                        226404999                       # DTB hits
+system.cpu1.itb.misses                          69604                       # DTB misses
+system.cpu1.itb.accesses                    226474603                       # DTB accesses
+system.cpu1.numCycles                       896249910                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  443058406                       # Number of instructions committed
-system.cpu1.committedOps                    521637964                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     48259182                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     4720                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 94194636881                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.153053                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.464457                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  420934522                       # Number of instructions committed
+system.cpu1.committedOps                    495850522                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     42911431                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     4588                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 93867828238                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.129191                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.469662                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13665                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      720990302                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      232937894                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements          5271409                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          430.049497                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          154587010                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5271921                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.322710                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8389845325000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   430.049497                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.839940                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.839940                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                   13511                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      680922299                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      215327611                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          4921419                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          458.899025                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          148299852                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          4921931                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            30.130421                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8388824602000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   458.899025                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.896287                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.896287                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          399                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           38                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        327906694                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       327906694                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     79069141                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       79069141                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     70951579                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      70951579                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       254478                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       254478                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       200049                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       200049                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1835496                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1835496                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1797284                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1797284                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    150020720                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       150020720                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    150275198                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      150275198                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3348164                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3348164                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      2321727                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2321727                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       675333                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       675333                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       453842                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       453842                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       163069                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       163069                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       199393                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       199393                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5669891                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5669891                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      6345224                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      6345224                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  55281073500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  55281073500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  48428743000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  48428743000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20617335000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  20617335000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2629405000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2629405000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4686368500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4686368500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      4186500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      4186500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 103709816500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 103709816500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 103709816500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 103709816500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     82417305                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     82417305                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     73273306                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     73273306                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       929811                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       929811                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       653891                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       653891                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1998565                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1998565                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1996677                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1996677                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    155690611                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    155690611                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    156620422                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    156620422                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.040625                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.040625                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.031686                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.031686                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.726312                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.726312                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.694064                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.694064                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081593                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.081593                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.099862                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.099862                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.036418                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.036418                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.040513                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.040513                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16510.861923                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16510.861923                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.930873                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.930873                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45428.442057                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45428.442057                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16124.493313                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16124.493313                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23503.174635                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23503.174635                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        313981831                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       313981831                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     76035057                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       76035057                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     68321160                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      68321160                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       232478                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       232478                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       184182                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       184182                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1549703                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1549703                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1524262                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1524262                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    144356217                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       144356217                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    144588695                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      144588695                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3124160                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3124160                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2104338                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2104338                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       561771                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       561771                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       510720                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       510720                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       156544                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       156544                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       180437                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       180437                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5228498                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5228498                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5790269                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5790269                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  48221817000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  48221817000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  44559226500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  44559226500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  19302885000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  19302885000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2427765500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2427765500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5104015500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5104015500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      7589000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      7589000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  92781043500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  92781043500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  92781043500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  92781043500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     79159217                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     79159217                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     70425498                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     70425498                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       794249                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       794249                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       694902                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       694902                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1706247                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1706247                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1704699                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1704699                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    149584715                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    149584715                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    150378964                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    150378964                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039467                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.039467                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029880                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.029880                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.707298                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.707298                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.734953                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.734953                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.091748                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.091748                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105847                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105847                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034953                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.034953                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.038505                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.038505                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15435.130403                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15435.130403                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21174.937914                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21174.937914                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37795.435855                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37795.435855                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15508.518372                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15508.518372                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28286.967196                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28286.967196                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18291.324560                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18291.324560                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16344.547726                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16344.547726                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17745.257529                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17745.257529                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16023.615397                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16023.615397                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1659,161 +1653,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3447609                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3447609                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       379178                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       379178                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       964484                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       964484                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           92                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total           92                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        41281                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        41281                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           68                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           68                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1343662                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1343662                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1343662                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1343662                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2968986                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2968986                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1357243                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1357243                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       675071                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       675071                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       453750                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       453750                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       121788                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       121788                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       199325                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       199325                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4326229                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4326229                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5001300                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5001300                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        23522                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        23522                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        22517                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        22517                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        46039                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        46039                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  44110385000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  44110385000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  27847514500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  27847514500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16178845000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16178845000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  20154706000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  20154706000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1764852000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1764852000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4482506000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4482506000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3997500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3997500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  71957899500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  71957899500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  88136744500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  88136744500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4055697500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4055697500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3925636000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3925636000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7981333500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7981333500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036024                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036024                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018523                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018523                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.726030                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.726030                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.693923                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.693923                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060938                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060938                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.099828                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.099828                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027787                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027787                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031933                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031933                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14857.053890                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14857.053890                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20517.707220                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20517.707220                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23966.138377                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23966.138377                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44418.084848                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44418.084848                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14491.181397                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14491.181397                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22488.428446                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22488.428446                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      4921438                       # number of writebacks
+system.cpu1.dcache.writebacks::total          4921438                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       336855                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       336855                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       865157                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       865157                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           99                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total           99                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        39963                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        39963                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           44                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           44                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1202012                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1202012                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1202012                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1202012                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2787305                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2787305                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1239181                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1239181                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       561309                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       561309                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       510621                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       510621                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116581                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116581                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       180393                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       180393                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4026486                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4026486                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4587795                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4587795                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        20902                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        20902                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        19312                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        19312                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        40214                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        40214                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38841507500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38841507500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26434060500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26434060500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12644921000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12644921000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  18783135000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  18783135000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1568875000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1568875000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4920605000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4920605000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      7128000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      7128000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  65275568000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  65275568000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  77920489000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  77920489000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3868216000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3868216000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3618681000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3618681000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7486897000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7486897000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035211                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035211                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017596                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017596                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.706717                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.706717                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.734810                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.734810                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.068326                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068326                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105821                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105821                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026918                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026918                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030508                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.030508                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13935.147930                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13935.147930                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21331.880089                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21331.880089                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22527.557905                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22527.557905                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36784.885463                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36784.885463                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13457.381563                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13457.381563                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27277.139357                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27277.139357                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16632.938178                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16632.938178                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17622.766981                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17622.766981                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172421.456509                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172421.456509                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174340.986810                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174340.986810                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173360.270640                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173360.270640                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16211.547240                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16211.547240                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16984.300519                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16984.300519                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185064.395752                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185064.395752                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187379.919221                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187379.919221                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186176.381360                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186176.381360                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          9020173                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          506.865133                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          232936753                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          9020685                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            25.822513                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8389731746000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.865133                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.989971                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.989971                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          9409188                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          506.684863                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          216784534                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          9409700                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            23.038411                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8388652871500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.684863                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.989619                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.989619                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          281                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        492935590                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       492935590                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    232936753                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      232936753                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    232936753                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       232936753                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    232936753                       # number of overall hits
-system.cpu1.icache.overall_hits::total      232936753                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      9020695                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      9020695                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      9020695                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       9020695                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      9020695                       # number of overall misses
-system.cpu1.icache.overall_misses::total      9020695                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  95573427500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  95573427500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  95573427500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  95573427500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  95573427500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  95573427500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    241957448                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    241957448                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    241957448                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    241957448                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    241957448                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    241957448                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.037282                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.037282                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.037282                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.037282                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.037282                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.037282                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10594.907321                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10594.907321                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10594.907321                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10594.907321                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10594.907321                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10594.907321                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        461798168                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       461798168                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    216784534                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      216784534                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    216784534                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       216784534                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    216784534                       # number of overall hits
+system.cpu1.icache.overall_hits::total      216784534                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      9409700                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      9409700                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      9409700                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       9409700                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      9409700                       # number of overall misses
+system.cpu1.icache.overall_misses::total      9409700                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  95979801000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  95979801000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  95979801000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  95979801000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  95979801000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  95979801000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    226194234                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    226194234                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    226194234                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    226194234                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    226194234                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    226194234                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.041600                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.041600                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.041600                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.041600                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.041600                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.041600                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10200.091501                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10200.091501                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10200.091501                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10200.091501                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10200.091501                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10200.091501                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1822,257 +1816,254 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9020695                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      9020695                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      9020695                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      9020695                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      9020695                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      9020695                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      9409188                       # number of writebacks
+system.cpu1.icache.writebacks::total          9409188                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9409700                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      9409700                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      9409700                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      9409700                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      9409700                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      9409700                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           92                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           92                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           92                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           92                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  91063080500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  91063080500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  91063080500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  91063080500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  91063080500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  91063080500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12520000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     12520000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     12520000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     12520000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.037282                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.037282                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.037282                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.037282                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.037282                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.037282                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10094.907377                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10094.907377                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10094.907377                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10094.907377                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10094.907377                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10094.907377                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  91274951000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  91274951000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  91274951000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  91274951000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  91274951000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  91274951000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12950500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     12950500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     12950500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     12950500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.041600                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.041600                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.041600                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.041600                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.041600                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.041600                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9700.091501                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9700.091501                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9700.091501                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9700.091501                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9700.091501                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9700.091501                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7367099                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7368207                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6599308                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6600409                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit          970                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       915185                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2451047                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13486.856931                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          25401363                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2467204                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           10.295607                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9750772511500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5534.671535                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    72.865878                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    75.759865                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3715.594887                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3131.532678                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   956.432088                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.337810                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004447                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004624                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.226782                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.191134                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.058376                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.823172                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1547                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           59                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14551                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           27                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          141                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          670                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          709                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           15                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1114                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2381                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4908                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         6029                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.094421                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003601                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.888123                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       480485557                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      480485557                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       478608                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       141054                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        619662                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3447607                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3447607                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        76833                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        76833                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        38108                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        38108                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       900678                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       900678                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8234691                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      8234691                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2752869                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2752869                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       182879                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       182879                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       478608                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       141054                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      8234691                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3653547                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       12507900                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       478608                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       141054                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      8234691                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3653547                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      12507900                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12194                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8418                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        20612                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       132767                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       132767                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       161216                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       161216                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       249202                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       249202                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       786004                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       786004                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1012720                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total      1012720                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       269177                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       269177                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12194                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8418                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       786004                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1261922                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2068538                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12194                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8418                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       786004                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1261922                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2068538                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    602053500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    457478000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   1059531500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   4022613999                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   4022613999                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3766406500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3766406500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3914500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3914500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  14165693998                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  14165693998                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  28461637500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  28461637500                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  38316841993                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  38316841993                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  18196585000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  18196585000                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    602053500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    457478000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  28461637500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  52482535991                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  82003704991                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    602053500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    457478000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  28461637500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  52482535991                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  82003704991                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       490802                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149472                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       640274                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3447608                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3447608                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       209600                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       209600                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       199324                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       199324                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1149880                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1149880                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9020695                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      9020695                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3765589                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3765589                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       452056                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       452056                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       490802                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149472                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      9020695                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4915469                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     14576438                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       490802                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149472                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      9020695                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4915469                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     14576438                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.024845                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.056318                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.032192                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.633430                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.633430                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.808814                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.808814                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       793623                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2151198                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13377.061252                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          23203065                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2166951                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           10.707702                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9986150274500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.259690                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.377906                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    74.184237                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   713.239419                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.764359                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004051                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004528                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.043533                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.816471                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          985                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023          109                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14659                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          173                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          750                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           51                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           59                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           46                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1249                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4750                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8044                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          438                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.060120                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006653                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.894714                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       482635734                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      482635734                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       517404                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       182303                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        699707                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3095740                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3095740                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks     11232116                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total     11232116                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          197                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total          197                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       799662                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       799662                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      8718417                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      8718417                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2602566                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      2602566                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       242267                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       242267                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       517404                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       182303                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      8718417                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3402228                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       12820352                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       517404                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       182303                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      8718417                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3402228                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      12820352                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        10447                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7725                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        18172                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       203082                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       203082                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       180388                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       180388                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       239405                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       239405                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       691283                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       691283                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       862205                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       862205                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       266022                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       266022                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        10447                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7725                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       691283                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1101610                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1811065                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        10447                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7725                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       691283                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1101610                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1811065                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    361003500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    296858500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    657862000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3343793000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   3343793000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1815465000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1815465000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      7003999                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      7003999                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  11577465998                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  11577465998                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  24488845500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  24488845500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  30668978480                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  30668978480                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  16284255500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  16284255500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    361003500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    296858500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  24488845500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  42246444478                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  67393151978                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    361003500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    296858500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  24488845500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  42246444478                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  67393151978                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       527851                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       190028                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       717879                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3095740                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3095740                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks     11232116                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total     11232116                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       203279                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       203279                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       180388                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       180388                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1039067                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1039067                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9409700                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      9409700                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3464771                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3464771                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       508289                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       508289                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       527851                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       190028                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      9409700                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4503838                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     14631417                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       527851                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       190028                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      9409700                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4503838                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     14631417                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.019792                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.040652                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.025313                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999031                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999031                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.216720                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.216720                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.087133                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.087133                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.268941                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.268941                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.595451                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.595451                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.024845                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.056318                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.087133                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.256725                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.141910                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.024845                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.056318                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.087133                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.256725                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.141910                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 49372.929309                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 54345.212640                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 51403.624102                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30298.297009                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30298.297009                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23362.485733                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23362.485733                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      3914500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      3914500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 56844.222751                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 56844.222751                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36210.550455                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36210.550455                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37835.573498                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37835.573498                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 67600.816563                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 67600.816563                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 49372.929309                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 54345.212640                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36210.550455                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 41589.366055                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 39643.315709                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 49372.929309                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 54345.212640                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36210.550455                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 41589.366055                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 39643.315709                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.230404                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.230404                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.073465                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.073465                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.248849                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.248849                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.523368                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.523368                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.019792                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.040652                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.073465                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.244594                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.123779                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.019792                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.040652                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.073465                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.244594                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.123779                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 34555.709773                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38428.284790                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36201.959058                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16465.235718                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16465.235718                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10064.222676                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10064.222676                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1400799.800000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1400799.800000                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48359.332503                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48359.332503                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35425.210080                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35425.210080                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35570.402027                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35570.402027                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 61213.942832                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 61213.942832                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 34555.709773                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38428.284790                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35425.210080                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38349.728559                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 37211.890229                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 34555.709773                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38428.284790                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35425.210080                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38349.728559                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 37211.890229                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2081,243 +2072,235 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1067557                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1067557                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks      1042577                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1042577                       # number of writebacks
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
 system.cpu1.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         9451                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         9451                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            6                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         1057                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         1057                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            5                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            5                       # number of InvalidateReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         4272                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         4272                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            7                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         1142                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         1142                       # number of ReadSharedReq MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            6                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        10508                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total        10515                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            7                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         5414                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         5422                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            6                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data        10508                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total        10515                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12194                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8417                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        20611                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       115832                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total       115832                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       735652                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       735652                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       132767                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       132767                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       161216                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       161216                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       239751                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       239751                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       785998                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       785998                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data      1011663                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total      1011663                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       269172                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       269172                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12194                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8417                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       785998                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1251414                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      2058023                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12194                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8417                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       785998                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1251414                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       735652                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2793675                       # number of overall MSHR misses
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+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10447                       # number of ReadReq MSHR misses
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+system.cpu1.l2cache.ReadReq_mshr_misses::total        18171                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       679285                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       679285                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       203082                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       203082                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       180388                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       180388                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       691276                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       691276                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       861063                       # number of ReadSharedReq MSHR misses
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+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       266022                       # number of InvalidateReq MSHR misses
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+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1096196                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2484928                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           92                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        23522                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        23614                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        22517                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        22517                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        20902                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        20994                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        19312                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        19312                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           92                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        46039                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        46131                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    528889500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    406963000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    935852500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  46172311210                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  46172311210                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4497693492                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4497693492                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2967096500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2967096500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3584500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3584500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  11268741998                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  11268741998                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  23745516000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  23745516000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  32172501493                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  32172501493                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  16580751000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16580751000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    528889500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    406963000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  23745516000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  43441243491                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  68122611991                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    528889500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    406963000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  23745516000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  43441243491                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  46172311210                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 114294923201                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     11784000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3867463500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3879247500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3756742500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3756742500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     11784000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7624206000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7635990000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.024845                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.056312                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.032191                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        40214                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        40306                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    298321500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    250498000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    548819500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  24534893187                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  24534893187                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6599396497                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6599396497                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3563733500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3563733500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      6517999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      6517999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   9585687998                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   9585687998                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20341013500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20341013500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25423220980                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25423220980                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  14688123500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  14688123500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    298321500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    250498000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20341013500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  35008908978                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  55898741978                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    298321500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    250498000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20341013500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  35008908978                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  24534893187                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  80433635165                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12214500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3700892500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3713107000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3473788500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3473788500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12214500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7174681000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7186895500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.019792                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.040647                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025312                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.633430                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.633430                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.808814                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808814                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999031                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999031                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.208501                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.208501                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.087133                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.087133                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.268660                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.268660                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.595440                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.595440                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.024845                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.056312                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.087133                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.254587                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.141188                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.024845                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.056312                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.087133                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.254587                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.226292                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.226292                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.073464                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.073464                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.248519                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248519                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.523368                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.523368                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.019792                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.040647                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.073464                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.243392                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.123409                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.019792                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.040647                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.073464                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.243392                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.191657                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45405.487361                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62763.794851                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33876.592015                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33876.592015                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18404.479084                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18404.479084                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      3584500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      3584500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47001.856084                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47001.856084                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30210.657025                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30210.657025                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31801.599439                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31801.599439                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61599.092773                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61599.092773                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30210.657025                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34713.726625                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33100.996437                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30210.657025                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34713.726625                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40912.032789                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164418.990732                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164277.441348                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166840.276236                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166840.276236                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165603.205978                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165528.386551                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.169835                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30203.043311                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36118.703029                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32496.215800                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32496.215800                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19755.934430                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19755.934430                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1303599.800000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1303599.800000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 40767.089256                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 40767.089256                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29425.314202                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29425.314202                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29525.390105                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29525.390105                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55213.942832                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55213.942832                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29425.314202                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31936.723887                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30957.803939                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29425.314202                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31936.723887                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32368.597869                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177059.252703                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176865.151948                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179877.200704                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179877.200704                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178412.518029                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178308.328785                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     29416501                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15028447                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         2391                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       554511                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       554502                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            9                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        803941                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     13684916                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        22517                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        22517                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      4553047                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict     13043260                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       982334                       # Transaction distribution
+system.cpu1.toL2Bus.snoop_filter.tot_requests     29428527                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15006964                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         2768                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      1972954                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1972589                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          365                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq        814249                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     13775310                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        19312                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        19312                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4142105                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean     11232116                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2703238                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       874176                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       414162                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       358438                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       473685                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           62                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1229561                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1158646                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9020695                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4893253                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       460729                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       452056                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     27060072                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17084009                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332493                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1088108                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         45564682                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    577330304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    542008212                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1195776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3926416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1124460708                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    6177589                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     35784390                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.024790                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.155485                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       401941                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       322763                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       444037                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           57                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1114947                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1047219                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9409700                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4456605                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       514166                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       508289                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     28226960                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15947748                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       397923                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1113211                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         45685842                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1204298752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    609360975                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1520224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4222808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1819402759                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    6269077                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     21677519                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.104647                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.306153                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          34897315     97.52%     97.52% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            887066      2.48%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2                 9      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          19409393     89.54%     89.54% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2267761     10.46%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               365      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      35784390                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   18416469994                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    187934075                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      21677519                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   29325134974                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    172530424                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  13533732383                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  14118247362                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7841048470                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7236066136                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    183047447                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    207955878                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    597345920                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    585496227                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40341                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40341                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136603                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136603                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47670                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40404                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40404                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136972                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136972                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47770                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2327,18 +2310,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122552                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231256                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231256                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122912                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231760                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231760                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353888                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47690                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354752                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47790                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2348,797 +2331,798 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155682                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339040                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7339040                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155927                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355392                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7355392                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496808                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36193000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7513405                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             47202500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               15500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25874502                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              168500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            36406501                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              123500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           566159223                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           566812397                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92680000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92927000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147952000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           148200000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115609                       # number of replacements
-system.iocache.tags.tagsinuse               11.261931                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115625                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9146785142000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.823570                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.438361                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.238973                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.464898                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.703871                       # Average percentage of cache occupancy
+system.iocache.tags.replacements               115872                       # number of replacements
+system.iocache.tags.tagsinuse               11.264501                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      6                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs               115888                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000052                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         9145998133000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.414921                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.849581                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.463433                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.240599                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.704031                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1041009                       # Number of tag accesses
-system.iocache.tags.data_accesses             1041009                       # Number of data accesses
+system.iocache.tags.tag_accesses              1043272                       # Number of tag accesses
+system.iocache.tags.data_accesses             1043272                       # Number of data accesses
+system.iocache.WriteLineReq_hits::realview.ide            2                       # number of WriteLineReq hits
+system.iocache.WriteLineReq_hits::total             2                       # number of WriteLineReq hits
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8900                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8937                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8896                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8933                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106982                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106982                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8900                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8940                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8896                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8936                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8900                       # number of overall misses
-system.iocache.overall_misses::total             8940                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1696302972                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1701497972                       # number of ReadReq miss cycles
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 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13913628251                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13913628251                       # number of WriteLineReq miss cycles
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-system.iocache.demand_miss_latency::realview.ide   1696302972                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1701866972                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1696302972                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1701866972                       # number of overall miss cycles
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+system.iocache.WriteLineReq_miss_latency::total  14013428406                       # number of WriteLineReq miss cycles
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+system.iocache.overall_miss_latency::realview.ide   1700094991                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1705724991                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8900                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8937                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8900                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8940                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8896                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8900                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8940                       # number of overall (read+write) accesses
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+system.iocache.overall_accesses::total           8936                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide     0.999981                       # miss rate for WriteLineReq accesses
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 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
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 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 190595.839551                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 190388.046548                       # average ReadReq miss latency
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+system.iocache.ReadReq_avg_miss_latency::realview.ide 191107.800247                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 190905.182022                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130365.304803                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130365.304803                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 190595.839551                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 190365.433110                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 190595.839551                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 190365.433110                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34247                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130988.656092                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130988.656092                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       140750                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 191107.800247                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 190882.384848                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       140750                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 191107.800247                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 190882.384848                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         36149                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3593                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3721                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.531589                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.714862                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106694                       # number of writebacks
-system.iocache.writebacks::total               106694                       # number of writebacks
+system.iocache.writebacks::writebacks          106948                       # number of writebacks
+system.iocache.writebacks::total               106948                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8900                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8937                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8896                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8933                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106982                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106982                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8900                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8940                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8896                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8900                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8940                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1251302972                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1254647972                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8896                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8936                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3411000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1255294991                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1258705991                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8577228251                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8577228251                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1251302972                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1254866972                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1251302972                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1254866972                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8664328406                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8664328406                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3630000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1255294991                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1258924991                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3630000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1255294991                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1258924991                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999981                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.999981                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140595.839551                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 140388.046548                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92189.189189                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141107.800247                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 140905.182022                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80365.304803                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80365.304803                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 140595.839551                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140365.433110                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 140595.839551                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140365.433110                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80988.656092                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80988.656092                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        90750                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 141107.800247                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 140882.384848                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        90750                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 141107.800247                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 140882.384848                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1566664                       # number of replacements
-system.l2c.tags.tagsinuse                63931.901156                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6426547                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1627093                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.949711                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1047057                       # number of replacements
+system.l2c.tags.tagsinuse                63052.180525                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6067910                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1106756                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     5.482609                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   17340.299819                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   183.189406                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   209.040410                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5130.513561                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    11368.638005                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11382.688685                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   175.831777                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   202.455245                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3752.541531                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     4974.040380                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9212.662336                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.264592                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002795                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003190                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.078285                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.173472                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.173686                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002683                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003089                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.057259                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.075898                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.140574                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.975523                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022         9887                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          204                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        50338                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          102                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          389                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         9395                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          202                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1895                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5328                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        42935                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.150864                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003113                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.768097                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 77438610                       # Number of tag accesses
-system.l2c.tags.data_accesses                77438610                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2557006                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2557006                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           27501                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           32544                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               60045                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6218                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          5959                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             12177                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           161499                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           176783                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               338282                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         6423                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4133                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       754192                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       613728                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       292319                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6682                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4427                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       728293                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       606746                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       315465                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3332408                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6423                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4133                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              754192                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              775227                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       292319                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6682                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4427                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              728293                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              783529                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       315465                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3670690                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         6423                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4133                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             754192                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             775227                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       292319                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6682                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4427                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             728293                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             783529                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       315465                       # number of overall hits
-system.l2c.overall_hits::total                3670690                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         45718                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         43728                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             89446                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data         9327                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         8734                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           18061                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         514166                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         145895                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             660061                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2392                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2135                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        67965                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       161112                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       279683                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2412                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2026                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        57704                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       110574                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       234171                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         920174                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2392                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2135                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             67965                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            675278                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       279683                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2412                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2026                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             57704                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            256469                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       234171                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1580235                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2392                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2135                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            67965                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           675278                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       279683                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2412                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2026                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            57704                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           256469                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       234171                       # number of overall misses
-system.l2c.overall_misses::total              1580235                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    695263000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    645953500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   1341216500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    147547000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    132765000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    280312000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  74695360000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  20188019500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  94883379500                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    336047000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    299166500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   9148970000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  22699764499                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  48351113314                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    341784000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    288119000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   7798345000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  15621099500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  40579265809                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 145463674622                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    336047000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    299166500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   9148970000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  97395124499                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  48351113314                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    341784000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    288119000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   7798345000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  35809119000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  40579265809                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    240347054122                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    336047000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    299166500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   9148970000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  97395124499                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  48351113314                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    341784000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    288119000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   7798345000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  35809119000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  40579265809                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   240347054122                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks      2557006                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2557006                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        73219                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        76272                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          149491                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        15545                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        14693                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         30238                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       675665                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       322678                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           998343                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         8815                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6268                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       822157                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       774840                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       572002                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         9094                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6453                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       785997                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       717320                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       549636                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      4252582                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8815                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6268                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          822157                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1450505                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       572002                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         9094                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6453                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          785997                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1039998                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       549636                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             5250925                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8815                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6268                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         822157                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1450505                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       572002                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         9094                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6453                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         785997                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1039998                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       549636                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            5250925                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.624401                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.573317                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.598337                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.600000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.594433                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.597295                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.760978                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.452138                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.661157                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.271356                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.340619                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.082667                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.207929                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.265230                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.313962                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.073415                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.154149                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.216380                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.271356                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.340619                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.082667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.465547                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.265230                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.313962                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.073415                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.246605                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.300944                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.271356                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.340619                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.082667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.465547                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.488955                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.265230                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.313962                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.073415                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.246605                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.426047                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.300944                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15207.642504                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14772.079674                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 14994.706303                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15819.341696                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15200.938860                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 15520.292343                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145274.794522                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 138373.621440                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 143749.410282                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140487.876254                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140124.824356                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134612.962554                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140894.312646                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 141701.492537                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142210.760118                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135143.924165                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141272.808255                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 158082.791539                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140487.876254                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140124.824356                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 134612.962554                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 144229.672074                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 141701.492537                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142210.760118                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 135143.924165                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 139623.576339                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 152095.766846                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140487.876254                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140124.824356                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 134612.962554                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 144229.672074                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 172878.270449                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 141701.492537                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142210.760118                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 135143.924165                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 139623.576339                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 173289.031558                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 152095.766846                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              4391                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   25661.598067                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    59.549817                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    63.820457                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     6721.957431                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5596.771487                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  5304.396230                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   138.527549                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   206.635310                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     5419.027786                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     6651.679849                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  7228.216543                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.391565                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000909                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000974                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu0.data       0.085400                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.080939                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002114                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.data       0.101497                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.110294                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.962100                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9310                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          176                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50213                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0           61                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1          427                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          684                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         1579                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         6559                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          158                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          361                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2614                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        11152                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        36045                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.142059                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.002686                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.766190                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 72230268                       # Number of tag accesses
+system.l2c.tags.data_accesses                72230268                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      2478146                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2478146                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          154381                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          128604                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              282985                       # number of UpgradeReq hits
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+system.l2c.UpgradeReq_misses::total            119342                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        10859                       # number of SCUpgradeReq misses
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+system.l2c.overall_accesses::cpu0.dtb.walker         6391                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         4570                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         661650                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1279879                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       454589                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         7480                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5843                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         691276                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         931015                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       450789                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4493482                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.283558                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.311704                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.296629                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.222890                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.219180                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.220975                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.735273                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.389634                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.622169                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.103583                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.142888                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.085899                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.143653                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.124332                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.165497                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.069155                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.127906                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.152370                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.103583                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.142888                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.085899                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.435406                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.124332                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.165497                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.069155                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.214208                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.250455                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.103583                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.142888                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.085899                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.435406                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.124332                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.165497                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.069155                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.214208                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.250455                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18060.677228                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19408.696772                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 18718.523236                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17283.037112                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17120.394737                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 17199.739431                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139078.519295                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134079.362956                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 138054.050765                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136851.963746                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138692.955590                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132939.904988                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136096.941732                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 136927.956989                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 136634.953464                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133246.930237                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 136461.774582                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 146856.665392                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136851.963746                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138692.955590                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.data 138579.919498                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136927.956989                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.inst 133246.930237                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 135032.848454                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 142291.228490                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136851.963746                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138692.955590                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.data 138579.919498                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136927.956989                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 136634.953464                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 133246.930237                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 135032.848454                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 142291.228490                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              1036                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       34                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        8                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs    129.147059                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs    129.500000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1195231                       # number of writebacks
-system.l2c.writebacks::total                  1195231                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          267                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           23                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          293                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           44                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          630                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            267                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             23                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            293                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             44                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                630                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           267                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            23                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.dtb.walker            3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           293                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            44                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               630                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        55441                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        55441                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        45718                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        43728                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        89446                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9327                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8734                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        18061                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       514166                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       145895                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        660061                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         2392                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         2135                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        67698                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       161089                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       279683                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2409                       # number of ReadSharedReq MSHR misses
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-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       110530                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       234171                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       919544                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         2392                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         2135                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu0.data       675255                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       279683                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2409                       # number of demand (read+write) MSHR misses
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-system.l2c.demand_mshr_misses::cpu1.data       256425                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       234171                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total          1579605                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         2392                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu0.data       675255                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2409                       # number of overall MSHR misses
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-system.l2c.overall_mshr_misses::cpu1.data       256425                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       234171                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total         1579605                       # number of overall MSHR misses
+system.l2c.writebacks::writebacks              823102                       # number of writebacks
+system.l2c.writebacks::total                   823102                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          112                       # number of ReadSharedReq MSHR hits
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+system.l2c.ReadSharedReq_mshr_hits::total          263                       # number of ReadSharedReq MSHR hits
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+system.l2c.CleanEvict_mshr_misses::writebacks        35269                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total        35269                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data        61102                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        58240                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total       119342                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10859                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11400                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total        22259                       # number of SCUpgradeReq MSHR misses
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.624401                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.573317                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.598337                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.594433                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.597295                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.452138                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.661157                       # mshr miss rate for ReadExReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.082342                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.207900                       # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.264900                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.313962                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.073042                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.154087                       # mshr miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.216232                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.271356                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.340619                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.082342                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.465531                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.264900                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.313962                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.073042                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.246563                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::total      0.300824                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.271356                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.340619                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.082342                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.465531                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.073042                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total     0.300824                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73580.712214                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73562.888904                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73571.998826                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76479.682642                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76568.010076                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76522.396324                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135274.794522                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128373.621440                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 133749.410282                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124676.223818                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130896.398879                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125219.539809                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131281.027775                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 148108.950330                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124676.223818                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 134230.283373                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125219.539809                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 129626.836307                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 142108.606976                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124676.223818                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 134230.283373                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125219.539809                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 129626.836307                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 142108.606976                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140688.023422                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146431.271259                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126000.342133                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138396.453126                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149839.721100                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145162.946429                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139509.057851                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148098.366531                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 131670.738530                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.283558                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.311704                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.296629                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.222890                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.219180                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.220975                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.735273                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.389634                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.622169                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.103583                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.142888                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.085730                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.143630                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.124332                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.165497                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.068977                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.127885                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.152296                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.103583                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.142888                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.085730                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.435394                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.124332                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.165497                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.068977                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.214194                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.250397                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.103583                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.142888                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.085730                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.435394                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.124332                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.165497                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.068977                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.214194                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.250397                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73405.101388                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73447.407332                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73425.747080                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76522.838199                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.421053                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76500.089851                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129078.519295                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124079.362956                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 128054.050765                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122985.737708                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126097.370539                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123319.428715                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 126467.494956                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 136875.285945                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122985.737708                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128580.058033                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123319.428715                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125035.044479                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 132299.122166                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122985.737708                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128580.058033                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123319.428715                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125035.044479                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 132299.122166                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154383.299498                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159070.933014                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131241.202012                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153993.698975                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162871.815452                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158558.142321                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154180.133718                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160896.324480                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 139282.030687                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               90608                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1019089                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38080                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38080                       # Transaction distribution
-system.membus.trans_dist::Writeback           1301925                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           271570                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           429176                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         310200                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          115027                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            674063                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           652544                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        928481                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122552                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               90049                       # Transaction distribution
+system.membus.trans_dist::ReadResp             640443                       # Transaction distribution
+system.membus.trans_dist::WriteReq              37563                       # Transaction distribution
+system.membus.trans_dist::WriteResp             37563                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       930050                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190296                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           413026                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         280293                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          150977                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            593740                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           574320                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        550394                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106981                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106981                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122912                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24802                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5589312                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5736718                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342877                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342877                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6079595                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155682                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        22290                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4211327                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4356581                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       343179                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       343179                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4699760                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155927                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        49604                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    180435584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    180642194                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7274816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7274816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               187917010                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           648574                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4152999                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        44580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    127415488                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    127617319                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7277312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7277312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               134894631                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           564682                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3194785                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4152999    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3194785    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4152999                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109607499                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3194785                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           109901497                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20503498                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            18632000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9125026082                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          6680198838                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         8873044520                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6549107858                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          230408874                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229362666                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3149,11 +3133,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             162                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              162                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -3192,52 +3176,52 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     12411375                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6308416                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      2241470                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         182770                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       168316                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        14454                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              90610                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           5207811                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38080                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38080                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          3858986                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1729776                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          481704                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        322377                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         804081                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          116                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          116                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1151274                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1151274                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      5124442                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9065091                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7602046                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              16667137                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    281816078                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    221579908                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              503395986                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3440017                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         14338060                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.337750                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.475069                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests     11369480                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6166084                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1983565                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          99756                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        89163                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        10593                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              90051                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4379282                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             37563                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            37563                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3408225                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1479469                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          686639                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        358765                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1045403                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          133                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1072017                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1072017                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4296486                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106981                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8273345                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7109938                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              15383283                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    249443752                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    200422911                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              449866663                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2689125                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          7811601                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.375584                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.487066                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                9509841     66.33%     66.33% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                4813765     33.57%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  14454      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4888281     62.58%     62.58% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                2912727     37.29%     99.86% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  10593      0.14%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           14338060                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9248164097                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            7811601                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8585712934                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2627637                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2584443                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        5363594791                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4648327252                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4586237114                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4065319209                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index 8edb1ca7a..4adb13d39 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,138 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.667490                       # Number of seconds simulated
-sim_ticks                                51667489826000                       # Number of ticks simulated
-final_tick                               51667489826000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.667600                       # Number of seconds simulated
+sim_ticks                                51667599599000                       # Number of ticks simulated
+final_tick                               51667599599000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  98445                       # Simulator instruction rate (inst/s)
-host_op_rate                                   115675                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5518412939                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 676348                       # Number of bytes of host memory used
-host_seconds                                  9362.74                       # Real time elapsed on the host
-sim_insts                                   921716010                       # Number of instructions simulated
-sim_ops                                    1083032845                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 178939                       # Simulator instruction rate (inst/s)
+host_op_rate                                   210249                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            10020424354                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 726764                       # Number of bytes of host memory used
+host_seconds                                  5156.23                       # Real time elapsed on the host
+sim_insts                                   922648651                       # Number of instructions simulated
+sim_ops                                    1084091117                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       356224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       294592                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10211648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          93641864                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        394368                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            104898696                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst     10211648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10211648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     87439552                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       355648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       310272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           9988672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          94253512                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        413888                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            105321992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      9988672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         9988672                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     87921472                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          87460132                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         5566                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         4603                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             159557                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1463167                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1639055                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1366243                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          87942052                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         5557                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         4848                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             156073                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1472724                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6467                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1645669                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1373773                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1368816                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           6895                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           5702                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               197642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1812394                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7633                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2030265                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          197642                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             197642                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1692351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1376346                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           6883                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           6005                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               193326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1824229                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8011                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2038453                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          193326                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             193326                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1701675                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1692750                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1692351                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          6895                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          5702                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              197642                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1812793                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7633                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3723015                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1639055                       # Number of read requests accepted
-system.physmem.writeReqs                      1368816                       # Number of write requests accepted
-system.physmem.readBursts                     1639055                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1368816                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                104838592                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     60928                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  87458560                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 104898696                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               87460132                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      952                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         145140                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               96907                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              103074                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               99514                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               96513                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               97689                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              108359                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               97886                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               97902                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               96810                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              157961                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             100161                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             104541                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              94779                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              97199                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              94176                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              94632                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               82268                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               85491                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               84713                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               83877                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               85039                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               91961                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               84027                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               85348                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               84923                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               91534                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              85936                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              89456                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              82822                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              84269                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              82271                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              82605                       # Per bank write bursts
+system.physmem.bw_write::total                1702073                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1701675                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          6883                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          6005                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              193326                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1824627                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3740527                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1645669                       # Number of read requests accepted
+system.physmem.writeReqs                      1376346                       # Number of write requests accepted
+system.physmem.readBursts                     1645669                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1376346                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                105266752                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     56064                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  87940608                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 105321992                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               87942052                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      876                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2255                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         378251                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               98784                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              105100                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              100845                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               95977                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              103819                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              113338                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               98145                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               99955                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               93968                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              154563                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              98779                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             100711                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              92945                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              97659                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              91699                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              98506                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               83240                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               87253                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               86416                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               83797                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               90075                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               95693                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               84431                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               87097                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               83064                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               88599                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              84727                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              86277                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              82015                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              84756                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              80845                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              85787                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51667488071000                       # Total gap between requests
+system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51667597819500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1639040                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1645654                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1366243                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1313990                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    317969                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       940                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       332                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       443                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       534                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::9                       341                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::11                      159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      164                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      118                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17                       91                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       73                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       54                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1373773                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::1                    317364                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -159,163 +159,161 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::41                      302                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::63                       54                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       648381                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      296.579894                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     173.167741                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.754919                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         255622     39.42%     39.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       156386     24.12%     63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        60110      9.27%     72.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        34859      5.38%     78.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        25315      3.90%     82.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        18876      2.91%     85.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        13882      2.14%     87.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        12930      1.99%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        70401     10.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         648381                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         79285                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.660314                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      283.326654                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          79282    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::42                      352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      236                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples       648118                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      298.103938                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.284544                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.148793                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         253468     39.11%     39.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       156556     24.16%     63.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        60545      9.34%     72.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        34961      5.39%     78.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        26042      4.02%     82.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        18689      2.88%     84.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        14146      2.18%     87.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        13035      2.01%     89.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        70676     10.90%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         648118                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         79768                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.619672                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-4095          79765    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           79285                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         79285                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.235795                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.792425                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.378813                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           77022     97.15%     97.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             299      0.38%     97.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              59      0.07%     97.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             299      0.38%     97.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              54      0.07%     98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             317      0.40%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             225      0.28%     98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              23      0.03%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              58      0.07%     98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             133      0.17%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              25      0.03%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              40      0.05%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             480      0.61%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              36      0.05%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              17      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             132      0.17%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               8      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            28      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           79768                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         79768                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.225855                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.793439                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.200790                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           77436     97.08%     97.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             326      0.41%     97.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              71      0.09%     97.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             315      0.39%     97.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              43      0.05%     98.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             360      0.45%     98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             211      0.26%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              25      0.03%     98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              65      0.08%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             125      0.16%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              20      0.03%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              34      0.04%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             501      0.63%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              33      0.04%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              30      0.04%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             120      0.15%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               8      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            23      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             4      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           79285                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    26536419219                       # Total ticks spent queuing
-system.physmem.totMemAccLat               57250850469                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8190515000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       16199.48                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           79768                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    26467861730                       # Total ticks spent queuing
+system.physmem.totMemAccLat               57307730480                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8223965000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       16091.91                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34949.48                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.03                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.69                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.03                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.69                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  34841.91                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.04                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.70                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.04                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.70                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.18                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1330988                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1025273                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.25                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                     17177428.18                       # Average gap between requests
-system.physmem.pageHitRate                      78.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2459736720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1342118250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6223136400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4424051520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3374668883040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1319911106400                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29842673702250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34551702734580                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.732053                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49645039210452                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1725290840000                       # Time in different power states
+system.physmem.avgWrQLen                        23.70                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1338706                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1032034                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.39                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.11                       # Row buffer hit rate for writes
+system.physmem.avgGap                     17097068.62                       # Average gap between requests
+system.physmem.pageHitRate                      78.53                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2524404960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1377403500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6364503600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4523001120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3374676002880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1325410671600                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29837914926750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34552790914410                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.751704                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49637080843701                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1725294480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    297159003548                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    305218373299                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2442023640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1332453375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6554020200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4431127680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3374668883040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1320412056885                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29842234272000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34552074836820                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.739255                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49644231851772                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1725290840000                       # Time in different power states
+system.physmem_1.actEnergy                 2375306640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1296050250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6464827200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4380881760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3374676002880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1318079999925                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29844345348750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34551618417405                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.729010                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49647781129555                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1725294480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    297961425728                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    294523106445                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -339,15 +337,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               252436095                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         176405196                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          11951074                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            185535740                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               131467669                       # Number of BTB hits
+system.cpu.branchPred.lookups               252640803                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         176566458                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          11942340                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            185523828                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               131623059                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.858407                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30937069                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2133020                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.946714                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30927608                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2129490                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -378,63 +376,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    560363                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                560363                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        20601                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       178609                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples       560363                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          560363    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       560363                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       199210                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 27145.243713                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 23005.972162                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20907.221064                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       196938     98.86%     98.86% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     98.86% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         1933      0.97%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143           52      0.03%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          120      0.06%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           58      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           84      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                    561342                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                561342                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        20890                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       179371                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples       561342                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          561342    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       561342                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       200261                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 26959.987217                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 22796.816332                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20928.483641                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       197960     98.85%     98.85% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071            3      0.00%     98.85% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         1973      0.99%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143           53      0.03%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          114      0.06%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           41      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           90      0.04%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::458752-524287           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       199210                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples  -1571833592                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0     -1571833592    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total  -1571833592                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        178610     89.66%     89.66% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         20601     10.34%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       199211                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       560363                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       200261                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples  -1569959592                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0     -1569959592    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total  -1569959592                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        179372     89.57%     89.57% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         20890     10.43%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       200262                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       561342                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       560363                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       199211                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       561342                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       200262                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       199211                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       759574                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       200262                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       761604                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    178192284                       # DTB read hits
-system.cpu.dtb.read_misses                     462603                       # DTB read misses
-system.cpu.dtb.write_hits                   157870024                       # DTB write hits
-system.cpu.dtb.write_misses                     97760                       # DTB write misses
+system.cpu.dtb.read_hits                    178417728                       # DTB read hits
+system.cpu.dtb.read_misses                     463663                       # DTB read misses
+system.cpu.dtb.write_hits                   158017805                       # DTB write hits
+system.cpu.dtb.write_misses                     97679                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               45300                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid               45304                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1089                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    78455                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1375                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  14585                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    77601                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1384                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  14410                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     23059                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                178654887                       # DTB read accesses
-system.cpu.dtb.write_accesses               157967784                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23069                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                178881391                       # DTB read accesses
+system.cpu.dtb.write_accesses               158115484                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         336062308                       # DTB hits
-system.cpu.dtb.misses                          560363                       # DTB misses
-system.cpu.dtb.accesses                     336622671                       # DTB accesses
+system.cpu.dtb.hits                         336435533                       # DTB hits
+system.cpu.dtb.misses                          561342                       # DTB misses
+system.cpu.dtb.accesses                     336996875                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -464,183 +462,190 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    134893                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                134893                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1070                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       117642                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       134893                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          134893    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       134893                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       118712                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 30207.312656                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 25802.029077                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 23121.543530                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       116190     97.88%     97.88% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071            6      0.01%     97.88% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         2295      1.93%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           67      0.06%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          109      0.09%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           28      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       118712                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  -1572850092                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     -1572850092    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  -1572850092                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        117642     99.10%     99.10% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1070      0.90%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       118712                       # Table walker page sizes translated
+system.cpu.itb.walker.walks                    135051                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                135051                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1071                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       117673                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       135051                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          135051    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       135051                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       118744                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 30328.088156                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 25835.192345                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 23534.472369                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-32767        58823     49.54%     49.54% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-65535        57227     48.19%     97.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-98303            2      0.00%     97.73% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-131071            5      0.00%     97.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-163839         2006      1.69%     99.43% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::163840-196607          464      0.39%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-229375           29      0.02%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::229376-262143           32      0.03%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-294911           88      0.07%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::294912-327679           29      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-360447           14      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::360448-393215           13      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-425983            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::425984-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       118744                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  -1570990092                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     -1570990092    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total  -1570990092                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        117673     99.10%     99.10% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1071      0.90%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       118744                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       134893                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       134893                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       135051                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       135051                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118712                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       118712                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       253605                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    438788360                       # ITB inst hits
-system.cpu.itb.inst_misses                     134893                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118744                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       118744                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       253795                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    439141642                       # ITB inst hits
+system.cpu.itb.inst_misses                     135051                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               45300                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid               45304                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1089                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    56501                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    55572                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    359579                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    356769                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                438923253                       # ITB inst accesses
-system.cpu.itb.hits                         438788360                       # DTB hits
-system.cpu.itb.misses                          134893                       # DTB misses
-system.cpu.itb.accesses                     438923253                       # DTB accesses
-system.cpu.numCycles                       2560804207                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                439276693                       # ITB inst accesses
+system.cpu.itb.hits                         439141642                       # DTB hits
+system.cpu.itb.misses                          135051                       # DTB misses
+system.cpu.itb.accesses                     439276693                       # DTB accesses
+system.cpu.numCycles                       2565959423                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   921716010                       # Number of instructions committed
-system.cpu.committedOps                    1083032845                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      92871017                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7624                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100775316475                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.778301                       # CPI: cycles per instruction
-system.cpu.ipc                               0.359932                       # IPC: instructions per cycle
+system.cpu.committedInsts                   922648651                       # Number of instructions committed
+system.cpu.committedOps                    1084091117                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      92858708                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7622                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100770378430                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.781080                       # CPI: cycles per instruction
+system.cpu.ipc                               0.359573                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16484                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1740208465                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       820595742                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements          10718531                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.930101                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           320228714                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          10719043                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.874749                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        7085883500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.930101                       # Average occupied blocks per requestor
+system.cpu.kern.inst.quiesce                    16482                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1742118066                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       823841357                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements          10735802                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.930082                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           320587267                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          10736314                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.860087                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        7087675500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.930082                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999863                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999863                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          394                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1345217745                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1345217745                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    163909013                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       163909013                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    147410694                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      147410694                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       512357                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        512357                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       335795                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       335795                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3851860                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3851860                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4160801                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4160801                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     311319707                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        311319707                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    311832064                       # number of overall hits
-system.cpu.dcache.overall_hits::total       311832064                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6365428                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6365428                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4129661                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4129661                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1399457                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1399457                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1238951                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1238951                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       310648                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       310648                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1346721008                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1346721008                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    164117651                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       164117651                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    147554232                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      147554232                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       511700                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        511700                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       336216                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       336216                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3856271                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3856271                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4163172                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4163172                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     311671883                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        311671883                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    312183583                       # number of overall hits
+system.cpu.dcache.overall_hits::total       312183583                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6375380                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6375380                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4133213                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4133213                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1400858                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1400858                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1238861                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1238861                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       308609                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       308609                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     10495089                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       10495089                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     11894546                       # number of overall misses
-system.cpu.dcache.overall_misses::total      11894546                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 117272085000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 117272085000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 200088691000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 200088691000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  84456521500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  84456521500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5138880500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   5138880500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     10508593                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       10508593                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     11909451                       # number of overall misses
+system.cpu.dcache.overall_misses::total      11909451                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 117756219000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 117756219000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 201470838000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 201470838000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  84198421500                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  84198421500                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5139608000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   5139608000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 317360776000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 317360776000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 317360776000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 317360776000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    170274441                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    170274441                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    151540355                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    151540355                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1911814                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1911814                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1574746                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1574746                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4162508                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4162508                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4160802                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4160802                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    321814796                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    321814796                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    323726610                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    323726610                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037383                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.037383                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027251                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027251                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.732005                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.732005                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786762                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.786762                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.074630                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.074630                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 319227057000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 319227057000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 319227057000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 319227057000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    170493031                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    170493031                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    151687445                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    151687445                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1912558                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1912558                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1575077                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1575077                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4164880                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4164880                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4163173                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4163173                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    322180476                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    322180476                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    324093034                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    324093034                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037394                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.037394                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027248                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027248                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.732453                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.732453                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786540                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.786540                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.074098                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.074098                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032612                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032612                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036743                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036743                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18423.283556                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 18423.283556                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.601960                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.601960                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68167.765715                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68167.765715                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16542.454804                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16542.454804                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032617                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032617                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036747                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036747                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18470.462780                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18470.462780                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48744.363767                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48744.363767                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 67964.381395                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 67964.381395                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16654.109245                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16654.109245                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30238.979012                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30238.979012                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26681.201283                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26681.201283                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30377.716313                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30377.716313                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26804.514918                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26804.514918                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -649,155 +654,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8229800                       # number of writebacks
-system.cpu.dcache.writebacks::total           8229800                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       778718                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       778718                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1821021                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1821021                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          152                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total          152                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69509                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        69509                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2599739                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2599739                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2599739                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2599739                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5586710                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5586710                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2308640                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2308640                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1391918                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1391918                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1238799                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1238799                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       241139                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       241139                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      8239619                       # number of writebacks
+system.cpu.dcache.writebacks::total           8239619                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       773301                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       773301                       # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total      1821450                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          142                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total          142                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70152                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        70152                       # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total      2594751                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2594751                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2594751                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5602079                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5602079                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2311763                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2311763                       # number of WriteReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total      1393294                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1238719                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1238719                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       238457                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       238457                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7895350                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7895350                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9287268                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9287268                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7913842                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7913842                       # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total      9307136                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  95942539500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  95942539500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106127468000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 106127468000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26584469000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26584469000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  83210863500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  83210863500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3483152500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3483152500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  96321163500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  96321163500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106904157500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 106904157500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26939627500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26939627500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  82952613500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  82952613500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3468831500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3468831500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202070007500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 202070007500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228654476500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 228654476500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5831192500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5831192500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5820427500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5820427500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11651620000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11651620000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032810                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032810                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015234                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015234                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.728061                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.728061                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786666                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786666                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057931                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057931                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203225321000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 203225321000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230164948500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 230164948500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6198462000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6198462000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6207588500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6207588500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12406050500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12406050500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032858                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032858                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015240                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015240                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.728498                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.728498                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786450                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786450                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057254                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057254                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024534                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024534                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028689                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028689                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17173.352384                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17173.352384                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45969.691247                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45969.691247                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19099.163169                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19099.163169                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67170.593050                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67170.593050                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14444.583829                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14444.583829                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024563                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024563                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028717                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028717                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17193.824560                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17193.824560                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46243.562813                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46243.562813                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19335.206712                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19335.206712                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66966.449614                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66966.449614                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14546.989604                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14546.989604                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25593.546518                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25593.546518                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24620.208709                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24620.208709                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173047.823248                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173047.823248                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172682.237584                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172682.237584                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172865.006009                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172865.006009                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25679.729391                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25679.729391                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24729.943615                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24729.943615                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183946.998249                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183946.998249                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.649499                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.649499                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184057.838672                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184057.838672                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          24130706                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.872431                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           414285199                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24131218                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.168019                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       39477111500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.872431                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          24189642                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.872408                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           414582353                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          24190154                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.138475                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       39504620500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.872408                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999751                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999751                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          287                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          128                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          133                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         462547654                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        462547654                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    414285199                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       414285199                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     414285199                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        414285199                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    414285199                       # number of overall hits
-system.cpu.icache.overall_hits::total       414285199                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     24131228                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      24131228                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     24131228                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       24131228                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     24131228                       # number of overall misses
-system.cpu.icache.overall_misses::total      24131228                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 326882606500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 326882606500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 326882606500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 326882606500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 326882606500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 326882606500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    438416427                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    438416427                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    438416427                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    438416427                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    438416427                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    438416427                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.055042                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.055042                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.055042                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.055042                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.055042                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.055042                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13546.041109                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13546.041109                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13546.041109                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13546.041109                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13546.041109                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13546.041109                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         462962680                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        462962680                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    414582353                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       414582353                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst     24190164                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst     24190164                       # number of overall misses
+system.cpu.icache.overall_misses::total      24190164                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 327340789000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 327340789000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 327340789000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 327340789000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 327340789000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 327340789000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    438772517                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    438772517                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    438772517                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    438772517                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    438772517                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    438772517                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.055131                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.055131                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.055131                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.055131                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.055131                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.055131                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13531.978907                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13531.978907                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13531.978907                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13531.978907                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13531.978907                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13531.978907                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -806,225 +811,230 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24131228                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     24131228                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     24131228                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     24131228                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     24131228                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     24131228                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     24189642                       # number of writebacks
+system.cpu.icache.writebacks::total          24189642                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24190164                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     24190164                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     24190164                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     24190164                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     24190164                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     24190164                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302751379500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 302751379500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302751379500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 302751379500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302751379500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 302751379500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   6746821500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   6746821500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   6746821500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   6746821500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.055042                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.055042                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.055042                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.055042                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.055042                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.055042                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12546.041150                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12546.041150                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12546.041150                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12546.041150                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12546.041150                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12546.041150                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.127703                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.127703                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.127703                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.127703                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303150626000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 303150626000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303150626000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 303150626000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303150626000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 303150626000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   6746864000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   6746864000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   6746864000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   6746864000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.055131                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.055131                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.055131                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.055131                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.055131                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.055131                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12531.978948                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12531.978948                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12531.978948                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12531.978948                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12531.978948                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12531.978948                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1490067                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65247.296250                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           65785634                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1553186                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            42.355284                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      36608904000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37009.506114                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   327.357473                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   390.452800                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8008.475299                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19511.504564                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.564720                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004995                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005958                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.122200                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.297722                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995595                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          261                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62858                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          260                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements          1495284                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65229.781494                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           65922487                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1558468                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            42.299545                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      36600562500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36948.253650                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   327.788805                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   379.909026                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7890.502586                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19683.327428                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.563786                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005002                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005797                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.120400                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.300344                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995327                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          237                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62947                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          237                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          534                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2399                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5570                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54303                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003983                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.959137                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        572783914                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       572783914                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       922401                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       283446                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1205847                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      8229800                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      8229800                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        10447                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        10447                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1641162                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1641162                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24023948                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     24023948                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6905333                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6905333                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       707969                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       707969                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       922401                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       283446                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     24023948                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      8546495                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        33776290                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       922401                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       283446                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     24023948                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      8546495                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       33776290                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         5566                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         4603                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        10169                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        37678                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        37678                       # number of UpgradeReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          502                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2422                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5485                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54486                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003616                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.960495                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        573928107                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       573928107                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       915811                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total        1195114                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      8239619                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      8239619                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     24185917                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     24185917                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data        10440                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total        10440                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1637843                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1637843                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24086368                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     24086368                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6914406                       # number of ReadSharedReq hits
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+system.cpu.l2cache.InvalidateReq_hits::cpu.data       709945                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       709945                       # number of InvalidateReq hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       619608                       # number of ReadExReq misses
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-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst       107277                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total       107277                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       314179                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       314179                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       530830                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       530830                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         5566                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.data       933787                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1051233                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    762054000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    629329000                       # number of ReadReq miss cycles
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1497567500                       # number of UpgradeReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        79500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total        79500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  82257791500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  14189953500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total  14189953500                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  73652413000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total  73652413000                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    762054000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    629329000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data 124658899500                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.Writeback_accesses::writebacks      8229800                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      8229800                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        48125                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.WritebackDirty_accesses::total      8239619                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu.l2cache.WritebackClean_accesses::total     24185917                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        47960                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        47960                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2260770                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2260770                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24131225                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     24131225                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7219512                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7219512                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1238799                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1238799                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       927967                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       288049                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     24131225                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9480282                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     34827523                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       927967                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       288049                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     24131225                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9480282                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     34827523                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.005998                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.015980                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.008363                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782919                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782919                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2264033                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2264033                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24190161                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     24190161                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7233600                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7233600                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1238719                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1238719                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       921368                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       284151                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     24190161                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9497633                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     34893313                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       921368                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       284151                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     24190161                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9497633                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     34893313                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006031                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.017061                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.008631                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782319                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782319                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.274069                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.274069                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004446                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004446                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043518                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043518                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.428504                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.428504                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.005998                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.015980                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004446                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.098498                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.030184                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.005998                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.015980                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004446                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.098498                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.030184                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136912.324829                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136721.485987                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 136825.941587                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39746.470089                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39746.470089                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.276582                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.276582                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004291                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004291                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.044127                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.044127                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.426872                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.426872                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006031                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.017061                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004291                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.099539                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.030366                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006031                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.017061                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.data     0.099539                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.030366                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137340.651431                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136758.663366                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137069.485824                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39528.331557                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39528.331557                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132757.794444                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132757.794444                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132273.959003                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132273.959003                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134958.440889                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134958.440889                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138749.529981                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138749.529981                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136912.324829                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136721.485987                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132273.959003                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133498.216938                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 133405.473382                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136912.324829                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136721.485987                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132273.959003                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133498.216938                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 133405.473382                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132659.882783                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132659.882783                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132259.270856                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132259.270856                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134610.448505                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134610.448505                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138758.307897                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138758.307897                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137340.651431                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136758.663366                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132259.270856                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133318.460541                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 133251.540702                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137340.651431                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136758.663366                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132259.270856                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133318.460541                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 133251.540702                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1033,8 +1043,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1259612                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1259612                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1267142                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1267142                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
@@ -1045,33 +1055,33 @@ system.cpu.l2cache.demand_mshr_hits::total           24                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5566                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4603                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        10169                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1098                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1098                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37678                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        37678                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5557                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4848                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        10405                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37520                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        37520                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       619608                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       619608                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107274                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107274                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       314158                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       314158                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       530830                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       530830                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         5566                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4603                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       107274                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       933766                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1051209                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         5566                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4603                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       107274                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       933766                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1051209                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       626190                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       626190                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       103790                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total       103790                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       319173                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       319173                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       528774                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       528774                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         5557                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4848                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       103790                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       945363                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1059558                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         5557                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4848                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       103790                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       945363                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1059558                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        86006                       # number of ReadReq MSHR uncacheable
@@ -1080,157 +1090,158 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33706
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119712                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    706394000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    583299000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1289693000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2666012000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2666012000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    707632000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    614526000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1322158000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2655683000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2655683000                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        69500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  76061711500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  76061711500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  13116951000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  13116951000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  39257197500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  39257197500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  68344113000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  68344113000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    706394000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    583299000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  13116951000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115318909000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 129725553000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    706394000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    583299000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  13116951000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115318909000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 129725553000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5936031500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5409917000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11345948500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5432186500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5432186500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   5936031500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10842103500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  16778135000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.005998                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.015980                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008363                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  76808392000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  76808392000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  12689415000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  12689415000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  39772846000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  39772846000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  68084045500                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  68084045500                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    707632000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    614526000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  12689415000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116581238000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 130592811000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    707632000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    614526000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  12689415000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116581238000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 130592811000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5777189500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11713263500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5819359500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5819359500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11596549000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  17532623000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006031                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.017061                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008631                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782919                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782919                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782319                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782319                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.274069                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.274069                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004445                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043515                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043515                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.428504                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.428504                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.005998                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.015980                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.098496                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030183                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.005998                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.015980                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.098496                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030183                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126721.485987                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126825.941587                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70757.789692                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.789692                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.276582                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.276582                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004291                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004291                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.044124                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.044124                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.426872                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.426872                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006031                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.017061                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004291                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.099537                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030366                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006031                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.017061                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004291                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.099537                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030366                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126758.663366                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127069.485824                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70780.463753                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70780.463753                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122757.794444                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122757.794444                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122275.211142                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122275.211142                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124960.043991                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124960.043991                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128749.529981                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128749.529981                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126721.485987                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122275.211142                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123498.723449                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123406.052460                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126721.485987                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122275.211142                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123498.723449                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123406.052460                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.118144                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160545.953646                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131920.429970                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161163.783896                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161163.783896                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.118144                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160854.910019                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140154.161655                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122659.882783                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122659.882783                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122260.477888                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122260.477888                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124612.188374                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124612.188374                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128758.307897                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128758.307897                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126758.663366                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122260.477888                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123319.019255                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123252.158919                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126758.663366                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122260.477888                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123319.019255                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123252.158919                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171445.217675                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136191.236658                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.551831                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.551831                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172047.965224                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146456.687717                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     70442734                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     35592438                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4386                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2280                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2280                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     70595106                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     35668602                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4412                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2257                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2257                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1728553                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      33080077                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1731880                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      33156424                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33706                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      9596069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     26854364                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        48128                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      9613409                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     24185917                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2732498                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        47963                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        48129                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2260770                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2260770                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     24131228                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7228389                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1345463                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1238799                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     72494093                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32387839                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       691084                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2167479                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total         107740495                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1547746112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1133685906                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2304392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7423736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2691160146                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2148445                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     73231054                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.009642                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.097721                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        47964                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2264033                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2264033                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     24190164                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7242479                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1345383                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1238719                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     72670859                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32439334                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       687653                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2163740                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total         107961586                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3099416704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1135424530                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2273208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7370944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         4244485386                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2167477                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     38466398                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.018246                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.133841                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           72524927     99.04%     99.04% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             706127      0.96%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           37764532     98.18%     98.18% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             701866      1.82%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       73231054                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    44001619997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       38466398                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    68278869995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1484887                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1476392                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   36281501081                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   36370852681                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14914900069                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14941078957                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     403060948                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     403557888                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1239526970                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1242412419                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40325                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40325                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40327                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40327                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1249,11 +1260,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231008                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231008                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231012                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231012                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353792                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353796                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1270,104 +1281,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334464                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334464                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334480                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334480                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492384                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492400                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42171500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               16000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25807000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            34147000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              120500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565802629                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           565729644                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               42000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147768000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147772000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115486                       # number of replacements
-system.iocache.tags.tagsinuse               10.440024                       # Cycle average of tags in use
+system.iocache.tags.replacements               115488                       # number of replacements
+system.iocache.tags.tagsinuse               10.440019                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115502                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115504                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13160095292000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle         13160148501000                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::realview.ethernet     3.520841                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.919182                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.919178                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.220053                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.432449                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.652501                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039893                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039893                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039911                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039911                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8840                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8877                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8842                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8879                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8840                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8880                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8842                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8882                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8840                       # number of overall misses
-system.iocache.overall_misses::total             8880                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1641330150                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1646399150                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8842                       # number of overall misses
+system.iocache.overall_misses::total             8882                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5086500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1658170108                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1663256608                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13825092479                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13825092479                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1641330150                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1646750150                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1641330150                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1646750150                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13863609036                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13863609036                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5437500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1658170108                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1663607608                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5437500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1658170108                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1663607608                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8840                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8877                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8842                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8879                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8840                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8880                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8842                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8882                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8840                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8880                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8842                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8882                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1381,55 +1392,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 185670.831448                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 185467.967782                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 187533.375707                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 187324.767204                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129613.482328                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129613.482328                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 185670.831448                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 185444.836712                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 185670.831448                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 185444.836712                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32333                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.584077                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129974.584077                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 187533.375707                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 187301.014186                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 187533.375707                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 187301.014186                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         34622                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3346                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3502                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.663180                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.886351                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8840                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8877                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8842                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8879                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8840                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8880                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8842                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8882                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8840                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8880                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1199330150                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1202549150                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8842                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8882                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1216070108                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1219306608                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8491892479                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8491892479                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1199330150                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1202750150                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1199330150                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1202750150                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8530409036                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8530409036                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3437500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1216070108                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1219507608                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3437500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1216070108                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1219507608                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1443,73 +1454,73 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135670.831448                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 135467.967782                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137533.375707                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 137324.767204                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79613.482328                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79613.482328                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 135670.831448                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 135444.836712                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 135670.831448                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 135444.836712                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.584077                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.584077                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 137533.375707                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 137301.014186                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 137533.375707                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 137301.014186                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               86006                       # Transaction distribution
-system.membus.trans_dist::ReadResp             526484                       # Transaction distribution
+system.membus.trans_dist::ReadResp             528253                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33706                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33706                       # Transaction distribution
-system.membus.trans_dist::Writeback           1366243                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           236394                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            38482                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1373773                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           233285                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            38308                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           38483                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1149637                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1149637                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        440478                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           38309                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1154179                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1154179                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        442247                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4838609                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4968261                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340944                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       340944                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5309205                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4854992                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4984644                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341559                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341559                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5326203                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    185140076                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    185310482                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7218752                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7218752                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               192529234                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3380                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3460550                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    186025772                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    186196178                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7238272                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7238272                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               193434450                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3077                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3470793                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3460550    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3470793    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3460550                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           102447500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3470793                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           102553500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5490500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5511000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9255992894                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9297161713                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         8767241103                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8798501817                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228448107                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227863618                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 225315f7c..3c5f4dcb0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,141 +1,141 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.331518                       # Number of seconds simulated
-sim_ticks                                51331518104000                       # Number of ticks simulated
-final_tick                               51331518104000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.331535                       # Number of seconds simulated
+sim_ticks                                51331535316000                       # Number of ticks simulated
+final_tick                               51331535316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55750                       # Simulator instruction rate (inst/s)
-host_op_rate                                    65505                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3383587938                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 679676                       # Number of bytes of host memory used
-host_seconds                                 15170.74                       # Real time elapsed on the host
-sim_insts                                   845761974                       # Number of instructions simulated
-sim_ops                                     993759083                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  76705                       # Simulator instruction rate (inst/s)
+host_op_rate                                    90129                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4658243300                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 731992                       # Number of bytes of host memory used
+host_seconds                                 11019.51                       # Real time elapsed on the host
+sim_insts                                   845255961                       # Number of instructions simulated
+sim_ops                                     993175006                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       205120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       196736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5673888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          72271240                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        441728                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             78788712                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5673888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5673888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67330112                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       205184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       203136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5579360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          71974536                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        439872                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             78402088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5579360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5579360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     67218688                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67350692                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3205                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3074                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             104607                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1129251                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6902                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1247039                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1052033                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          67239268                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3206                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3174                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             103130                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1124615                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6873                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1240998                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1050292                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1054606                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           3996                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3833                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               110534                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1407931                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8605                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1534899                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          110534                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             110534                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1311672                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1052865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           3997                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           3957                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               108693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1402150                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8569                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1527367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1309501                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1312073                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1311672                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          3996                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3833                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              110534                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1408332                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8605                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2846972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1247039                       # Number of read requests accepted
-system.physmem.writeReqs                      1054606                       # Number of write requests accepted
-system.physmem.readBursts                     1247039                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1054606                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 79759552                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     50944                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  67349568                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  78788712                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               67350692                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      796                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1309902                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1309501                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          3997                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          3957                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1402551                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8569                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2837269                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1240998                       # Number of read requests accepted
+system.physmem.writeReqs                      1052865                       # Number of write requests accepted
+system.physmem.readBursts                     1240998                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1052865                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 79374080                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     49792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  67238272                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  78402088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               67239268                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      778                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         141264                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               74145                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               81438                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               79571                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               74681                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               75850                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               80076                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               74234                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               74770                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               71012                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              102127                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              78424                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              78933                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              75355                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              78384                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              73014                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              74229                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61794                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67391                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               68136                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               64875                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               65862                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               67755                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               63835                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65687                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               61691                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               69909                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65651                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67939                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              65356                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67578                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64108                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64770                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         323831                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               73630                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               80699                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               78276                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               74217                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               73666                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               79970                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               75195                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               74032                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               71713                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              100993                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              77049                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              78387                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              77207                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              77888                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              72930                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              74368                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61890                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               67926                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               67010                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               65080                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               64889                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               68021                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64968                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65143                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               62358                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               69100                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              64674                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              67475                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              66848                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              67005                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              63727                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64484                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51331516800500                       # Total gap between requests
+system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51331533904500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1225754                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1219713                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1052033                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    635607                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    328525                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    149631                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    126665                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       692                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       573                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       581                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1305                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       789                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       347                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      405                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::12                      172                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::14                      130                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       74                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1050292                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    631662                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    326376                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    149637                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    126770                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       678                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       576                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       562                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1325                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       777                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       342                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      166                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      165                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       76                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -159,120 +159,120 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    11652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    13577                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    31214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    44410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    55222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    63148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    64318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    64499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    66981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    65872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    66221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    71514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    66478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    79594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    84129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    64906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    68384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      320                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       476504                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      308.725081                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     177.620621                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     336.470597                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         186131     39.06%     39.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       111955     23.50%     62.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        45179      9.48%     72.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23084      4.84%     76.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18337      3.85%     80.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11525      2.42%     83.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10900      2.29%     85.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8098      1.70%     87.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        61295     12.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         476504                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59915                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.799683                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      269.572248                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          59912     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    11849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    13848                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::35                      540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       67                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       475699                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      308.203229                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.287854                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     336.241632                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         186276     39.16%     39.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       111535     23.45%     62.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        45072      9.47%     72.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23389      4.92%     77.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18072      3.80%     80.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11535      2.42%     83.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10579      2.22%     85.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8108      1.70%     87.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        61133     12.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         475699                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59810                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.735663                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      269.812069                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          59807     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59915                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59915                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.563832                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.981523                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.290123                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           57069     95.25%     95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             858      1.43%     96.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              58      0.10%     96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             312      0.52%     97.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              36      0.06%     97.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             354      0.59%     97.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             211      0.35%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              25      0.04%     98.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              62      0.10%     98.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             123      0.21%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              28      0.05%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              35      0.06%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             500      0.83%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              29      0.05%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              31      0.05%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             125      0.21%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               7      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           59810                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59810                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.565591                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.987331                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.225331                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           56970     95.25%     95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             839      1.40%     96.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              56      0.09%     96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             337      0.56%     97.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              42      0.07%     97.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             348      0.58%     97.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             200      0.33%     98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              22      0.04%     98.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              64      0.11%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             127      0.21%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              27      0.05%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              38      0.06%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             506      0.85%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              29      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              24      0.04%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             125      0.21%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::108-111             1      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            19      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59915                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    31917471814                       # Total ticks spent queuing
-system.physmem.totMemAccLat               55284528064                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6231215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25610.95                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            25      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59810                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    31819415784                       # Total ticks spent queuing
+system.physmem.totMemAccLat               55073540784                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6201100000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25656.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44360.95                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  44406.27                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.55                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.31                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.53                       # Average system read bandwidth in MiByte/s
@@ -281,56 +281,56 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.76                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1024444                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    797630                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.21                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1019502                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    795615                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.20                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22302099.93                       # Average gap between requests
-system.physmem.pageHitRate                      79.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1809644760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  987405375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4795167000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3404170800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352725027600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1235982378375                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29714714061000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34314417854910                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.486362                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49432942986454                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1714072100000                       # Time in different power states
+system.physmem.writeRowHitRate                  75.73                       # Row buffer hit rate for writes
+system.physmem.avgGap                     22377767.94                       # Average gap between requests
+system.physmem.pageHitRate                      79.23                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1796611320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  980293875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4755496200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3401526960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1234173509595                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29716310123250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34314143605920                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.480817                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49435613390416                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1714072620000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    184500143546                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    181848672584                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1792725480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  978173625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4925481600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3414972960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352725027600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1238461921980                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29712539014500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34314837317745                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.494534                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49429295042072                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1714072100000                       # Time in different power states
+system.physmem_1.actEnergy                 1799673120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  981964500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4918173000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3406348080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1238619690855                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29712409964250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34314861858525                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.494809                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49429083175074                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1714072620000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    188150328928                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    188374993676                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst          400                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          400                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst           25                       # Number of read requests responded to by this memory
+system.realview.nvmem.bytes_read::total           420                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst          384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
@@ -339,15 +339,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               223690256                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         149470273                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12181359                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157723580                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               103180902                       # Number of BTB hits
+system.cpu.branchPred.lookups               223536271                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         149385948                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12169974                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            157736918                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               103109650                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.418818                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30739943                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             342702                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.368115                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30707782                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             342742                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -378,45 +378,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks            196399                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksLong        196399                       # Table walker walks initiated with long descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples       196399                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0       196399    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total       196399                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walksPending::samples  -1585443796                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::0  -1585443796    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walksPending::total  -1585443796                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K       153599     91.92%     91.92% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::2M        13493      8.08%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total       167092                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       196399                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walks            196595                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong        196595                       # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples       196595                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0       196595    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total       196595                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walksPending::samples  -1584953796                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::0  -1584953796    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walksPending::total  -1584953796                       # Table walker pending requests distribution
+system.cpu.checker.dtb.walker.walkPageSizes::4K       153567     91.80%     91.80% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M        13723      8.20%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total       167290                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       196595                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       196399                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       167092                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       196595                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       167290                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       167092                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total       363491                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       167290                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total       363885                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits            159160853                       # DTB read hits
-system.cpu.checker.dtb.read_misses             146855                       # DTB read misses
-system.cpu.checker.dtb.write_hits           144325246                       # DTB write hits
-system.cpu.checker.dtb.write_misses             49544                       # DTB write misses
+system.cpu.checker.dtb.read_hits            159060610                       # DTB read hits
+system.cpu.checker.dtb.read_misses             146851                       # DTB read misses
+system.cpu.checker.dtb.write_hits           144228364                       # DTB write hits
+system.cpu.checker.dtb.write_misses             49744                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid        78304                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_mva_asid        78296                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid            2034                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries            71588                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries            71608                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           6477                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           6498                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults             18958                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses        159307708                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses       144374790                       # DTB write accesses
+system.cpu.checker.dtb.perms_faults             18956                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses        159207461                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses       144278108                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                 303486099                       # DTB hits
-system.cpu.checker.dtb.misses                  196399                       # DTB misses
-system.cpu.checker.dtb.accesses             303682498                       # DTB accesses
+system.cpu.checker.dtb.hits                 303288974                       # DTB hits
+system.cpu.checker.dtb.misses                  196595                       # DTB misses
+system.cpu.checker.dtb.accesses             303485569                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -446,46 +446,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.walker.walks            119834                       # Table walker walks requested
-system.cpu.checker.itb.walker.walksLong        119834                       # Table walker walks initiated with long descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples       119834                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0       119834    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total       119834                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walksPending::samples  -1586395296                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::0  -1586395296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walksPending::total  -1586395296                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K       107995     98.82%     98.82% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walks            119842                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong        119842                       # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples       119842                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0       119842    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total       119842                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walksPending::samples  -1586149296                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::0  -1586149296    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walksPending::total  -1586149296                       # Table walker pending requests distribution
+system.cpu.checker.itb.walker.walkPageSizes::4K       108003     98.82%     98.82% # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkPageSizes::2M         1286      1.18%    100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total       109281                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total       109289                       # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       119834                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       119834                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       119842                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       119842                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109281                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109281                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total       229115                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            846167011                       # ITB inst hits
-system.cpu.checker.itb.inst_misses             119834                       # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109289                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109289                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total       229131                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits            845660985                       # ITB inst hits
+system.cpu.checker.itb.inst_misses             119842                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
 system.cpu.checker.itb.write_misses                 0                       # DTB write misses
 system.cpu.checker.itb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid        78304                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_mva_asid        78296                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.itb.flush_tlb_asid            2034                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries            51635                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries            51575                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        846286845                       # ITB inst accesses
-system.cpu.checker.itb.hits                 846167011                       # DTB hits
-system.cpu.checker.itb.misses                  119834                       # DTB misses
-system.cpu.checker.itb.accesses             846286845                       # DTB accesses
-system.cpu.checker.numCycles                994327079                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses        845780827                       # ITB inst accesses
+system.cpu.checker.itb.hits                 845660985                       # DTB hits
+system.cpu.checker.itb.misses                  119842                       # DTB misses
+system.cpu.checker.itb.accesses             845780827                       # DTB accesses
+system.cpu.checker.numCycles                993742997                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -517,87 +517,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    934978                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                934978                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15042                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       154863                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       425141                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       509837                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2238.847906                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14877.677912                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       506434     99.33%     99.33% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         1917      0.38%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607          986      0.19%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          211      0.04%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          153      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           25      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751           49      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287           51      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       509837                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       473320                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 22997.265064                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18038.108072                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20298.605153                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       462482     97.71%     97.71% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         7672      1.62%     99.33% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2249      0.48%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          179      0.04%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          532      0.11%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           62      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751          112      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           23      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       473320                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 784047304876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.724244                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.519446                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  781857637876     99.72%     99.72% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1171824000      0.15%     99.87% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     476098500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     199009000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     143211000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    120940000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     26747000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     49238000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2599500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 784047304876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        154864     91.15%     91.15% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15042      8.85%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       169906                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       934978                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks                    935593                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                935593                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15313                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       154778                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       425408                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       510185                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2222.203710                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14681.416911                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       506821     99.34%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         1912      0.37%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607          970      0.19%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          202      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          151      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           19      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751           50      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287           49      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       510185                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       473757                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23106.578900                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 18127.358359                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20599.365275                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       462892     97.71%     97.71% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         7688      1.62%     99.33% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         2250      0.47%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          174      0.04%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          494      0.10%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           87      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751          117      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           41      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       473757                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 784064516876                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.722483                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.520538                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  781865994376     99.72%     99.72% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    1176082000      0.15%     99.87% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     477234000      0.06%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     199500000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     146109500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    120981500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     26256500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     49725000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2626500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::18-19         7500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 784064516876                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        154779     91.00%     91.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         15313      9.00%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       170092                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       935593                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       934978                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       169906                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       935593                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       170092                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       169906                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1104884                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       170092                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1105685                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    168982671                       # DTB read hits
-system.cpu.dtb.read_misses                     669792                       # DTB read misses
-system.cpu.dtb.write_hits                   147065605                       # DTB write hits
-system.cpu.dtb.write_misses                    265186                       # DTB write misses
+system.cpu.dtb.read_hits                    168870430                       # DTB read hits
+system.cpu.dtb.read_misses                     669785                       # DTB read misses
+system.cpu.dtb.write_hits                   146966916                       # DTB write hits
+system.cpu.dtb.write_misses                    265808                       # DTB write misses
 system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               78304                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid               78296                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    2034                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    71824                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                    71844                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                        98                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   9312                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   9429                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69742                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                169652463                       # DTB read accesses
-system.cpu.dtb.write_accesses               147330791                       # DTB write accesses
+system.cpu.dtb.perms_faults                     69613                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                169540215                       # DTB read accesses
+system.cpu.dtb.write_accesses               147232724                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         316048276                       # DTB hits
-system.cpu.dtb.misses                          934978                       # DTB misses
-system.cpu.dtb.accesses                     316983254                       # DTB accesses
+system.cpu.dtb.hits                         315837346                       # DTB hits
+system.cpu.dtb.misses                          935593                       # DTB misses
+system.cpu.dtb.accesses                     316772939                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -627,180 +625,177 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    161206                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                161206                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1436                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       121549                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17620                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       143586                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1244.532893                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9274.227664                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       142628     99.33%     99.33% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          542      0.38%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303           55      0.04%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           79      0.06%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839          218      0.15%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           29      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            4      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                    161130                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                161130                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1443                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       121427                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17608                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       143522                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1275.602347                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  9467.048086                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       142512     99.30%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          586      0.41%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303           51      0.04%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071           83      0.06%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839          223      0.16%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           32      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911           14      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       143586                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       140605                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 28864.162014                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24089.686815                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 22873.385810                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       137806     98.01%     98.01% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071          710      0.50%     98.51% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1778      1.26%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143          108      0.08%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          117      0.08%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           38      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           35      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       140605                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 663785102088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.942542                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.233053                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     38191035356      5.75%      5.75% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    625543374232     94.24%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        49878500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          812000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 663785102088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        121549     98.83%     98.83% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1436      1.17%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       122985                       # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       143522                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       140478                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 29089.590541                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24285.230021                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 22670.988579                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       137385     97.80%     97.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071          891      0.63%     98.43% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         1925      1.37%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           93      0.07%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          119      0.08%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           27      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           23      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       140478                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 668097269884                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.944108                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.230056                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     37393446856      5.60%      5.60% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    630652469528     94.40%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        50695000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          657500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4            1000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 668097269884                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        121427     98.83%     98.83% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1443      1.17%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       122870                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161206                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       161206                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161130                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       161130                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122985                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       122985                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       284191                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    355626065                       # ITB inst hits
-system.cpu.itb.inst_misses                     161206                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122870                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       122870                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       284000                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    355391745                       # ITB inst hits
+system.cpu.itb.inst_misses                     161130                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               78304                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid               78296                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    2034                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    52940                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    52871                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    369021                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    369048                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                355787271                       # ITB inst accesses
-system.cpu.itb.hits                         355626065                       # DTB hits
-system.cpu.itb.misses                          161206                       # DTB misses
-system.cpu.itb.accesses                     355787271                       # DTB accesses
-system.cpu.numCycles                       1638586091                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                355552875                       # ITB inst accesses
+system.cpu.itb.hits                         355391745                       # DTB hits
+system.cpu.itb.misses                          161130                       # DTB misses
+system.cpu.itb.accesses                     355552875                       # DTB accesses
+system.cpu.numCycles                       1639149006                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          642614268                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      998103903                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   223690256                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133920845                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     910005464                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26014386                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3801464                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                28966                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9302327                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1031206                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          853                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 355240310                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6091194                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   48629                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1579791741                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.740255                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.146164                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          642133876                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      997446842                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   223536271                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          133817432                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     910640256                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                25987402                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3814067                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                27748                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9296817                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1023598                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          983                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 355005878                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6082209                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   48751                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1579931046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.739715                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.145918                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1024362050     64.84%     64.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                213190505     13.49%     78.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70458696      4.46%     82.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                271780490     17.20%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1024858413     64.87%     64.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                213048750     13.48%     78.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70422001      4.46%     82.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                271601882     17.19%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1579791741                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.136514                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.609125                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                522893988                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             566130284                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 431833495                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49726107                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9207867                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33553949                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3859168                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1081567524                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              28956293                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9207867                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                567372760                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                69190624                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      368823691                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 437050453                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             128146346                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1061861877                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6771880                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5087051                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 328687                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 662195                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               77193560                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20256                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1009820206                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1635273516                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1255804175                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1470464                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             944392449                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65427754                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           26765768                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23112103                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 102007080                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            173010630                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           150618329                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9860591                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8967243                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1027007600                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27059230                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1042343751                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3268943                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60307743                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33600701                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         312855                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1579791741                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.659798                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.917984                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1579931046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.136373                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.608515                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                522505611                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             567007663                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 431520293                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              49702709                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9194770                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33525771                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3859042                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1080875290                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              28941730                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9194770                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                566963257                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                68325752                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      370117398                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 436739828                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             128590041                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1061188804                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6761282                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               5074872                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 331009                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 667465                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               77645177                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            20261                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1009236679                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1634390089                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1255037462                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1470821                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             943893813                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65342863                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           26761446                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23109655                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 101993436                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            172887729                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           150512713                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9835963                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8956761                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1026341207                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27052915                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1041697414                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3264017                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        60219112                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33542548                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         311458                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1579931046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.659331                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.917837                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           934526324     59.16%     59.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           332943694     21.08%     80.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           234048480     14.82%     95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            71809082      4.55%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6444954      0.41%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19207      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           935073091     59.18%     59.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           332737212     21.06%     80.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           233873919     14.80%     95.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            71794095      4.54%     99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6433566      0.41%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19163      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1579791741                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1579931046                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                57575402     35.04%     35.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 100057      0.06%     35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26740      0.02%     35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                57548727     35.04%     35.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 100099      0.06%     35.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26751      0.02%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.12% # attempts to use FU when none available
@@ -823,19 +818,19 @@ system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.12% # at
 system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              764      0.00%     35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              757      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44168987     26.88%     62.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62424891     38.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44132085     26.87%     62.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              62410380     38.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             717769712     68.86%     68.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2531817      0.24%     69.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122691      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             717342377     68.86%     68.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2532202      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                122567      0.01%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   8      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
@@ -857,102 +852,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         121277      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         121087      0.01%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            172853843     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           148944351     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            172736633     16.58%     85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           148842483     14.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1042343751                       # Type of FU issued
-system.cpu.iq.rate                           0.636124                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   164296841                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157623                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3829567748                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1113568735                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1024464263                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2477278                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             947290                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       909965                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1205083989                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1556592                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4287735                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1041697414                       # Type of FU issued
+system.cpu.iq.rate                           0.635511                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   164218799                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157645                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3828331710                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1112806179                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1023834597                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2476979                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             946356                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       909820                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1204359624                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1556578                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4281868                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13755130                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14415                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       142727                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6290239                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13732493                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14369                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       140572                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6281305                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2513645                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1546946                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2514322                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1544139                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9207867                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6935208                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9652893                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1054288001                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9194770                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6870613                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9053250                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1053615244                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             173010630                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            150618329                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           22687803                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  56498                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               9524585                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         142727                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3650015                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5096410                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8746425                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1031209628                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             168969861                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10209992                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             172887729                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            150512713                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           22684457                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  56400                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8925068                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         140572                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3644333                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5090402                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8734735                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1030574997                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             168857481                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10197714                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        221171                       # number of nop insts executed
-system.cpu.iew.exec_refs                    316030804                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                195653401                       # Number of branches executed
-system.cpu.iew.exec_stores                  147060943                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.629329                       # Inst execution rate
-system.cpu.iew.wb_sent                     1026179606                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1025374228                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 436457494                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 705894723                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        221122                       # number of nop insts executed
+system.cpu.iew.exec_refs                    315819616                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                195518777                       # Number of branches executed
+system.cpu.iew.exec_stores                  146962135                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.628726                       # Inst execution rate
+system.cpu.iew.wb_sent                     1025549780                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1024744417                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 436186320                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 705504935                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.625768                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618304                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.625169                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.618261                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        51232529                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        26746375                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8382033                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1567845308                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.633837                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.270098                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        51156578                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        26741457                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8371043                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1568002280                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.633402                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.269603                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1057713558     67.46%     67.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    286814809     18.29%     85.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120141410      7.66%     93.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36433500      2.32%     95.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28325160      1.81%     97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13966043      0.89%     98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8603569      0.55%     98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4169387      0.27%     99.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11677872      0.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1058124948     67.48%     67.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    286691231     18.28%     85.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    120053535      7.66%     93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36420041      2.32%     95.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28336916      1.81%     97.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     13959603      0.89%     98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8598360      0.55%     98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4160425      0.27%     99.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11657221      0.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1567845308                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            845761974                       # Number of instructions committed
-system.cpu.commit.committedOps              993759083                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1568002280                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            845255961                       # Number of instructions committed
+system.cpu.commit.committedOps              993175006                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      303583589                       # Number of memory references committed
-system.cpu.commit.loads                     159255499                       # Number of loads committed
-system.cpu.commit.membars                     6904959                       # Number of memory barriers committed
-system.cpu.commit.branches                  188760643                       # Number of branches committed
-system.cpu.commit.fp_insts                     896514                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 913055926                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25211674                       # Number of function calls committed.
+system.cpu.commit.refs                      303386643                       # Number of memory references committed
+system.cpu.commit.loads                     159155235                       # Number of loads committed
+system.cpu.commit.membars                     6901293                       # Number of memory barriers committed
+system.cpu.commit.branches                  188640484                       # Number of branches committed
+system.cpu.commit.fp_insts                     896738                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 912506063                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25186659                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        687818920     69.21%     69.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2146460      0.22%     69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98075      0.01%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        687431731     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2146648      0.22%     69.43% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            97945      0.01%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
@@ -979,531 +974,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc       111997      0.01%     69.45% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       159255499     16.03%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      144328090     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       159155235     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      144231408     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         993759083                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11677872                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2593635375                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2101836328                       # The number of ROB writes
-system.cpu.timesIdled                         8111566                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        58794350                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101024450248                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   845761974                       # Number of Instructions Simulated
-system.cpu.committedOps                     993759083                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.937408                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.937408                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.516154                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.516154                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1220647692                       # number of integer regfile reads
-system.cpu.int_regfile_writes               729132737                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1462075                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   783592                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 224479860                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                225129726                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2563991678                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               26780868                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9656863                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.972805                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           282353083                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9657375                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.237042                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        2742937500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.972805                       # Average occupied blocks per requestor
+system.cpu.commit.op_class_0::total         993175006                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11657221                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2593153041                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2100498051                       # The number of ROB writes
+system.cpu.timesIdled                         8123602                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59217960                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101023921760                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   845255961                       # Number of Instructions Simulated
+system.cpu.committedOps                     993175006                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.939234                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.939234                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.515668                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.515668                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1219925781                       # number of integer regfile reads
+system.cpu.int_regfile_writes               728690577                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1462315                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   782072                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 224390859                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                225039549                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              2563491272                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               26777143                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9646522                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.972803                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           282175483                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9647034                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.249973                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.972803                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          383                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1233161168                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1233161168                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146769345                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146769345                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127879890                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127879890                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       376551                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        376551                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       324490                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       324490                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3281849                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3281849                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3677222                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3677222                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     274649235                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        274649235                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    275025786                       # number of overall hits
-system.cpu.dcache.overall_hits::total       275025786                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9521174                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9521174                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11203473                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11203473                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1164152                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1164152                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1231188                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1231188                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       446606                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       446606                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1232341715                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1232341715                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146679057                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146679057                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127793945                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127793945                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       377283                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        377283                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       324111                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       324111                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3281173                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3281173                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3676011                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3676011                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     274473002                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        274473002                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    274850285                       # number of overall hits
+system.cpu.dcache.overall_hits::total       274850285                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9506685                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9506685                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11193954                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11193954                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1163770                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1163770                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1231562                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1231562                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       446112                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       446112                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20724647                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20724647                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21888799                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21888799                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 166185133500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 166185133500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 435748871062                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 435748871062                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  89257967135                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  89257967135                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6843268000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6843268000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       276500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       276500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 601934004562                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 601934004562                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 601934004562                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 601934004562                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    156290519                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    156290519                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    139083363                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    139083363                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1540703                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1540703                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1555678                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1555678                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3728455                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3728455                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3677227                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3677227                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    295373882                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    295373882                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    296914585                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    296914585                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060920                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060920                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080552                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080552                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755598                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.755598                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791416                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.791416                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119783                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119783                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data     20700639                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20700639                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21864409                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21864409                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 165615263000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 165615263000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 435458645679                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 435458645679                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  89047451888                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  89047451888                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6832433500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6832433500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       275500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       275500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 601073908679                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 601073908679                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 601073908679                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 601073908679                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    156185742                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    156185742                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    138987899                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    138987899                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1541053                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1541053                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1555673                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1555673                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3727285                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3727285                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3676016                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3676016                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    295173641                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    295173641                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    296714694                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    296714694                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060868                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.060868                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080539                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080539                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755178                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.755178                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791659                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791659                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119688                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119688                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070164                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070164                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073721                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073721                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17454.269137                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17454.269137                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38894.088562                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38894.088562                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72497.431046                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72497.431046                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15322.830414                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15322.830414                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55300                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55300                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29044.354992                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29044.354992                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27499.635981                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27499.635981                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     49670570                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070130                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070130                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073688                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073688                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17420.926748                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17420.926748                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38901.235942                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38901.235942                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72304.481535                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72304.481535                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15315.511576                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15315.511576                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55100                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55100                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29036.490549                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29036.490549                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27490.974427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27490.974427                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     49516087                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1593951                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1592102                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.161918                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.101077                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7468918                       # number of writebacks
-system.cpu.dcache.writebacks::total           7468918                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4425833                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4425833                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9207187                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9207187                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7019                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         7019                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219274                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       219274                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13633020                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13633020                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13633020                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13633020                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5095341                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5095341                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1996286                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1996286                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1157368                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1157368                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224169                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1224169                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227332                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       227332                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      7469877                       # number of writebacks
+system.cpu.dcache.writebacks::total           7469877                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4421127                       # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6981                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         6981                       # number of WriteLineReq MSHR hits
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total       218536                       # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total     13619474                       # number of overall MSHR hits
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+system.cpu.dcache.SoftPFReq_mshr_misses::total      1156964                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224581                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1224581                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227576                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       227576                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7091627                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7091627                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8248995                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8248995                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7081165                       # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total      8238129                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  83980884000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  83980884000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  76343937421                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  76343937421                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22998470000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22998470000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  87650245635                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  87650245635                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3191570000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3191570000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       271500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       271500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160324821421                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 160324821421                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183323291421                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 183323291421                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5829051500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5829051500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5836628967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5836628967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11665680467                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11665680467                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032602                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032602                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751195                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751195                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786904                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786904                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060972                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060972                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  83741631500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  83741631500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  76263176167                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  76263176167                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22882989500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22882989500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  87447550388                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  87447550388                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3189935000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3189935000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       270500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       270500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160004807667                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 160004807667                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182887797167                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182887797167                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192854000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192854000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228264964                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228264964                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12421118964                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12421118964                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032561                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032561                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014358                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014358                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.750762                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.750762                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787171                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787171                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061057                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061057                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024009                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024009                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027782                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027782                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16481.896697                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16481.896697                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38242.985935                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38242.985935                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19871.354660                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19871.354660                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71599.791887                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71599.791887                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14039.246564                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14039.246564                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54300                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54300                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22607.621836                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22607.621836                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22223.712273                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22223.712273                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173081.878378                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173081.878378                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173214.297454                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173214.297454                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173148.105605                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 173148.105605                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023990                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.023990                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027764                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027764                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16466.557160                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16466.557160                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38215.528492                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38215.528492                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19778.480143                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19778.480143                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71410.180615                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71410.180615                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14017.009702                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14017.009702                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54100                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54100                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22595.831006                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22595.831006                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22200.161853                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22200.161853                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183884.256785                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183884.256785                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184836.923196                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184836.923196                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184360.717250                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184360.717250                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15000702                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.916861                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           339450182                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15001214                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.628181                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       24732660500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.916861                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          14982836                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.916862                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           339236129                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          14983348                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.640876                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       24730722500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.916862                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999838                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999838                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         370220442                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        370220442                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    339450182                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       339450182                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     339450182                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        339450182                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    339450182                       # number of overall hits
-system.cpu.icache.overall_hits::total       339450182                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15768830                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15768830                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15768830                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15768830                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15768830                       # number of overall misses
-system.cpu.icache.overall_misses::total      15768830                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 212844795884                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 212844795884                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 212844795884                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 212844795884                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 212844795884                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 212844795884                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    355219012                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    355219012                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    355219012                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    355219012                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    355219012                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    355219012                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044392                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044392                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044392                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044392                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044392                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044392                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13497.817903                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13497.817903                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13497.817903                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13497.817903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13497.817903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13497.817903                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        22619                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         369968151                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        369968151                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    339236129                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       339236129                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     339236129                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        339236129                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    339236129                       # number of overall hits
+system.cpu.icache.overall_hits::total       339236129                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst     15748452                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total      15748452                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst     15748452                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total       15748452                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst     15748452                       # number of overall misses
+system.cpu.icache.overall_misses::total      15748452                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 212811738878                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 212811738878                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 212811738878                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 212811738878                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 212811738878                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 212811738878                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    354984581                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    354984581                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    354984581                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    354984581                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    354984581                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    354984581                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044364                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.044364                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.044364                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.044364                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.044364                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.044364                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13513.184590                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13513.184590                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13513.184590                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13513.184590                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        22549                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1385                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1395                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.331408                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.164158                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       767400                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       767400                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       767400                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       767400                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       767400                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       767400                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15001430                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15001430                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15001430                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15001430                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15001430                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15001430                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total        21295                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total        21295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190561779393                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 190561779393                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190561779393                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 190561779393                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190561779393                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 190561779393                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684494000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684494000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684494000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   2684494000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042231                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042231                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042231                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.042231                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042231                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.042231                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12702.907616                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12702.907616                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12702.907616                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12702.907616                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12702.907616                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12702.907616                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126062.174219                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126062.174219                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126062.174219                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126062.174219                       # average overall mshr uncacheable latency
+system.cpu.icache.writebacks::writebacks     14982836                       # number of writebacks
+system.cpu.icache.writebacks::total          14982836                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       764882                       # number of ReadReq MSHR hits
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+system.cpu.icache.demand_mshr_hits::total       764882                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::total       764882                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     14983570                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     14983570                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     14983570                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     14983570                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     14983570                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     14983570                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190589950887                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 190589950887                       # number of ReadReq MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 190589950887                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042209                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.042209                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for overall accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12719.929288                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1125228                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65275.787267                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           45935367                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1186879                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.702654                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      22917959500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37021.466735                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   280.855675                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   393.338533                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8151.985016                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19428.141309                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.564903                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004286                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124389                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.296450                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996029                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          269                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61382                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          269                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          550                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2696                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5155                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52911                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004105                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.936615                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        407946828                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       407946828                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       779449                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       298283                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1077732                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7468918                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7468918                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9287                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9287                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.replacements          1120546                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65234.831512                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           45882504                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1182138                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            38.813154                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      22908442500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37014.981518                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   292.089334                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   422.524862                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8026.847283                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        61297                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          295                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2697                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5154                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52826                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.935318                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1568942                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14917877                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14917877                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6228350                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6228350                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       729417                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       729417                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       779449                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::total       23792901                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3205                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3074                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6279                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        33824                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        33824                       # number of UpgradeReq misses
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+system.cpu.l2cache.overall_hits::total       23768957                       # number of overall hits
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+system.cpu.l2cache.UpgradeReq_misses::cpu.data        33876                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total        33876                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       387344                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       387344                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83351                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        83351                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       248584                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       248584                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       494751                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       494751                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         3205                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         3074                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        83351                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::total        725558                       # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::cpu.itb.walker         3074                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        83351                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       635928                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       725558                       # number of overall misses
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+system.cpu.l2cache.ReadSharedReq_misses::total       246229                       # number of ReadSharedReq misses
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+system.cpu.l2cache.InvalidateReq_misses::total       493187                       # number of InvalidateReq misses
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+system.cpu.l2cache.UpgradeReq_miss_latency::total   1421351500                       # number of UpgradeReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::total  11215140000                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.InvalidateReq_miss_latency::total  76701730500                       # number of InvalidateReq miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.inst  11215140000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  88275361500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 100360996500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       782654                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       301357                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1084011                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      7468918                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      7468918                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43111                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        43111                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  53670750500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  53670750500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11020841000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total  11020841000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  34201430000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  34201430000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  76472888000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.InvalidateReq_miss_latency::total  76472888000                       # number of InvalidateReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    444507000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    436877000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  11020841000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  87872180500                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    444507000                       # number of overall miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.inst  11020841000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  87872180500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  99774405500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       782431                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_accesses::total      1084275                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      7469877                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      7469877                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     14980289                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     14980289                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43248                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        43248                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1956286                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1956286                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15001228                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     15001228                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6476934                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224168                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1224168                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       782654                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       782654                       # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.inst     15001228                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      8433220                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     24518459                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004095                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010201                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.005792                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.784579                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.784579                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224581                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1224581                       # number of InvalidateReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010515                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.005884                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.783296                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783296                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.198000                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.198000                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005556                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005556                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038380                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038380                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.404153                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.404153                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004095                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010201                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005556                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.075407                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.029592                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004095                       # miss rate for overall accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005556                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.075407                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.029592                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138052.262090                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139244.469746                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 138635.929288                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41891.851939                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41891.851939                       # average UpgradeReq miss latency
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+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402739                       # miss rate for InvalidateReq accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137642.407057                       # average ReadReq miss latency
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41957.477270                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138804.456762                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138804.456762                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134553.154731                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134553.154731                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138827.470795                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138827.470795                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155030.976188                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155030.976188                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138052.262090                       # average overall miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138813.452938                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 138322.500062                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138052.262090                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139244.469746                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134553.154731                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138813.452938                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 138322.500062                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138807.494258                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134607.335662                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134607.335662                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138900.901194                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138900.901194                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155058.604546                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155058.604546                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 138356.690596                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 138356.690596                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1512,200 +1513,201 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       945403                       # number of writebacks
-system.cpu.l2cache.writebacks::total           945403                       # number of writebacks
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           20                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           20                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           20                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           20                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           20                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           20                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3205                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3074                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6279                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1050                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1050                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33824                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        33824                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks       943662                       # number of writebacks
+system.cpu.l2cache.writebacks::total           943662                       # number of writebacks
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           19                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           19                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           19                       # number of overall MSHR hits
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+system.cpu.l2cache.ReadReq_mshr_misses::total         6380                       # number of ReadReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33876                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        33876                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       387344                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       387344                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83351                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83351                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       248564                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       248564                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       494751                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       494751                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3205                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3074                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        83351                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       635908                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       725538                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3205                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3074                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        83351                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       635908                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       725538                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
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+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        81874                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        81874                       # number of ReadCleanReq MSHR misses
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+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       246210                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       493187                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       493187                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3206                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3174                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        81874                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3206                       # number of overall MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.inst        81874                       # number of overall MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54973                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88669                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    410407500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    397297500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    807705000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2393374500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2393374500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    817584000                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2397445500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49891633500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49891633500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10381630000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10381630000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  32021997500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  32021997500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  71754220500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  71754220500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    410407500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    397297500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10381630000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  81913631000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  93102966000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    410407500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    397297500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10381630000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  81913631000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  93102966000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418306500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5408063000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7826369500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5444622000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5444622000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418306500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10852685000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13270991500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004095                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010201                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005792                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49804190500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49804190500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10202101000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10202101000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31736616500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31736616500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  71541018000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  71541018000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    405137000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10202101000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  81540807000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  92560492000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10202101000                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5771724000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8190487000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836234500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836234500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607958500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14026721500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005884                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784579                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784579                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783296                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783296                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.198000                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.198000                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005556                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005556                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038377                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038377                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.404153                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.404153                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004095                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010201                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005556                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.075405                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.029592                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004095                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010201                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005556                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.075405                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.029592                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129244.469746                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128635.929288                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70759.652909                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70759.652909                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.197723                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.197723                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005464                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038072                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038072                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402739                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402739                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.029445                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.029445                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128147.962382                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70771.209706                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70771.209706                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128804.456762                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128804.456762                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124553.154731                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124553.154731                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128827.977905                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128827.977905                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145030.976188                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145030.976188                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129244.469746                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124553.154731                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128813.650717                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128322.659874                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129244.469746                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124553.154731                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128813.650717                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128322.659874                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160581.477522                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142367.516781                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161580.662393                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161580.662393                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161081.203432                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149668.897811                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128807.494258                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128807.494258                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124607.335662                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128900.599082                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128900.599082                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145058.604546                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145058.604546                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171379.654374                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148993.796842                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173202.590812                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173202.590812                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172291.366106                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158193.728290                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     50050277                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     25391485                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3463                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2168                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2168                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     49994853                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     25364266                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3498                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2149                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2149                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1617253                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23096406                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1617841                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23069110                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8520965                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     17374022                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43114                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8520195                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     14980289                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2361594                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43251                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43119                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1956286                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1956286                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     15001430                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6485775                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1330832                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1224168                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45043419                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29192673                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       728958                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1917333                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          76882383                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    960419312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1017977630                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2410856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6261232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1987069030                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1835462                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     52366647                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.013365                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.114833                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43256                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1955542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1955542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     14983570                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6475758                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1331245                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1224581                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     44989806                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29161893                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       729252                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1917892                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          76798843                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1918014176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1017349854                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2414752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6259448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2944038230                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1831110                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     27676926                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025201                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.156737                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           51666749     98.66%     98.66% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             699898      1.34%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           26979426     97.48%     97.48% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             697500      2.52%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       52366647                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    32990991996                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       27676926                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    47946942997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1490388                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1474889                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22530796241                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22505485675                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13336103780                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13321051501                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     427917846                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     427763271                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1135029759                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1135810761                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40289                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40289                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40286                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40286                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1724,11 +1726,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230936                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230936                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230930                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230930                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353720                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353714                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1745,104 +1747,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492096                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492072                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41870500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25173000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              168500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            36497500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              129000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565927033                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           565751099                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               44500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147696000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147690000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115449                       # number of replacements
-system.iocache.tags.tagsinuse               10.422254                       # Cycle average of tags in use
+system.iocache.tags.replacements               115446                       # number of replacements
+system.iocache.tags.tagsinuse               10.422238                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115465                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115462                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13103107121000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.543889                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.878365                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221493                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429898                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651391                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13103145499000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.543896                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.878342                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221494                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429896                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651390                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039569                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039569                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039542                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039542                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8804                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8841                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8801                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8838                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8804                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8844                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8801                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8841                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8804                       # number of overall misses
-system.iocache.overall_misses::total             8844                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5106000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1685439007                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1690545007                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8801                       # number of overall misses
+system.iocache.overall_misses::total             8841                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1693888006                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1698957506                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13827154026                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13827154026                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5457000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1685439007                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1690896007                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5457000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1685439007                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1690896007                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13866022593                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13866022593                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1693888006                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1699308506                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1693888006                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1699308506                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8804                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8841                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8801                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8838                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8804                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8844                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8801                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8841                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8804                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8844                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8801                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8841                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1856,55 +1858,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       138000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 191440.141640                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 191216.492139                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 192465.402341                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 192233.254809                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129632.809814                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129632.809814                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       136425                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 191440.141640                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 191191.316938                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       136425                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 191440.141640                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 191191.316938                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34672                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129997.211740                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129997.211740                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 192207.726049                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 192207.726049                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         36226                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3494                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3621                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.923297                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.004419                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8804                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8841                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8801                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8838                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8804                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8844                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8801                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8841                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8804                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8844                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3256000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1245239007                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1248495007                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8801                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8841                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1253838006                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1257057506                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8493954026                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8493954026                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3457000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1245239007                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1248696007                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3457000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1245239007                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1248696007                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8532822593                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8532822593                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1253838006                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1257258506                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1253838006                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1257258506                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1918,73 +1920,73 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        88000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141440.141640                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 141216.492139                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142465.402341                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 142233.254809                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79632.809814                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79632.809814                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        86425                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 141440.141640                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 141191.316938                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        86425                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 141440.141640                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 141191.316938                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79997.211740                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79997.211740                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54973                       # Transaction distribution
-system.membus.trans_dist::ReadResp             402008                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
+system.membus.trans_dist::ReadResp             398274                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::Writeback           1052033                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           186512                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34605                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1050292                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           182485                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34687                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           34608                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            881317                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           881317                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        347035                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           34690                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            879035                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           879035                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        343302                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3680509                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3810131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342394                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342394                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4152525                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3662907                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3792527                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342336                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342336                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4134863                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    138873356                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    139043342                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7266048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7266048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               146309390                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2606                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2698981                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    138377164                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    138547134                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7264192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               145811326                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2632                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2687314                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2698981    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2687314    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2698981                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           104149000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2687314                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103976500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               33000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               32000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5470500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5452000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7144084722                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7124848125                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6645299856                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6613283400                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228305891                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227684837                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index a0d86b26c..b4e7404dd 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,170 +1,170 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.395178                       # Number of seconds simulated
-sim_ticks                                47395178174000                       # Number of ticks simulated
-final_tick                               47395178174000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.314506                       # Number of seconds simulated
+sim_ticks                                47314506373000                       # Number of ticks simulated
+final_tick                               47314506373000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  85380                       # Simulator instruction rate (inst/s)
-host_op_rate                                   100389                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4378207332                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 733200                       # Number of bytes of host memory used
-host_seconds                                 10825.25                       # Real time elapsed on the host
-sim_insts                                   924259255                       # Number of instructions simulated
-sim_ops                                    1086731985                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  99848                       # Simulator instruction rate (inst/s)
+host_op_rate                                   117399                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5125940674                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 814164                       # Number of bytes of host memory used
+host_seconds                                  9230.40                       # Real time elapsed on the host
+sim_insts                                   921635123                       # Number of instructions simulated
+sim_ops                                    1083644532                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       173952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       172224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          5051936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         46751112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     21558016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       154688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       128576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2266144                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         13742800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     14572608                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        453056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            105025112                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      5051936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2266144                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7318080                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     87763520                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       141824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       130048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4236960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         43669256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     19384064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       193856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       178880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3171232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         16700240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     15629760                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        443968                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            103880088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4236960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3171232                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7408192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     86326016                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          87784104                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2718                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2691                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             94889                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            730499                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       336844                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2417                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2009                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             35452                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            214744                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       227697                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           7079                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1657039                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1371305                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          86346600                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2216                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2032                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             82155                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            682345                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       302876                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3029                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2795                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             49594                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            260954                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       244215                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6937                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1639148                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1348844                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1373879                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3670                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          3634                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              106592                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              986411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       454857                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2713                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               47814                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              289962                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       307470                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9559                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2215945                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         106592                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          47814                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             154406                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1851739                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1351418                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2997                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2749                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               89549                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              922957                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       409685                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          4097                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3781                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               67025                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              352962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       330338                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9383                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2195523                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          89549                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          67025                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             156573                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1824515                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1852174                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1851739                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3670                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         3634                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             106592                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             986845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       454857                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2713                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              47814                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             289962                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       307470                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9559                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4068119                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1657039                       # Number of read requests accepted
-system.physmem.writeReqs                      1373879                       # Number of write requests accepted
-system.physmem.readBursts                     1657039                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1373879                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                106020736                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     29760                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  87783296                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 105025112                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               87784104                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      465                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1824950                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1824515                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2997                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2749                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              89549                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             923392                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       409685                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         4097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3781                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              67025                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             352962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       330338                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9383                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4020473                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1639148                       # Number of read requests accepted
+system.physmem.writeReqs                      1351418                       # Number of write requests accepted
+system.physmem.readBursts                     1639148                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1351418                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                104871744                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     33728                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  86344960                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 103880088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               86346600                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      527                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         224488                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              100246                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              102501                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               99063                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              111016                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              103342                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              111704                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              101938                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              100431                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               95106                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              125245                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             101573                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             106068                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              95582                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             100418                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             101028                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             101313                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               83566                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               87156                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               83944                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               90509                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               85224                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               91500                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               84276                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               85215                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               82233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               88133                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              85317                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              88722                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              80882                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              85628                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              84824                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              84485                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         532498                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              106578                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              104344                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              100892                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              102125                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              100013                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              109287                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              101103                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               99682                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               97394                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              128253                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              98226                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              99141                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              97088                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             102696                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              95500                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              96299                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               86551                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               88756                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               83871                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               85066                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               83226                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               90269                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               84251                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               84163                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               81439                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               87752                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              80936                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              83767                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              81736                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              86099                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              79882                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              81376                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47395176675500                       # Total gap between requests
+system.physmem.numWrRetry                          31                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47314504873500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1635681                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1617790                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1371305                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    618737                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    421038                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    166212                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    166706                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    103650                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     63464                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     34359                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     32178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     28455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      8186                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::12                     1852                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17                      434                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      150                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1348844                       # Write request sizes (log2)
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+system.physmem.rdQLenPdf::19                       99                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::21                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -188,178 +188,183 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::58                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       71                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       34                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1046566                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      185.180531                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     114.222366                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     242.012748                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         630659     60.26%     60.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       204416     19.53%     79.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        66292      6.33%     86.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        36110      3.45%     89.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        25913      2.48%     92.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        14303      1.37%     93.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        14388      1.37%     94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7964      0.76%     95.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        46521      4.45%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1046566                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         78027                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.230689                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      247.022438                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          78024    100.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::1024-1151        46290      4.36%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1061449                       # Bytes accessed per row activation
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 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::65536-69631            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           78027                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         78027                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.578710                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.107570                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.499017                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           72603     93.05%     93.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            2990      3.83%     96.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             480      0.62%     97.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             334      0.43%     97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              81      0.10%     98.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             301      0.39%     98.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             173      0.22%     98.64% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::48-51              88      0.11%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             126      0.16%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              37      0.05%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              56      0.07%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             406      0.52%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              31      0.04%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              24      0.03%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             123      0.16%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              13      0.02%     99.93% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::96-99               5      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.94% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            17      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.00%    100.00% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::236-239             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           78027                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    82234419314                       # Total ticks spent queuing
-system.physmem.totMemAccLat              113295181814                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8282870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       49641.26                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           76381                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         76381                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.663293                       # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::16-19           70865     92.78%     92.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            3094      4.05%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             460      0.60%     97.43% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::124-127             4      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            25      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           76381                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    70826288095                       # Total ticks spent queuing
+system.physmem.totMemAccLat              101550431845                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8193105000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       43223.11                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  68391.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.24                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.22                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  61973.11                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.22                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.82                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.20                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.82                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.27                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.73                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1332435                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    649185                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.43                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  47.33                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15637234.88                       # Average gap between requests
-system.physmem.pageHitRate                      65.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4004169120                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2184814500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6475833000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4480207200                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3095622519600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1180796903550                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27401319159750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31694883606720                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.736482                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45584100048214                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582629100000                       # Time in different power states
+system.physmem.avgRdQLen                         1.33                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.65                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1314681                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    611629                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.23                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  45.33                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15821254.20                       # Average gap between requests
+system.physmem.pageHitRate                      64.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4090980600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2232181875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6427387200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4446271440                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3090353329440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1181376195975                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27352407006750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31641333353280                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.744914                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45502947755010                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1579935240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    228448334286                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    231620211240                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3907869840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2132270250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6445397400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4407851520                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3095622519600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1181668397355                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27400554691500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31694738997465                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.733431                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45582807436264                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582629100000                       # Time in different power states
+system.physmem_1.actEnergy                 3933573840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2146295250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6353809800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4296155760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3090353329440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1178540083170                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27354894825000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31640518072260                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.727683                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45507092069935                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1579935240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    229740006236                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    227478372065                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu0.inst          384                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           572                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst          384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_read::total           556                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst          368                       # Number of instructions bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          528                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
+system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst           23                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             39                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
@@ -379,15 +384,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              146971248                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         97492286                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          7372479                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups           103605243                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               68020426                       # Number of BTB hits
+system.cpu0.branchPred.lookups              132773230                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         87983669                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6601963                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            93351299                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               61553732                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            65.653459                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               20148210                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            220615                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            65.937735                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               18245658                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            197691                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -418,88 +423,85 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   621589                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               621589                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        13120                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        97816                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       286624                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       334965                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2330.974878                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 14719.833023                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       332297     99.20%     99.20% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1432      0.43%     99.63% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          943      0.28%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          131      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           57      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           84      0.03%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           13      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                   574649                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               574649                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        12370                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88781                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       269295                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       305354                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2428.535405                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 14847.246962                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       302828     99.17%     99.17% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1395      0.46%     99.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          849      0.28%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          146      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           44      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           73      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           14      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::458752-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       334965                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       317874                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 20050.667875                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 16636.288203                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 22186.320011                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       314157     98.83%     98.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          825      0.26%     99.09% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         2043      0.64%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          147      0.05%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          407      0.13%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215          108      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751          100      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           42      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823           23      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::720896-786431            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       317874                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 575732613804                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.609948                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.538779                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 574368413804     99.76%     99.76% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    774580000      0.13%     99.90% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    276702000      0.05%     99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7    125012500      0.02%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9     99386000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     49877000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     16787500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     21052000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       785500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19        17500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 575732613804                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        97816     88.17%     88.17% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        13120     11.83%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       110936                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       621589                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total       305354                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       295785                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 20483.935967                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17662.897721                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 19270.228379                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       292925     99.03%     99.03% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          638      0.22%     99.25% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1609      0.54%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          142      0.05%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          290      0.10%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           80      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           60      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           29      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       295785                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 533721818468                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.601728                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.544409                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 532429522968     99.76%     99.76% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    722596500      0.14%     99.89% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    256398500      0.05%     99.94% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    121663500      0.02%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9     95265000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     53651000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     19676500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     22307000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       728500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19         9000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 533721818468                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        88781     87.77%     87.77% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        12370     12.23%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       101151                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       574649                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       621589                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       110936                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       574649                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       101151                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       110936                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       732525                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       101151                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       675800                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   106854280                       # DTB read hits
-system.cpu0.dtb.read_misses                    451291                       # DTB read misses
-system.cpu0.dtb.write_hits                   87452638                       # DTB write hits
-system.cpu0.dtb.write_misses                   170298                       # DTB write misses
+system.cpu0.dtb.read_hits                    96498807                       # DTB read hits
+system.cpu0.dtb.read_misses                    413728                       # DTB read misses
+system.cpu0.dtb.write_hits                   78559139                       # DTB write hits
+system.cpu0.dtb.write_misses                   160921                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              44894                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   41576                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      658                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  7382                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              44695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   38359                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      510                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  7352                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    40291                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               107305571                       # DTB read accesses
-system.cpu0.dtb.write_accesses               87622936                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    37571                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                96912535                       # DTB read accesses
+system.cpu0.dtb.write_accesses               78720060                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        194306918                       # DTB hits
-system.cpu0.dtb.misses                         621589                       # DTB misses
-system.cpu0.dtb.accesses                    194928507                       # DTB accesses
+system.cpu0.dtb.hits                        175057946                       # DTB hits
+system.cpu0.dtb.misses                         574649                       # DTB misses
+system.cpu0.dtb.accesses                    175632595                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -529,1172 +531,1177 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    88821                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                88821                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1050                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        63713                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        10161                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        78660                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1640.999237                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 13001.605750                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        77771     98.87%     98.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          446      0.57%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303           46      0.06%     99.50% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071           60      0.08%     99.57% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839          236      0.30%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           63      0.08%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            4      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            4      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911           12      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks                    78486                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                78486                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          887                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        55688                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         9272                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        69214                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1487.228017                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 11268.156243                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        68484     98.95%     98.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          441      0.64%     99.58% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303           31      0.04%     99.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071           33      0.05%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839          145      0.21%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           56      0.08%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        78660                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        74924                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26158.080188                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 21735.719179                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 28586.196281                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        72785     97.15%     97.15% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          128      0.17%     97.32% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         1706      2.28%     99.59% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143          120      0.16%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679          108      0.14%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           38      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           23      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        74924                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 438261516832                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.857100                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.350244                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    62664607652     14.30%     14.30% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   375564750680     85.69%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       27774000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        4139500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walkWaitTime::total        69214                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        65847                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26575.804517                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 22865.862438                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 26620.164914                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        64258     97.59%     97.59% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          112      0.17%     97.76% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607         1232      1.87%     99.63% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           99      0.15%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           79      0.12%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           35      0.05%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           19      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287           11      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        65847                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 404869617088                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.839049                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.367685                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    65190904252     16.10%     16.10% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   339654890336     83.89%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       21211000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        2423500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::4         188000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          57000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 438261516832                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        63713     98.38%     98.38% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         1050      1.62%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        64763                       # Table walker page sizes translated
+system.cpu0.itb.walker.walksPending::total 404869617088                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        55688     98.43%     98.43% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          887      1.57%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        56575                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        88821                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        88821                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        78486                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        78486                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        64763                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        64763                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       153584                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   231690538                       # ITB inst hits
-system.cpu0.itb.inst_misses                     88821                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        56575                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        56575                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       135061                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   209228100                       # ITB inst hits
+system.cpu0.itb.inst_misses                     78486                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              44894                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   30101                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              44695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   27529                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   229340                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   202656                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               231779359                       # ITB inst accesses
-system.cpu0.itb.hits                        231690538                       # DTB hits
-system.cpu0.itb.misses                          88821                       # DTB misses
-system.cpu0.itb.accesses                    231779359                       # DTB accesses
-system.cpu0.numCycles                       863793222                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               209306586                       # ITB inst accesses
+system.cpu0.itb.hits                        209228100                       # DTB hits
+system.cpu0.itb.misses                          78486                       # DTB misses
+system.cpu0.itb.accesses                    209306586                       # DTB accesses
+system.cpu0.numCycles                       789288757                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          99193613                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     650316460                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  146971248                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          88168636                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    710473999                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               15870286                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2085677                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              375453                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      6582690                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       821108                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       973136                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                231460528                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1900058                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  29560                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         828440819                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.919217                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.204961                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          88186567                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     587222731                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  132773230                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          79799390                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    653950437                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               14236776                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   1849931                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              326899                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      5945958                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       775108                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       835772                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                209027134                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1689441                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  26384                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         758989060                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.905560                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.200949                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               463819781     55.99%     55.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               141489715     17.08%     73.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                49366419      5.96%     79.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               173764904     20.97%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               429796828     56.63%     56.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               127839256     16.84%     73.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                44588296      5.87%     79.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               156764680     20.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           828440819                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.170146                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.752861                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               116939951                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            422028211                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                244586455                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             39268558                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5617644                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            21189817                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2362286                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             672848975                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             25418616                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5617644                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               154577177                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               70595603                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     261705373                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                245642920                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             90302102                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             654266166                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              6467849                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents             11101204                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                403453                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                928162                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              53323892                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           11721                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          625141147                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups           1009026275                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       772228505                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           892399                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            562735066                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                62406074                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          16247606                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      14088158                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 79534921                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           107241964                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           91079408                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          9519471                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         8265411                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 630985849                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           16282634                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                634912655                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2916139                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       58420750                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     38187791                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        288602                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    828440819                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.766395                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.051588                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           758989060                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.168219                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.743990                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               104466806                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            394260374                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                219139619                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             36084867                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5037394                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19164568                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2120604                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             606612799                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             22830363                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5037394                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               138662412                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               63104555                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     247113571                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                220473798                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             84597330                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             589875332                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              5798642                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             10641909                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                381250                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                853231                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              50687884                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           10092                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          564041119                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            911558490                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       696481853                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           699850                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            508008632                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                56032481                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          14857922                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      12905611                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 72985645                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            96647129                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           81788442                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          8697028                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         7422933                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 568689811                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           14912069                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                572654206                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2621739                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       52458189                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     34404562                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        258659                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    758989060                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.754496                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.046900                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          482464203     58.24%     58.24% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          143786503     17.36%     75.59% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          123657330     14.93%     90.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           70325398      8.49%     99.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            8201627      0.99%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               5758      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          446419238     58.82%     58.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          130584028     17.20%     76.02% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          111330924     14.67%     90.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           63215854      8.33%     99.02% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            7434312      0.98%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               4704      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      828440819                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      758989060                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               65751499     45.58%     45.58% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 72629      0.05%     45.63% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  24296      0.02%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              30      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.64% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              37784970     26.19%     71.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             40630472     28.16%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               59334745     45.62%     45.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 61701      0.05%     45.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  15638      0.01%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              17      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              34211739     26.30%     71.98% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             36440950     28.02%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            434162938     68.38%     68.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1557110      0.25%     68.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                85116      0.01%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  3      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         85507      0.01%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           110176891     17.35%     86.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           88845090     13.99%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            391815865     68.42%     68.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1438003      0.25%     68.67% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                75602      0.01%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         42288      0.01%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            99488891     17.37%     86.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           79793556     13.93%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             634912655                       # Type of FU issued
-system.cpu0.iq.rate                          0.735029                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  144263896                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.227218                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2243978291                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        705234549                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    616677073                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1467869                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            599303                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       545442                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             778270494                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 906057                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2895519                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             572654206                       # Type of FU issued
+system.cpu0.iq.rate                          0.725532                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  130064790                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.227126                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2035873022                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        635743875                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    556160378                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1110977                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            443650                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       409772                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             702028683                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 690312                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2617659                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     13298175                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        18246                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       145606                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      6202009                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     11976787                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        15696                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       128509                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      5549515                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2767326                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      4824800                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2485031                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4622903                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5617644                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                8735359                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              7907130                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          647396791                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5037394                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                7963594                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              7170717                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          583715188                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            107241964                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            91079408                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13794371                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 59022                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              7772545                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        145606                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2195305                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      3186569                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5381874                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            626447733                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            106847652                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          7850968                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             96647129                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            81788442                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          12627210                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 54569                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              7047111                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        128509                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       1976888                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2838838                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4815726                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            565090405                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             96493854                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          6996299                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       128308                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   194298385                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               118240799                       # Number of branches executed
-system.cpu0.iew.exec_stores                  87450733                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.725229                       # Inst execution rate
-system.cpu0.iew.wb_sent                     618051464                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    617222515                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                300479191                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                493067457                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       113308                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   175051410                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               106737211                       # Number of branches executed
+system.cpu0.iew.exec_stores                  78557556                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.715949                       # Inst execution rate
+system.cpu0.iew.wb_sent                     557331942                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    556570150                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                270940614                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                444738310                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.714549                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609408                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.705154                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609214                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       50926327                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15994032                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          5054980                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    818740070                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.719212                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.525829                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       45776609                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       14653410                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4520969                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    750266004                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.707940                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.517135                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    561213375     68.55%     68.55% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    132109065     16.14%     84.68% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     58113446      7.10%     91.78% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     19548895      2.39%     94.17% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     13854430      1.69%     95.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      9447713      1.15%     97.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6268110      0.77%     97.78% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3880157      0.47%     98.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     14304879      1.75%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    517711139     69.00%     69.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    119807975     15.97%     84.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     52242096      6.96%     91.94% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     17345693      2.31%     94.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     12502849      1.67%     95.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      8569717      1.14%     97.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      5628818      0.75%     97.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3480187      0.46%     98.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     12977530      1.73%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    818740070                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           501771314                       # Number of instructions committed
-system.cpu0.commit.committedOps             588847718                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    750266004                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           452897446                       # Number of instructions committed
+system.cpu0.commit.committedOps             531143684                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     178821180                       # Number of memory references committed
-system.cpu0.commit.loads                     93943789                       # Number of loads committed
-system.cpu0.commit.membars                    3938709                       # Number of memory barriers committed
-system.cpu0.commit.branches                 112215548                       # Number of branches committed
-system.cpu0.commit.fp_insts                    531565                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                540152053                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            14962116                       # Number of function calls committed.
+system.cpu0.commit.refs                     160909268                       # Number of memory references committed
+system.cpu0.commit.loads                     84670341                       # Number of loads committed
+system.cpu0.commit.membars                    3612111                       # Number of memory barriers committed
+system.cpu0.commit.branches                 101352463                       # Number of branches committed
+system.cpu0.commit.fp_insts                    401266                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                487082373                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13540419                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       408576800     69.39%     69.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1307130      0.22%     69.61% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           67517      0.01%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.62% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        75091      0.01%     69.63% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.63% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.63% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.63% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       93943789     15.95%     85.59% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      84877391     14.41%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       368934944     69.46%     69.46% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1203387      0.23%     69.69% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           59505      0.01%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.70% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        36580      0.01%     69.71% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.71% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.71% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.71% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       84670341     15.94%     85.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      76238927     14.35%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        588847718                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             14304879                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1439565573                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1289210941                       # The number of ROB writes
-system.cpu0.timesIdled                        1140163                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       35352403                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 93926563172                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  501771314                       # Number of Instructions Simulated
-system.cpu0.committedOps                    588847718                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.721488                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.721488                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.580893                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.580893                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               739095549                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              439787902                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   872002                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  484356                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                137161341                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               137881500                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1443535644                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              16079939                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          6407370                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          508.018138                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          166146345                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          6407881                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            25.928438                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       2962355000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   508.018138                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.992223                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.992223                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          248                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        371124901                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       371124901                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     87218466                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       87218466                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     73809320                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      73809320                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       228978                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       228978                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       263867                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       263867                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1900288                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1900288                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1938762                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1938762                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    161027786                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       161027786                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    161256764                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      161256764                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      7088028                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7088028                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      7798635                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      7798635                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       740346                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       740346                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       850980                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       850980                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       273336                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       273336                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       194663                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       194663                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     14886663                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      14886663                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     15627009                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     15627009                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 124519522000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 124519522000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171455239141                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 171455239141                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 101116390498                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 101116390498                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4428125500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4428125500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4749567500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4749567500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      4799500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      4799500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 295974761141                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 295974761141                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 295974761141                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 295974761141                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     94306494                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     94306494                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     81607955                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     81607955                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       969324                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       969324                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1114847                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1114847                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2173624                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2173624                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2133425                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      2133425                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    175914449                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    175914449                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    176883773                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    176883773                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.075159                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.075159                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.095562                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.095562                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.763776                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.763776                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.763316                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.763316                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.125751                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.125751                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.091244                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.091244                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.084624                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.084624                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.088346                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.088346                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17567.583254                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17567.583254                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21985.288341                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 21985.288341                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118823.462946                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118823.462946                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16200.301095                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16200.301095                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24398.922754                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24398.922754                       # average StoreCondReq miss latency
+system.cpu0.commit.op_class_0::total        531143684                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             12977530                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1309875410                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1162529912                       # The number of ROB writes
+system.cpu0.timesIdled                         987855                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       30299697                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 93839724027                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  452897446                       # Number of Instructions Simulated
+system.cpu0.committedOps                    531143684                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.742754                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.742754                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.573805                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.573805                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               666947650                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              396615179                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   682678                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  298828                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                124079442                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               124706529                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1318525921                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              14734262                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          5881965                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          478.956800                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          149156359                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5882471                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            25.356072                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       2962390000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   478.956800                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.935463                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.935463                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          506                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.988281                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        334047120                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       334047120                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     78452229                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       78452229                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     65886147                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      65886147                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       209885                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       209885                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       258671                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       258671                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1757048                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1757048                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1773588                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1773588                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    144338376                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       144338376                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    144548261                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      144548261                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6459284                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      6459284                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7288144                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7288144                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       689122                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       689122                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       817042                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       817042                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       245228                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       245228                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       193470                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       193470                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     13747428                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      13747428                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     14436550                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     14436550                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110052955500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 110052955500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 170225463786                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 170225463786                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  91498155223                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  91498155223                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3890581500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3890581500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5535454500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5535454500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      8571500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      8571500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 280278419286                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 280278419286                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 280278419286                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 280278419286                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     84911513                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     84911513                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     73174291                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     73174291                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       899007                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       899007                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1075713                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1075713                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2002276                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2002276                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1967058                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1967058                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    158085804                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    158085804                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    158984811                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    158984811                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076071                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.076071                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.099600                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.099600                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766537                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766537                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.759535                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.759535                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.122475                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.122475                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098355                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098355                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086962                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.086962                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.090805                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.090805                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17037.949640                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17037.949640                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23356.490183                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 23356.490183                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111987.089064                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111987.089064                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15865.160177                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15865.160177                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28611.435882                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28611.435882                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19881.874208                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19881.874208                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18939.949490                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18939.949490                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     31639371                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     26128725                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           779388                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         763893                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    40.595148                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    34.204692                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.698651                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20387.698651                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19414.501338                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 19414.501338                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     28857818                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     25701299                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           757026                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         713337                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    38.119983                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    36.029673                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      4315919                       # number of writebacks
-system.cpu0.dcache.writebacks::total          4315919                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3584647                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3584647                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6264689                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      6264689                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4628                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         4628                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       139100                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       139100                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9849336                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      9849336                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9849336                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      9849336                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3503381                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3503381                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1533946                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1533946                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       733362                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       733362                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       846352                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       846352                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       134236                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       134236                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       194661                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       194661                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      5037327                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5037327                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5770689                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5770689                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        33238                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33238                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        33405                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33405                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        66643                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        66643                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  56780867000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  56780867000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  38418617555                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  38418617555                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  19943250500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  19943250500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 100022529998                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 100022529998                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1962249500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1962249500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4554969500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4554969500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      4736500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      4736500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  95199484555                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  95199484555                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115142735055                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 115142735055                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5997592500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5997592500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5944742000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5944742000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11942334500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11942334500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037149                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037149                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018797                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018797                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.756571                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.756571                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.759164                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.759164                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061757                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061757                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.091243                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.091243                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028635                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028635                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032624                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032624                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16207.448462                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16207.448462                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25045.612789                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25045.612789                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27194.278542                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27194.278542                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 118180.768756                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 118180.768756                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14617.908013                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14617.908013                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23399.497074                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23399.497074                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5882015                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5882015                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3286907                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3286907                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5842010                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      5842010                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4476                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         4476                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       122858                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       122858                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9128917                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9128917                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9128917                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9128917                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3172377                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3172377                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1446134                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1446134                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       682277                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       682277                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       812566                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       812566                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       122370                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       122370                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       193461                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       193461                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4618511                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4618511                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5300788                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5300788                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32879                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32879                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        32981                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        32981                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        65860                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        65860                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49995905500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49995905500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39710234771                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  39710234771                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17655223500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17655223500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  90433652723                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  90433652723                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1780369000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1780369000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5342108500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5342108500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      8456500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      8456500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  89706140271                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  89706140271                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 107361363771                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 107361363771                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6303225000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6303225000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   6238855500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6238855500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12542080500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12542080500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037361                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037361                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019763                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019763                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.758923                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.758923                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.755374                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.755374                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061115                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061115                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098350                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098350                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029215                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029215                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.033341                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.033341                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15759.761687                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.761687                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27459.581734                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27459.581734                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25876.914362                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25876.914362                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 111293.916707                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 111293.916707                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14549.064313                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14549.064313                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27613.361349                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27613.361349                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18898.809737                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18898.809737                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19953.030748                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19953.030748                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180443.844395                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180443.844395                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177959.646759                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177959.646759                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179198.633015                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179198.633015                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19423.173458                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19423.173458                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20253.849762                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20253.849762                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191709.753946                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191709.753946                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189165.140535                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189165.140535                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190435.476769                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190435.476769                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          6757482                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.935144                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          224272608                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6757994                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            33.186269                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      22852216000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.935144                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999873                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999873                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          6005225                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.936915                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          202641946                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          6005737                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            33.741395                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      21603135000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.936915                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999877                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999877                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           82                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        469620349                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       469620349                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    224272608                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      224272608                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    224272608                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       224272608                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    224272608                       # number of overall hits
-system.cpu0.icache.overall_hits::total      224272608                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      7158551                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      7158551                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      7158551                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       7158551                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      7158551                       # number of overall misses
-system.cpu0.icache.overall_misses::total      7158551                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  82703845756                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  82703845756                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  82703845756                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  82703845756                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  82703845756                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  82703845756                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    231431159                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    231431159                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    231431159                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    231431159                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    231431159                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    231431159                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.030932                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.030932                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.030932                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.030932                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.030932                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.030932                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11553.154508                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 11553.154508                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11553.154508                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 11553.154508                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11553.154508                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11553.154508                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs     13180342                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets         1608                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           863819                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        424004104                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       424004104                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    202641946                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      202641946                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    202641946                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       202641946                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    202641946                       # number of overall hits
+system.cpu0.icache.overall_hits::total      202641946                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6357218                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6357218                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6357218                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6357218                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6357218                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6357218                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  72002088632                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  72002088632                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  72002088632                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  72002088632                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  72002088632                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  72002088632                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    208999164                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    208999164                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    208999164                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    208999164                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    208999164                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    208999164                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.030417                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.030417                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.030417                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.030417                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.030417                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.030417                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11326.037369                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 11326.037369                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11326.037369                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 11326.037369                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11326.037369                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 11326.037369                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     11168048                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets         1595                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           759109                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets             14                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.258222                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets   114.857143                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.712048                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets   113.928571                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       400520                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       400520                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       400520                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       400520                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       400520                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       400520                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6758031                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6758031                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6758031                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6758031                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6758031                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6758031                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  74295068991                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  74295068991                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  74295068991                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  74295068991                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  74295068991                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  74295068991                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939725498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939725498                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939725498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939725498                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.029201                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.029201                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.029201                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.029201                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.029201                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.029201                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10993.596950                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10993.596950                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10993.596950                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10993.596950                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10993.596950                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10993.596950                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095                       # average overall mshr uncacheable latency
+system.cpu0.icache.writebacks::writebacks      6005225                       # number of writebacks
+system.cpu0.icache.writebacks::total          6005225                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       351442                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       351442                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       351442                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       351442                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       351442                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       351442                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6005776                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      6005776                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6005776                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      6005776                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6005776                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      6005776                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  64732998531                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  64732998531                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  64732998531                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  64732998531                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  64732998531                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  64732998531                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939780998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939780998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939780998                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939780998                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028736                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028736                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028736                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028736                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028736                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028736                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10778.457027                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10778.457027                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10778.457027                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10778.457027                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10778.457027                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10778.457027                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      8609545                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8618519                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         8045                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7993443                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      8002831                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         8432                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1094401                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2903307                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16246.409963                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          22353900                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2918996                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            7.658078                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     21271828500                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  7113.964436                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    80.712375                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    97.665127                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4225.088231                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3888.580421                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   840.399372                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.434202                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004926                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.005961                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.257879                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.237340                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.051294                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.991602                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1391                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           88                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14210                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          134                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          197                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          595                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          461                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            5                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           66                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          745                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4851                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4773                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3664                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.084900                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005371                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.867310                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       448966117                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      448966117                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       605202                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       189837                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        795039                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      4315912                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      4315912                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data       110882                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total       110882                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        36120                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total        36120                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       962986                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       962986                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      6062865                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      6062865                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3276140                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      3276140                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       213470                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       213470                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       605202                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       189837                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      6062865                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      4239126                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       11097030                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       605202                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       189837                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      6062865                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      4239126                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      11097030                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        13783                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10250                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        24033                       # number of ReadReq misses
-system.cpu0.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
-system.cpu0.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       133626                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       133626                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       158531                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       158531                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           10                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total           10                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       336962                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       336962                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       695135                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       695135                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1092519                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1092519                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       631427                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       631427                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        13783                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10250                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       695135                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1429481                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2148649                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        13783                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10250                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       695135                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1429481                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2148649                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    679881500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    586856000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total   1266737500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   4146846499                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   4146846499                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3851336998                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3851336998                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4641499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4641499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  22977113499                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  22977113499                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  27999451498                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  27999451498                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  50408930969                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  50408930969                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  96428495994                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  96428495994                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    679881500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    586856000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  27999451498                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  73386044468                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total 102652233466                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    679881500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    586856000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  27999451498                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  73386044468                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total 102652233466                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       618985                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       200087                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       819072                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      4315913                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      4315913                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       244508                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       244508                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       194651                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       194651                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           10                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           10                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1299948                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1299948                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6758000                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      6758000                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4368659                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      4368659                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       844897                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       844897                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       618985                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       200087                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      6758000                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5668607                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     13245679                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       618985                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       200087                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      6758000                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5668607                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     13245679                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022267                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.051228                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.029342                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.546510                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.546510                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.814437                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.814437                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.prefetcher.pfSpanPage      1016241                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2612055                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15872.009303                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          17309640                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2628171                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.586192                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle      3536776000                       # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14904.546668                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    64.900343                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    63.931766                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   838.630526                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.909701                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003961                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003902                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.051186                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.968751                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1148                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14896                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           19                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          168                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          583                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          378                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           39                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1338                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5968                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4418                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3068                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.070068                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.909180                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       407586755                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      407586755                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       586295                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       178487                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        764782                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3871957                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3871957                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      8013001                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      8013001                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          532                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total          532                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            1                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       876856                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       876856                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5449817                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5449817                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2990512                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2990512                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       195363                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       195363                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       586295                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       178487                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      5449817                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3867368                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       10081967                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       586295                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       178487                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      5449817                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3867368                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      10081967                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11719                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8497                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        20216                       # number of ReadReq misses
+system.cpu0.l2cache.WritebackDirty_misses::writebacks            2                       # number of WritebackDirty misses
+system.cpu0.l2cache.WritebackDirty_misses::total            2                       # number of WritebackDirty misses
+system.cpu0.l2cache.WritebackClean_misses::writebacks            2                       # number of WritebackClean misses
+system.cpu0.l2cache.WritebackClean_misses::total            2                       # number of WritebackClean misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       253056                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       253056                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       193456                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       193456                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       324941                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       324941                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       555934                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       555934                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       984475                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       984475                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       615167                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       615167                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11719                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8497                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       555934                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1309416                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      1885566                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11719                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8497                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       555934                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1309416                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1885566                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    564728500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    467676000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total   1032404500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3400771000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   3400771000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2092190000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2092190000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      8283499                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      8283499                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  22038897500                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  22038897500                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22689432998                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22689432998                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  43523481971                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  43523481971                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  86915383999                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  86915383999                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    564728500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    467676000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22689432998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  65562379471                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  89284216969                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    564728500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    467676000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22689432998                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  65562379471                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  89284216969                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       598014                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       186984                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       784998                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3871959                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      3871959                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      8013003                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      8013003                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       253588                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       253588                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       193457                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       193457                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1201797                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1201797                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6005751                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      6005751                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3974987                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3974987                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       810530                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       810530                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       598014                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       186984                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      6005751                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      5176784                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     11967533                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       598014                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       186984                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      6005751                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      5176784                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total     11967533                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.019597                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.045442                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.025753                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
+system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.997902                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.997902                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999995                       # miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999995                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.259212                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.259212                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.102861                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.102861                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.250081                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.250081                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.747342                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.747342                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022267                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.051228                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.102861                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.252175                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.162215                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022267                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.051228                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.102861                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.252175                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.162215                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 49327.541174                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 57254.243902                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 52708.255316                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31033.230801                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31033.230801                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 24293.904650                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 24293.904650                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 464149.900000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 464149.900000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 68189.034666                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 68189.034666                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40279.156564                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40279.156564                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 46140.095476                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 46140.095476                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 152715.192721                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 152715.192721                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 49327.541174                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 57254.243902                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40279.156564                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 51337.544513                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 47775.245499                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 49327.541174                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 57254.243902                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40279.156564                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 51337.544513                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 47775.245499                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs         4122                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.270379                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.270379                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.092567                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.092567                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.247667                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.247667                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.758969                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.758969                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.019597                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.045442                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.092567                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.252940                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.157557                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.019597                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.045442                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.092567                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.252940                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.157557                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48189.137298                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 55040.131811                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 51068.683221                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13438.808011                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13438.808011                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10814.810603                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10814.810603                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 2070874.750000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2070874.750000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67824.305028                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67824.305028                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40813.177460                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40813.177460                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44209.839733                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44209.839733                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 141287.461777                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 141287.461777                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48189.137298                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 55040.131811                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40813.177460                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50069.939172                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 47351.414360                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48189.137298                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 55040.131811                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40813.177460                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50069.939172                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 47351.414360                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs         3549                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs              26                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs              15                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   158.538462                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   236.600000                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1567709                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1567709                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            6                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          165                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          171                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        67086                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        67086                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            4                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         8307                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         8307                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          165                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            4                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        75393                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        75568                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            6                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          165                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            4                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        75393                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        75568                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        13777                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10085                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        23862                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
-system.cpu0.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks       118847                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total       118847                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       832278                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       832278                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       133626                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       133626                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       158531                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       158531                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           10                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       269876                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       269876                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       695131                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       695131                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1084212                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1084212                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       631427                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       631427                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        13777                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10085                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       695131                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1354088                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      2073081                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        13777                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10085                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       695131                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1354088                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       832278                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2905359                       # number of overall MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21294                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        33238                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        54532                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        33405                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        33405                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21294                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        66643                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        87937                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    597098000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    519597500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1116695500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  67202265861                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  67202265861                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4741207495                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4741207495                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3076689494                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3076689494                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4263499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4263499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  17260521499                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  17260521499                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  23828492498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  23828492498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  43284601971                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  43284601971                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  92639933994                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  92639933994                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    597098000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    519597500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  23828492498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  60545123470                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  85490311468                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    597098000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    519597500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  23828492498                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  60545123470                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  67202265861                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 152692577329                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780019500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5731623000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8511642500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5688753467                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5688753467                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780019500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11420376467                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14200395967                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.022257                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.050403                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.029133                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.writebacks::writebacks      1633377                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1633377                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            5                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          190                       # number of ReadReq MSHR hits
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+system.cpu0.l2cache.ReadExReq_mshr_hits::total        59160                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            2                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         6628                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         6628                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           15                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total           15                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            5                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          190                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        65788                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        65985                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          190                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            2                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        65788                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        65985                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        11714                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8307                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total        20021                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            2                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::total            2                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            2                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::total            2                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       825638                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       825638                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       253056                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       253056                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       193456                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       193456                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
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+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       555932                       # number of ReadCleanReq MSHR misses
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+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       615152                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       615152                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11714                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32879                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        54172                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        32981                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        32981                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        65860                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        87153                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    494096500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    408146000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    902242500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  60235996440                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  60235996440                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7625664494                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7625664494                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3888505997                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3888505997                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      7593499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      7593499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16722004500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16722004500                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  19353809498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  19353809498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  37185118471                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  37185118471                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  83223435999                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  83223435999                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    494096500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    408146000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  19353809498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  53907122971                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  74163174969                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    494096500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    408146000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  19353809498                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  53907122971                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  60235996440                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 134399171409                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780082500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6040017000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8820099500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5985704467                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5985704467                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780082500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  12025721467                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14805803967                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.019588                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.044426                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.025505                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
+system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.546510                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.546510                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.814437                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.814437                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.997902                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.997902                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999995                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999995                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.207605                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.207605                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.102860                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.102860                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.248180                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248180                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.747342                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.747342                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022257                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.050403                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.102860                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.238875                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.156510                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022257                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.050403                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.102860                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.238875                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.221153                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.221153                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.092567                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092567                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.246000                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.246000                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.758950                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.758950                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.019588                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.044426                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.092567                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240232                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.152043                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.019588                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.044426                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.092567                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240232                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.219344                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46798.068058                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80744.974469                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35481.175033                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35481.175033                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19407.494395                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19407.494395                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 426349.900000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 426349.900000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63957.230354                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63957.230354                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34279.139469                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34279.139469                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39922.636875                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39922.636875                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 146715.192721                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 146715.192721                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34279.139469                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44712.842496                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41238.288069                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34279.139469                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44712.842496                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52555.493944                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172441.873759                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156085.280202                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170296.466607                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170296.466607                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171366.482106                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161483.743669                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.221033                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45064.806953                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72956.909009                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30134.296338                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30134.296338                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20100.208818                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20100.208818                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1898374.750000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1898374.750000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62916.478228                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62916.478228                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34813.267626                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34813.267626                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38027.542623                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38027.542623                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 135289.222825                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 135289.222825                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34813.267626                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43346.662323                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40758.380621                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34813.267626                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43346.662323                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50808.334361                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183704.400985                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162816.574983                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181489.477790                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181489.477790                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182595.224218                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169882.895219                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     27252548                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13981170                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2244                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       570842                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       570828                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops           14                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq       1016473                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     12252394                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        33406                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        33405                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      5923375                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict     10861944                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1063583                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       463812                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       352945                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       515465                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           72                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1384026                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1310731                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6758031                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5399513                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       852147                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       844897                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     20314687                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20641650                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       432749                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1348262                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         42737348                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    432852704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    646893668                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1600696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4951880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1086298948                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    6525445                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     34111599                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.027918                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.164740                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests     24664078                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12671171                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2283                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      2001831                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2001348                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          483                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        921539                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     11008242                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        32982                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        32981                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5510686                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      8013020                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2592060                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1056695                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       478539                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       354281                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       520874                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq          100                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          211                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1281558                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1212477                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6005776                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4986753                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       818816                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       810530                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18057865                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19072336                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       391759                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1260604                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         38782564                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    768948880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    715383853                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1495872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4784112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1490612717                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    7046224                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     20167865                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.116092                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.320411                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          33159285     97.21%     97.21% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            952300      2.79%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2                14      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          17827011     88.39%     88.39% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2340371     11.60%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               483      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      34111599                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   18295414402                       # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    218599021                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      20167865                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   24544733928                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    212322671                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  10163463729                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   9035902540                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   9200637125                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8451585698                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    233049222                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    205222100                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    729789968                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    663162345                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              123149965                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         82495484                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5956200                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            86779618                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               56690061                       # Number of BTB hits
+system.cpu1.branchPred.lookups              136771271                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         91615454                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6699408                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            96252672                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               62838118                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            65.326470                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16440472                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            156518                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            65.284544                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               18248077                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            178326                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1724,87 +1731,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   527411                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               527411                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10595                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        86487                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       240409                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       287002                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2359.187392                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 14719.861354                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       284807     99.24%     99.24% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1123      0.39%     99.63% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          785      0.27%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          158      0.06%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679           41      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   587464                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               587464                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        12287                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        93954                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       273243                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       314221                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2460.273184                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 14941.067276                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       311748     99.21%     99.21% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1254      0.40%     99.61% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          917      0.29%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          161      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679           52      0.02%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::327680-393215           63      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           20      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           18      0.01%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       287002                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       269681                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19234.134032                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 15959.440473                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 20416.372217                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       266977     99.00%     99.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          731      0.27%     99.27% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1349      0.50%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          143      0.05%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          295      0.11%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           58      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           94      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           19      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::786432-851967            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::851968-917503            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       269681                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 429707115240                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.574612                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.551988                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 428613446240     99.75%     99.75% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    584261000      0.14%     99.88% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    233148000      0.05%     99.94% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    115723000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9     78401000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     45162000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     15712000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     20912500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       347500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19         2000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 429707115240                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        86487     89.09%     89.09% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10595     10.91%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        97082                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       527411                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       314221                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       302969                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 20764.791117                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17394.458301                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 22544.227052                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       299168     98.75%     98.75% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          939      0.31%     99.06% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1914      0.63%     99.69% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          156      0.05%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          510      0.17%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215          121      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751          110      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           28      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            7      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       302969                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 477883045620                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.598615                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.553378                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 476579478620     99.73%     99.73% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    689019500      0.14%     99.87% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    279828500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    139297000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9     94668000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     55014500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     17997000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     27375000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       352000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19        15500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 477883045620                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        93955     88.43%     88.43% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        12287     11.57%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       106242                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       587464                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       527411                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        97082                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       587464                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       106242                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        97082                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       624493                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       106242                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       693706                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    91393564                       # DTB read hits
-system.cpu1.dtb.read_misses                    362569                       # DTB read misses
-system.cpu1.dtb.write_hits                   75279430                       # DTB write hits
-system.cpu1.dtb.write_misses                   164842                       # DTB write misses
+system.cpu1.dtb.read_hits                   101377575                       # DTB read hits
+system.cpu1.dtb.read_misses                    401827                       # DTB read misses
+system.cpu1.dtb.write_hits                   83690670                       # DTB write hits
+system.cpu1.dtb.write_misses                   185637                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              44894                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   36642                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      200                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  5827                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              44695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   39959                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      225                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  6406                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    40054                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                91756133                       # DTB read accesses
-system.cpu1.dtb.write_accesses               75444272                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    43965                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               101779402                       # DTB read accesses
+system.cpu1.dtb.write_accesses               83876307                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        166672994                       # DTB hits
-system.cpu1.dtb.misses                         527411                       # DTB misses
-system.cpu1.dtb.accesses                    167200405                       # DTB accesses
+system.cpu1.dtb.hits                        185068245                       # DTB hits
+system.cpu1.dtb.misses                         587464                       # DTB misses
+system.cpu1.dtb.accesses                    185655709                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1834,1160 +1841,1166 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    82282                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                82282                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          773                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        59282                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore         9946                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        72336                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1446.824541                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 11538.500060                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-65535        71995     99.53%     99.53% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-131071           83      0.11%     99.64% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-196607          237      0.33%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-262143           12      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        72336                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        70001                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 24228.861016                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 20738.037138                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 24674.307569                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        68717     98.17%     98.17% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071           87      0.12%     98.29% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          984      1.41%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           73      0.10%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           83      0.12%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           23      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           22      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::917504-983039            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        70001                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 391052327076                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.846616                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.360520                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    60001678208     15.34%     15.34% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   331032470368     84.65%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       15971500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        2073000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         134000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 391052327076                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        59282     98.71%     98.71% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          773      1.29%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        60055                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                    92227                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                92227                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          973                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        66704                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        11080                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        81147                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1613.670253                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 12323.334174                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        80305     98.96%     98.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          403      0.50%     99.46% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303           31      0.04%     99.50% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071           81      0.10%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839          234      0.29%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           59      0.07%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        81147                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        78757                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26873.185876                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 22946.544582                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 27397.779974                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        76775     97.48%     97.48% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          153      0.19%     97.68% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1519      1.93%     99.61% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143          117      0.15%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679          110      0.14%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           35      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           36      0.05%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        78757                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 434901307160                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.857521                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.349757                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    61992873300     14.25%     14.25% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   372883353360     85.74%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       22166000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        2474500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         253500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5         186500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 434901307160                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        66704     98.56%     98.56% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          973      1.44%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        67677                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        82282                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        82282                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        92227                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        92227                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        60055                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        60055                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       142337                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   193960223                       # ITB inst hits
-system.cpu1.itb.inst_misses                     82282                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        67677                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        67677                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       159904                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   215454990                       # ITB inst hits
+system.cpu1.itb.inst_misses                     92227                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              44894                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1069                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   26113                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              44695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   28858                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   206259                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   231246                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               194042505                       # ITB inst accesses
-system.cpu1.itb.hits                        193960223                       # DTB hits
-system.cpu1.itb.misses                          82282                       # DTB misses
-system.cpu1.itb.accesses                    194042505                       # DTB accesses
-system.cpu1.numCycles                       680051209                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               215547217                       # ITB inst accesses
+system.cpu1.itb.hits                        215454990                       # DTB hits
+system.cpu1.itb.misses                          92227                       # DTB misses
+system.cpu1.itb.accesses                    215547217                       # DTB accesses
+system.cpu1.numCycles                       759155378                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          76309039                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     545586843                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  123149965                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          73130533                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    567094976                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               12846360                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   1862646                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              285569                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      6032568                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       729307                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       772817                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                193732934                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1488213                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  27982                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         659510102                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.972600                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.218843                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          87128814                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     606063748                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  136771271                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          81086195                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    630037393                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               14425462                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2172177                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              325931                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      6736887                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       827556                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       851702                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                215200214                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1679756                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  31517                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         735293191                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.969104                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.218230                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               352323655     53.42%     53.42% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               119769188     18.16%     71.58% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                40581175      6.15%     77.74% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               146836084     22.26%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               394185812     53.61%     53.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               132782093     18.06%     71.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                45182528      6.14%     77.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               163142758     22.19%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           659510102                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.181089                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.802273                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                93216709                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            325116567                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                201438015                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             35171632                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               4567179                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            17405067                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1892222                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             567399835                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             20537774                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               4567179                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               125466899                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               47033211                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     215743407                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                203915656                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             62783750                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             552356795                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5241539                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents              9909237                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                240791                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                292344                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              29944703                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           11393                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          524936389                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            854810992                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       653637843                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           615050                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            473696954                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                51239429                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15119385                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13351935                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 70628253                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            91219643                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           78311402                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          8799360                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         7480777                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 531265202                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15384643                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                536975559                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2409415                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       48765571                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     31310459                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        261406                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    659510102                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.814204                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.064087                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           735293191                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.180162                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.798340                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               105275670                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            361149345                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                225652352                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             38094367                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5121457                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19322389                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              2132865                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             630175710                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             23074598                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5121457                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               140790232                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               54705867                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     237824642                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                227778492                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             69072501                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             613335461                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              5878562                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents             11068691                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                265258                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                344448                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              33464644                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           12708                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          582683755                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            946463821                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       725287459                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           802163                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            525337621                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                57346134                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          16349116                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      14383675                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 76724538                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           101292205                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           87094038                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          9603338                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         8276902                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 590341476                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           16600780                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                596033149                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2703684                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       54441407                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     34942140                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        296921                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    735293191                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.810606                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.063717                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          364889522     55.33%     55.33% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          126119203     19.12%     74.45% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          101926801     15.45%     89.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           59299384      8.99%     98.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7271358      1.10%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               3834      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          408888874     55.61%     55.61% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          138685440     18.86%     74.47% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          113812160     15.48%     89.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           65908523      8.96%     98.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7993150      1.09%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               5044      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      659510102                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      735293191                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               53688772     43.65%     43.65% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 42849      0.03%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   9758      0.01%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              12      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              33350405     27.12%     70.81% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             35903096     29.19%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               59894815     43.89%     43.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 54223      0.04%     43.93% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                  19415      0.01%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              13      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              36698954     26.89%     70.83% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             39811710     29.17%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               84      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            365127801     68.00%     68.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1207443      0.22%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                64356      0.01%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  5      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.23% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         40592      0.01%     68.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            94109837     17.53%     85.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           76425394     14.23%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass               40      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            405160238     67.98%     67.98% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1323587      0.22%     68.20% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                73165      0.01%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  6      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         83635      0.01%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           104404803     17.52%     85.74% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           84987627     14.26%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             536975559                       # Type of FU issued
-system.cpu1.iq.rate                          0.789610                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  122994892                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.229051                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1857852304                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        595160433                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    521544916                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1013221                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            400944                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       372548                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             659338375                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 631992                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2462766                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             596033149                       # Type of FU issued
+system.cpu1.iq.rate                          0.785127                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  136479130                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.228979                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        2065187396                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        660997777                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    578833453                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1354907                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            550149                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       503649                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             731674033                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 838206                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2717332                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     11273364                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        14330                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       146929                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5363484                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     12501770                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        16793                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       165759                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5982611                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2532880                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      4046276                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2801463                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      4362378                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               4567179                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                5912411                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              2185508                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          546765447                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               5121457                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                6701200                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              2456436                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          607072203                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             91219643                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            78311402                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          13149679                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 62909                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              2062449                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        146929                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       1850208                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2506307                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4356515                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            530131647                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             91388835                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6328626                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts            101292205                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            87094038                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          14166456                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 66987                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              2327340                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        165759                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2053658                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2840126                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4893784                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            588333719                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            101371104                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          7124424                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       115602                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   166669354                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                99325061                       # Number of branches executed
-system.cpu1.iew.exec_stores                  75280519                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.779547                       # Inst execution rate
-system.cpu1.iew.wb_sent                     522591798                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    521917464                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                252132377                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                413034686                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       129947                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   185062017                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               110209905                       # Number of branches executed
+system.cpu1.iew.exec_stores                  83690913                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.774985                       # Inst execution rate
+system.cpu1.iew.wb_sent                     580075402                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    579337102                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                280158358                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                458852190                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.767468                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.610439                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.763134                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.610563                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       42738935                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       15123237                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4100199                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    651431241                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.764293                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.565341                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       47675638                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       16303859                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4608134                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    726275789                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.760731                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.562013                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    432003686     66.32%     66.32% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    115523895     17.73%     84.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     47761812      7.33%     91.38% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15857432      2.43%     93.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     11422302      1.75%     95.57% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      7738049      1.19%     96.76% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5451213      0.84%     97.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3205095      0.49%     98.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     12467757      1.91%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    483439526     66.56%     66.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    126884990     17.47%     84.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     53284484      7.34%     91.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     17968651      2.47%     93.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     12727519      1.75%     95.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      8624800      1.19%     96.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      6048440      0.83%     97.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3562811      0.49%     98.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     13734568      1.89%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    651431241                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           422487941                       # Number of instructions committed
-system.cpu1.commit.committedOps             497884267                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    726275789                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           468737677                       # Number of instructions committed
+system.cpu1.commit.committedOps             552500848                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     152894196                       # Number of memory references committed
-system.cpu1.commit.loads                     79946278                       # Number of loads committed
-system.cpu1.commit.membars                    3616952                       # Number of memory barriers committed
-system.cpu1.commit.branches                  94285217                       # Number of branches committed
-system.cpu1.commit.fp_insts                    364520                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                457066504                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12254498                       # Number of function calls committed.
+system.cpu1.commit.refs                     169901862                       # Number of memory references committed
+system.cpu1.commit.loads                     88790435                       # Number of loads committed
+system.cpu1.commit.membars                    3923548                       # Number of memory barriers committed
+system.cpu1.commit.branches                 104577420                       # Number of branches committed
+system.cpu1.commit.fp_insts                    490317                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                507351840                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13608772                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       343931170     69.08%     69.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult         972359      0.20%     69.27% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           50623      0.01%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        35877      0.01%     69.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.29% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       79946278     16.06%     85.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      72947918     14.65%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       381394130     69.03%     69.03% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1072293      0.19%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           58068      0.01%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.24% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        74453      0.01%     69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       88790435     16.07%     85.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      81111427     14.68%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        497884267                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             12467757                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1176002301                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1089287670                       # The number of ROB writes
-system.cpu1.timesIdled                         891748                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       20541107                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 94110305176                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  422487941                       # Number of Instructions Simulated
-system.cpu1.committedOps                    497884267                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.609635                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.609635                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.621259                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.621259                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               627139214                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              370414988                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   604419                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  299356                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                113711382                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               114470989                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1170516156                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15242864                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5157965                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          429.133488                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          142089244                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5158477                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            27.544805                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8487531137500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   429.133488                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.838151                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.838151                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          378                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        317144363                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       317144363                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     74103111                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       74103111                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     63551574                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      63551574                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       164336                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       164336                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        50299                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        50299                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1740316                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1740316                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1762571                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1762571                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    137654685                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       137654685                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    137819021                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      137819021                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      6065944                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      6065944                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      6987777                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      6987777                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       664365                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       664365                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       405961                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       405961                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       258244                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       258244                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193910                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       193910                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     13053721                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      13053721                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     13718086                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     13718086                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  97739183000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  97739183000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 145756860728                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 145756860728                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  16103531712                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  16103531712                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4003848500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   4003848500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4624613000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4624613000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5341000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5341000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 243496043728                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 243496043728                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 243496043728                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 243496043728                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     80169055                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     80169055                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     70539351                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     70539351                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       828701                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       828701                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       456260                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       456260                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1998560                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1998560                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1956481                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1956481                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    150708406                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    150708406                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    151537107                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    151537107                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.075664                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.075664                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.099062                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.099062                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.801694                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.801694                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.889758                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.889758                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.129215                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.129215                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.099112                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.099112                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.086616                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.086616                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.090526                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.090526                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16112.773708                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16112.773708                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.831174                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.831174                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 39667.681654                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 39667.681654                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15504.129815                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15504.129815                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23849.275437                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23849.275437                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total        552500848                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             13734568                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1308834452                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1209328543                       # The number of ROB writes
+system.cpu1.timesIdled                         978867                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       23862187                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 93869849108                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  468737677                       # Number of Instructions Simulated
+system.cpu1.committedOps                    552500848                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.619574                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.619574                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.617446                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.617446                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               695521161                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              411377637                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   787723                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  479172                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                125942514                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               126793051                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1299771916                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              16418490                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          5616176                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          458.902978                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          158371031                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5616685                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            28.196531                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8486277940000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   458.902978                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.896295                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.896295                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          363                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        352316395                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       352316395                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     82533449                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       82533449                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     71018677                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      71018677                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       182219                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       182219                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        55748                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        55748                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1865594                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1865594                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1903770                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1903770                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    153552126                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       153552126                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    153734345                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      153734345                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      6611698                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      6611698                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      7495595                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      7495595                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       706613                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       706613                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       438931                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       438931                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       288457                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       288457                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       203515                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       203515                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     14107293                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      14107293                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     14813906                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     14813906                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 112950117500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 112950117500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 162063724604                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 162063724604                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  18729695563                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  18729695563                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4597585500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   4597585500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5657651000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5657651000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      7414500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      7414500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 275013842104                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 275013842104                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 275013842104                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 275013842104                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     89145147                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     89145147                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     78514272                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     78514272                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       888832                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       888832                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       494679                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       494679                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2154051                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2154051                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2107285                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2107285                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    167659419                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    167659419                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    168548251                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    168548251                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.074168                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.074168                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.095468                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.095468                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.794991                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.794991                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.887305                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.887305                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.133914                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.133914                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.096577                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.096577                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.084143                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.084143                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087891                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.087891                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17083.375178                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 17083.375178                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21621.195463                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21621.195463                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42671.161442                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42671.161442                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15938.547166                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15938.547166                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27799.675700                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27799.675700                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18653.381954                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18653.381954                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17750.001256                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17750.001256                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      4190229                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     23645788                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           332306                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         708476                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    12.609550                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    33.375567                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19494.444618                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19494.444618                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18564.573186                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18564.573186                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      4974164                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     25867147                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           359446                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         756404                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    13.838418                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    34.197528                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3362559                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3362559                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3121386                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3121386                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5664444                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      5664444                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3068                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total         3068                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       133009                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       133009                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      8785830                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      8785830                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      8785830                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      8785830                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2944558                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2944558                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1323333                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1323333                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       664291                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       664291                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       402893                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       402893                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       125235                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       125235                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193904                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       193904                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4267891                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4267891                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4932182                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4932182                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5159                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5159                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         4882                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         4882                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10041                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10041                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  44629208000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  44629208000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  29351732295                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  29351732295                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15227596000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15227596000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  15536076712                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  15536076712                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1817525500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1817525500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4430771000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4430771000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5279000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5279000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  73980940295                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  73980940295                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  89208536295                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  89208536295                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    520581000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    520581000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    549653500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    549653500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1070234500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1070234500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036729                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036729                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018760                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018760                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.801605                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.801605                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.883034                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.883034                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062663                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.062663                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.099109                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.099109                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028319                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.028319                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032548                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.032548                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15156.504983                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15156.504983                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22180.155936                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22180.155936                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22923.080397                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22923.080397                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 38561.297198                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 38561.297198                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14512.919711                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14512.919711                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22850.333155                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22850.333155                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      5616192                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5616192                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3382349                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3382349                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6057293                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      6057293                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3337                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         3337                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       147189                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       147189                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      9439642                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      9439642                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      9439642                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      9439642                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3229349                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3229349                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1438302                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1438302                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       706535                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       706535                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       435594                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       435594                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       141268                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       141268                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       203504                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       203504                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4667651                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4667651                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5374186                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5374186                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5460                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5460                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         5292                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         5292                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10752                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10752                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  50929568500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  50929568500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  34490212579                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  34490212579                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16980659000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16980659000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  18123603563                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  18123603563                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   2072685000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   2072685000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5454243000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5454243000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      7318500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      7318500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  85419781079                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  85419781079                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102400440079                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 102400440079                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    594704500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    594704500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    661334500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    661334500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1256039000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1256039000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036226                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036226                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018319                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018319                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.794903                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.794903                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.880559                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.880559                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.065582                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065582                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.096572                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.096572                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027840                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027840                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031885                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031885                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15770.846849                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15770.846849                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23979.812709                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23979.812709                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24033.712413                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24033.712413                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41606.641880                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41606.641880                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14672.006399                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14672.006399                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26801.650090                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26801.650090                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17334.308748                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17334.308748                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18087.032533                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18087.032533                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100907.346385                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 100907.346385                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112587.771405                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 112587.771405                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106586.445573                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 106586.445573                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18300.378730                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18300.378730                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19054.130259                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19054.130259                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108920.238095                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 108920.238095                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124968.726379                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124968.726379                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116819.103423                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116819.103423                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5202817                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.771617                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          188211208                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5203329                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            36.171306                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8527218243000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.771617                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980023                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.980023                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          5955939                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.596349                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          208888584                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5956451                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            35.069303                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8525956583000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.596349                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979680                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.979680                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           97                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        392655056                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       392655056                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    188211208                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      188211208                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    188211208                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       188211208                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    188211208                       # number of overall hits
-system.cpu1.icache.overall_hits::total      188211208                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      5514651                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      5514651                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      5514651                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       5514651                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      5514651                       # number of overall misses
-system.cpu1.icache.overall_misses::total      5514651                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  61642094935                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  61642094935                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  61642094935                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  61642094935                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  61642094935                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  61642094935                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    193725859                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    193725859                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    193725859                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    193725859                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    193725859                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    193725859                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.028466                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.028466                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.028466                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.028466                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.028466                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.028466                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11177.877790                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 11177.877790                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11177.877790                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 11177.877790                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11177.877790                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 11177.877790                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      9398442                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          360                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           665033                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              6                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.132294                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets           60                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses        436342012                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       436342012                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    208888584                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      208888584                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    208888584                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       208888584                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    208888584                       # number of overall hits
+system.cpu1.icache.overall_hits::total      208888584                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      6304191                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      6304191                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      6304191                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       6304191                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      6304191                       # number of overall misses
+system.cpu1.icache.overall_misses::total      6304191                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  70452471315                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  70452471315                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  70452471315                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  70452471315                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  70452471315                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  70452471315                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    215192775                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    215192775                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    215192775                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    215192775                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    215192775                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    215192775                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029296                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.029296                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029296                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.029296                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029296                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.029296                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11175.497588                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 11175.497588                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11175.497588                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 11175.497588                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11175.497588                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 11175.497588                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs     10802796                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          573                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           747541                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              5                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.451108                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets   114.600000                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       311313                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       311313                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       311313                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       311313                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       311313                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       311313                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5203338                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5203338                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5203338                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5203338                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5203338                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5203338                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      5955939                       # number of writebacks
+system.cpu1.icache.writebacks::total          5955939                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       347729                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       347729                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       347729                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       347729                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       347729                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       347729                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5956462                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5956462                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5956462                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5956462                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5956462                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5956462                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  55550609345                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  55550609345                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  55550609345                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  55550609345                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  55550609345                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  55550609345                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8907998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8907998                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8907998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      8907998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.026859                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.026859                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.026859                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.026859                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.026859                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.026859                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10675.956347                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10675.956347                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10675.956347                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10675.956347                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10675.956347                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10675.956347                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  63484136905                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  63484136905                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  63484136905                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  63484136905                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  63484136905                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  63484136905                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8835998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8835998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8835998                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      8835998                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027680                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027680                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027680                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.027680                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027680                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.027680                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10658.027686                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10658.027686                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10658.027686                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10658.027686                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10658.027686                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10658.027686                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 131880.567164                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 131880.567164                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7284852                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7288644                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         3499                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7807580                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7812689                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         4721                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       858524                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2147738                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13168.263726                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          17929780                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2163721                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            8.286549                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10234175062500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5935.884902                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    83.839548                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    89.493119                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2981.742674                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3164.985598                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   912.317885                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.362298                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.005117                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005462                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.181991                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.193175                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.055683                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.803727                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1279                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           76                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14628                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          228                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          605                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          432                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           36                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           24                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1303                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5317                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4591                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3288                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078064                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004639                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.892822                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       355115319                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      355115319                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       503903                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       170407                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        674310                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3362546                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3362546                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        76168                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        76168                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        33807                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        33807                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       827137                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       827137                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4627973                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4627973                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2745456                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2745456                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       178495                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       178495                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       503903                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       170407                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4627973                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3572593                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8874876                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       503903                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       170407                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4627973                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3572593                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8874876                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11662                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8601                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        20263                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks           12                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total           12                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       140170                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       140170                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       160091                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       160091                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.prefetcher.pfSpanPage       919623                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2337918                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13374.571842                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          17269379                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2353639                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.337310                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    10121843878000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12566.070038                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    56.667232                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    65.366082                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data     0.000003                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   686.468486                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.766972                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003459                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003990                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.000000                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.041899                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.816319                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1203                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           84                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14434                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           80                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          187                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          549                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          387                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           65                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          840                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4705                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4934                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3842                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.073425                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005127                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.880981                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       397810098                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      397810098                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       597256                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       208532                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        805788                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3539726                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3539726                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      8031138                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      8031138                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          945                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total          945                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            4                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
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+system.cpu1.l2cache.ReadCleanReq_hits::total      5374664                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3032294                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      3032294                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       189660                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       189660                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       597256                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       208532                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      5374664                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3922237                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total       10102689                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       597256                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       208532                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      5374664                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3922237                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total      10102689                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12883                       # number of ReadReq misses
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+system.cpu1.l2cache.ReadReq_misses::total        23135                       # number of ReadReq misses
+system.cpu1.l2cache.WritebackDirty_misses::writebacks            5                       # number of WritebackDirty misses
+system.cpu1.l2cache.WritebackDirty_misses::total            5                       # number of WritebackDirty misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       246019                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       246019                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       203494                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       203494                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       288732                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       288732                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       575353                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       575353                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       984374                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       984374                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       223283                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       223283                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11662                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8601                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       575353                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1273106                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1868722                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11662                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8601                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       575353                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1273106                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1868722                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    594160000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    468390500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   1062550500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   4210266499                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   4210266499                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3771249000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3771249000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      5184498                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      5184498                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  15534540997                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  15534540997                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  20167259000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  20167259000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  37839552480                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  37839552480                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  13425130499                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  13425130499                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    594160000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    468390500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  20167259000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  53374093477                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  74603902977                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    594160000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    468390500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  20167259000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  53374093477                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  74603902977                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       515565                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       179008                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       694573                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3362558                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3362558                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       216338                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       216338                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       193898                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       193898                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadExReq_misses::total       311077                       # number of ReadExReq misses
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+system.cpu1.l2cache.ReadCleanReq_misses::total       581787                       # number of ReadCleanReq misses
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+system.cpu1.l2cache.ReadSharedReq_misses::total      1040673                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       244105                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       244105                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12883                       # number of demand (read+write) misses
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+system.cpu1.l2cache.demand_misses::total      1956672                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12883                       # number of overall misses
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+system.cpu1.l2cache.overall_misses::cpu1.inst       581787                       # number of overall misses
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+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    705237000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    609311000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total   1314548000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3694717000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   3694717000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1939092500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1939092500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      7171998                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      7171998                       # number of SCUpgradeFailReq miss cycles
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+system.cpu1.l2cache.ReadExReq_miss_latency::total  16701418499                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  22000590000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  22000590000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  43617133977                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  43617133977                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  15757180999                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  15757180999                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    705237000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    609311000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  22000590000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  60318552476                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    705237000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    609311000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  22000590000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  60318552476                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  83633690476                       # number of overall miss cycles
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+system.cpu1.l2cache.ReadReq_accesses::total       828923                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3539731                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3539731                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      8031138                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      8031138                       # number of WritebackClean accesses(hits+misses)
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+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       203498                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1115869                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1115869                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5203326                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      5203326                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3729830                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3729830                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       401778                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       401778                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       515565                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       179008                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      5203326                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4845699                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     10743598                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       515565                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       179008                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      5203326                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4845699                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     10743598                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.022620                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.048048                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.029173                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000004                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000004                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.647921                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.647921                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.825645                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.825645                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1201020                       # number of ReadExReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadCleanReq_accesses::total      5956451                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4072967                       # number of ReadSharedReq accesses(hits+misses)
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+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       433765                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       433765                       # number of InvalidateReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021115                       # miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::total     0.027910                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.996174                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.996174                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999980                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999980                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.258751                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.258751                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.110574                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.110574                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.263919                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.263919                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.555737                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.555737                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.022620                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.048048                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.110574                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.262729                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.173938                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.022620                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.048048                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.110574                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.262729                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.173938                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 50948.379352                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 54457.679340                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 52437.965750                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30036.858807                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30036.858807                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23556.908258                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23556.908258                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       864083                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       864083                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53802.630110                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53802.630110                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35051.975048                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35051.975048                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38440.219348                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38440.219348                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 60126.075424                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 60126.075424                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 50948.379352                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 54457.679340                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35051.975048                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 41924.312254                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 39922.419160                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 50948.379352                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 54457.679340                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35051.975048                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 41924.312254                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 39922.419160                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          689                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.259011                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.259011                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.097673                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.097673                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.255507                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.255507                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.562759                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.562759                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021115                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.046859                       # miss rate for demand accesses
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+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.256305                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.162253                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021115                       # miss rate for overall accesses
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+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15018.014869                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15018.014869                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9528.991027                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9528.991027                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1195333                       # average SCUpgradeFailReq miss latency
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+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53689.017507                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53689.017507                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37815.540739                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37815.540739                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 41912.429723                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 41912.429723                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 64550.832629                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 64550.832629                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54741.675076                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 59433.378853                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37815.540739                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44622.565176                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 42742.825816                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54741.675076                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 59433.378853                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37815.540739                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44622.565176                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 42742.825816                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs          758                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               5                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   137.800000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   126.333333                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1011189                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1011189                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            3                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          149                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          152                       # number of ReadReq MSHR hits
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-system.cpu1.l2cache.InvalidateReq_mshr_hits::total           12                       # number of InvalidateReq MSHR hits
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-system.cpu1.l2cache.Writeback_mshr_misses::total           12                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks       102199                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total       102199                       # number of CleanEvict MSHR misses
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-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       140170                       # number of UpgradeReq MSHR misses
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 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
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 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
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-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    479244000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    487648500                       # number of ReadReq MSHR uncacheable cycles
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-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1000634000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022614                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.047216                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.028954                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000004                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000004                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1180803500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021108                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.046087                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.027701                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.647921                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.647921                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.825645                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.825645                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996174                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996174                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999980                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999980                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.215298                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.215298                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.110574                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.110574                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.262911                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.262911                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.555707                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.555707                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.022614                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.047216                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.110574                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.251947                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.169061                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.022614                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.047216                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.110574                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.251947                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.222035                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.222035                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.097673                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.097673                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.254101                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.254101                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.562745                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.562745                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021108                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.046087                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.097673                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.246799                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.158082                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021108                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.046087                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.097673                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.246799                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.236233                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 46295.659092                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64713.594163                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32826.799579                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32826.799579                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18485.698746                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18485.698746                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       802083                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       802083                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48485.514714                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48485.514714                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29051.975048                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29051.975048                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32412.588508                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32412.588508                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 54126.588312                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 54126.588312                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29051.975048                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35575.463241                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33627.728921                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29051.975048                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35575.463241                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42466.849098                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 92894.747044                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93311.997704                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105076.915199                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 105076.915199                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 98817.797032                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 98994.261971                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.226128                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 50761.235955                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59823.938056                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31373.954837                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31373.954837                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19288.362296                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19288.362296                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1099333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1099333                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48243.449741                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48243.449741                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31815.540739                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31815.540739                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 35803.680263                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35803.680263                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 58550.043216                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 58550.043216                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31815.540739                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 38352.282068                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 36506.855443                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31815.540739                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 38352.282068                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43523.410547                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100898.168498                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101182.648815                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117454.081633                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117454.081633                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109046.781994                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 109141.648951                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     21572446                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11121796                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1158                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       524506                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       524489                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops           17                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        847854                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      9869269                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         4882                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         4882                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      4416651                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      8880510                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       907695                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp           13                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       421769                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       350236                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       471619                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           69                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1189775                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1122660                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5203338                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4763767                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       409409                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       401778                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15609171                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16649345                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       393406                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1143795                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         33795717                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    333013936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    531452177                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1432064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4124520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         870022697                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5627139                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     27397107                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.032027                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.176075                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests     24065952                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     12401926                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1256                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      2060689                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2060329                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          360                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq        934376                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     11053796                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         5292                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         5292                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4812576                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      8031153                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2767424                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq      1034593                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       454030                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       361772                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       513435                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq          121                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          211                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1276992                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1207288                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5956462                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5025648                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       440267                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       433765                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17868522                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18112795                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       459206                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1298566                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         37739089                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    762364336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    703129592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1750272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4881112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1472125312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    6734851                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     19529823                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.125012                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.330788                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          26519684     96.80%     96.80% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            877406      3.20%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2                17      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          17088727     87.50%     87.50% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2440736     12.50%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               360      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      27397107                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   14402314458                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    173479331                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      19529823                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   23888032965                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    176197847                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7809268085                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   8940771887                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7687735490                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8370756543                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    214700392                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    240887058                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    628828296                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    689185473                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40404                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40404                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136681                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136681                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47892                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136623                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136623                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47620                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -3002,13 +3015,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122826                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231264                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231264                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122554                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231208                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231208                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354170                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47912                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353842                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47640                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -3023,105 +3036,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155933                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339072                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7339072                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155661                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338848                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7338848                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7497091                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36369000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496595                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36904500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            24719501                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              169000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            36445000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              115000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           566086533                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           565389979                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               44500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92876000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92662000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147960000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147904000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115614                       # number of replacements
-system.iocache.tags.tagsinuse               11.301705                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115630                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9126915715000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.837722                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.463983                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239858                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.466499                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.706357                       # Average percentage of cache occupancy
+system.iocache.tags.replacements               115596                       # number of replacements
+system.iocache.tags.tagsinuse               11.294963                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      4                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs               115612                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000035                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         9125681000000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.424342                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.870620                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.464021                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.241914                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705935                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1041045                       # Number of tag accesses
-system.iocache.tags.data_accesses             1041045                       # Number of data accesses
+system.iocache.tags.tag_accesses              1040789                       # Number of tag accesses
+system.iocache.tags.data_accesses             1040789                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8904                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8941                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8876                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8913                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8904                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8944                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8876                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8916                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8904                       # number of overall misses
-system.iocache.overall_misses::total             8944                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5199000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1751682968                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1756881968                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8876                       # number of overall misses
+system.iocache.overall_misses::total             8916                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5200000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1711011512                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1716211512                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13928366565                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13928366565                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5568000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1751682968                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1757250968                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5568000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1751682968                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1757250968                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13978863467                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13978863467                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5569000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1711011512                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1716580512                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5569000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1711011512                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1716580512                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8904                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8941                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8876                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8913                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8904                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8944                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8876                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8916                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8904                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8944                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8876                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8916                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -3135,55 +3148,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140513.513514                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 196729.893082                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 196497.256235                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 192768.309148                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 192551.499159                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130503.397094                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130503.397094                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       139200                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 196729.893082                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 196472.603757                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       139200                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 196729.893082                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 196472.603757                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         36915                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130976.533496                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130976.533496                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 192768.309148                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 192528.096904                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 192768.309148                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 192528.096904                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         36708                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3596                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3726                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.265573                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.851852                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106695                       # number of writebacks
-system.iocache.writebacks::total               106695                       # number of writebacks
+system.iocache.writebacks::writebacks          106693                       # number of writebacks
+system.iocache.writebacks::total               106693                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8904                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8941                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8876                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8913                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8904                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8944                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8876                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8916                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8904                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8944                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3349000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1306482968                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1309831968                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8876                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8916                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3350000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1267211512                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1270561512                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8591966565                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8591966565                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3568000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1306482968                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1310050968                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3568000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1306482968                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1310050968                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8642463467                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8642463467                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3569000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1267211512                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1270780512                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3569000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1267211512                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1270780512                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -3197,621 +3210,626 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90513.513514                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 146729.893082                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 146497.256235                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142768.309148                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 142551.499159                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80503.397094                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80503.397094                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89200                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 146729.893082                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 146472.603757                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89200                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 146729.893082                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 146472.603757                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80976.533496                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80976.533496                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 142768.309148                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 142528.096904                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 142768.309148                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 142528.096904                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1633941                       # number of replacements
-system.l2c.tags.tagsinuse                63813.673701                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5902225                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1694519                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.483127                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1583129                       # number of replacements
+system.l2c.tags.tagsinuse                63158.639853                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6207421                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1642739                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.778702                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   18421.604397                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   145.885026                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   177.213344                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5018.050694                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    11022.844294                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  9747.408023                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   214.913940                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   271.296665                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2354.078258                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     5504.302098                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10936.076961                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.281091                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002226                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.002704                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.076569                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.168195                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.148734                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003279                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.004140                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.035920                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.083989                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.166871                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.973719                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        11165                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          256                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        49157                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2         1008                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          549                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         9608                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          249                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2663                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         4864                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        41332                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.170364                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003906                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.750076                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 73803894                       # Number of tag accesses
-system.l2c.tags.data_accesses                73803894                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2578909                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2578909                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           27661                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           31933                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               59594                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6629                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          5839                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             12468                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           166000                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           160567                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               326567                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         7163                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4665                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       621325                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       619304                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       290117                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6244                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4367                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       539807                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       573735                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       292658                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2959385                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          7163                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4665                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              621325                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              785304                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       290117                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6244                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4367                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              539807                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              734302                       # number of demand (read+write) hits
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-system.l2c.demand_hits::total                 3285952                       # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.data             785304                       # number of overall hits
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-system.l2c.overall_hits::cpu1.dtb.walker         6244                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4367                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             539807                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             734302                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       292658                       # number of overall hits
-system.l2c.overall_hits::total                3285952                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         47272                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         44187                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             91459                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        10524                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         8835                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           19359                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         557751                       # number of ReadExReq misses
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-system.l2c.ReadExReq_misses::total             667386                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2718                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2691                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        73804                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       176754                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       337074                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2418                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2009                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        35546                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       108545                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       227714                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         969273                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2718                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2691                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             73804                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            734505                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       337074                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2418                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2009                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             35546                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            218180                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       227714                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1636659                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2718                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2691                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            73804                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           734505                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       337074                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2418                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2009                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            35546                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           218180                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       227714                       # number of overall misses
-system.l2c.overall_misses::total              1636659                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    726731000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    727663000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   1454394000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    175002000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    129347000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    304349000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  99619806501                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  16419004998                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 116038811499                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    387278500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    381455000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst  10138420502                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  26142956500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  61823794743                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    346383500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    287503000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   4887103000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  15686030000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  41333236319                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 161414161064                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    387278500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    381455000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst  10138420502                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 125762763001                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  61823794743                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    346383500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    287503000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4887103000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  32105034998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  41333236319                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    277452972563                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    387278500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    381455000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst  10138420502                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 125762763001                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  61823794743                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    346383500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    287503000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4887103000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  32105034998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  41333236319                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   277452972563                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks      2578909                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2578909                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        74933                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        76120                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          151053                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        17153                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        14674                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         31827                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       723751                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       270202                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           993953                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         9881                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7356                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       695129                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       796058                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       627191                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8662                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6376                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       575353                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       682280                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       520372                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3928658                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         9881                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         7356                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          695129                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1519809                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       627191                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         8662                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6376                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          575353                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          952482                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       520372                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4922611                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         9881                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         7356                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         695129                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1519809                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       627191                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         8662                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6376                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         575353                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         952482                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       520372                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4922611                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.630857                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.580491                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.605476                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.613537                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.602085                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.608257                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.770639                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.405752                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.671446                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.275073                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.365824                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.106173                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.222037                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.537434                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.279150                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.315088                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.061781                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.159092                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.437598                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.246719                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.275073                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.365824                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.106173                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.483288                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.537434                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.279150                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.315088                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.061781                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.229065                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.437598                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.332478                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.275073                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.365824                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.106173                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.483288                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.537434                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.279150                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.315088                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.061781                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.229065                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.437598                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.332478                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15373.392283                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16467.807274                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 15902.141943                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16628.848347                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14640.294284                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 15721.318250                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 178609.821410                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149760.614749                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 173870.610859                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142486.571008                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141752.136752                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137369.526069                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 147905.883318                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 183413.122172                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143252.067825                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 143107.516177                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137486.721431                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144511.769312                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181513.812585                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 166531.164145                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142486.571008                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141752.136752                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 137369.526069                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 171221.112179                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 183413.122172                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 143252.067825                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 143107.516177                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 137486.721431                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 147149.303318                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181513.812585                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 169523.995263                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142486.571008                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141752.136752                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 137369.526069                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 171221.112179                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 183413.122172                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143252.067825                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 143107.516177                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 137486.721431                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 147149.303318                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181513.812585                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 169523.995263                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              5328                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   20395.624897                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    35.797068                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    37.096794                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3244.022805                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4223.269206                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  3404.413573                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   297.158145                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   465.494648                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3968.740099                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     9359.576527                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17727.446091                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.311213                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000546                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000566                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.049500                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.064442                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.051947                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004534                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.007103                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.060558                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.142816                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.270499                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.963724                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10142                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          206                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        49262                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2         1206                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          394                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         8542                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          205                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          375                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3055                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5795                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        39993                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.154755                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003143                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.751678                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 79196544                       # Number of tag accesses
+system.l2c.tags.data_accesses                79196544                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      2898173                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2898173                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total               1                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data          160488                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          150342                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              310830                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         37186                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         44723                       # number of SCUpgradeReq hits
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+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.272134                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.299193                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.285478                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.264372                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.208344                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.234803                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.778032                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.415275                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.666876                       # miss rate for ReadExReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.203222                       # miss rate for ReadSharedReq accesses
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+system.l2c.ReadSharedReq_miss_rate::total     0.250556                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.278847                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.278847                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.337315                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16242.562872                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17969.377580                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 17135.045254                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15593.572284                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18181.393373                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 16805.422933                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165524.321757                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147395.289544                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 162065.059331                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142684.115523                       # average ReadSharedReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137162.872932                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 145069.328964                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143261.637504                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142089.803220                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137117.547208                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143975.728771                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 163688.380804                       # average ReadSharedReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.inst 137162.872932                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 161160.729237                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.inst 137117.547208                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 145613.451613                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::total 163019.571857                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.inst 137162.872932                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 161160.729237                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 163019.571857                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             10461                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       43                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      107                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs    123.906977                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     97.766355                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1264610                       # number of writebacks
-system.l2c.writebacks::total                  1264610                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          171                       # number of ReadSharedReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                364                       # number of demand (read+write) MSHR hits
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-system.l2c.overall_mshr_hits::total               364                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        56079                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        56079                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        47272                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        44187                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        91459                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10524                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         8835                       # number of SCUpgradeReq MSHR misses
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-system.l2c.overall_mshr_miss_latency::total 261046166563                       # number of overall MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7197500                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency::total   7923621000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   5120804533                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    429980000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5550784533                       # number of WriteReq MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::total  13474405533                       # number of overall MSHR uncacheable cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4718897004                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   9129956008                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::total   8304410500                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::total  14260264533                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.630857                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.580491                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.605476                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.613537                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.602085                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.608257                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.770639                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.405752                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.671446                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.275073                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.365824                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.105927                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.222008                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.537434                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.279035                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.315088                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.061517                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.159068                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.437597                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.246626                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.275073                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.365824                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.105927                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.483273                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.537434                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.279035                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.315088                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.061517                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.229048                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.437597                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.332404                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.275073                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.365824                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.105927                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.483273                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.537434                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.279035                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.315088                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.061517                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.229048                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.437597                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.332404                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73616.390294                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73553.635707                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73586.071387                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76461.516819                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.098585                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.084354                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168609.821410                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139760.614749                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 163870.610859                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127419.322885                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137909.099139                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127550.149743                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134512.466714                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 156548.463338                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127419.322885                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161222.616076                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127550.149743                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137149.843686                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 159534.904503                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127419.322885                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161222.616076                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127550.149743                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137149.843686                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 159534.904503                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154441.302124                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74922.726391                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132599.588326                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153294.552702                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88074.559607                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 144978.309426                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153866.490599                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81318.507820                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 137433.631498                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.272134                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.299193                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.285478                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.264372                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.208344                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.234803                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.778031                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.415275                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.666875                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.278847                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.357118                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.109544                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.202317                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.523301                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.302054                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.345830                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.085145                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.180852                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.428190                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.250193                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.278847                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.357118                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.109544                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.484780                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.523301                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.302054                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.345830                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.085145                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.247954                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.428190                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.337027                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.278847                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.357118                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.109544                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.484780                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.523301                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.302054                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.345830                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.085145                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.247954                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.428190                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.337027                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73513.974368                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73520.246226                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73517.215898                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76539.471865                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76458.666015                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76501.631296                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155524.478079                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137395.289544                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 152065.180648                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127229.273092                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 135142.172565                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127189.983043                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133999.223594                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153742.669820                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127229.273092                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 151191.633086                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127189.983043                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135627.302450                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 153050.954108                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127229.273092                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 151191.633086                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127189.983043                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135627.302450                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 153050.954108                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165697.299188                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 82908.849395                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139109.343853                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164474.122464                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100403.061224                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155615.029734                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165084.763635                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91520.883721                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 145557.461805                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               59756                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1037606                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38287                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38287                       # Transaction distribution
-system.membus.trans_dist::Writeback           1371305                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           262648                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           440849                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         306045                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          117782                       # Transaction distribution
+system.membus.trans_dist::ReadReq               59697                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1020888                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38273                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38273                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1348844                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           267564                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           448101                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         314840                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          158230                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            681386                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           660425                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        977850                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122826                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25318                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5711814                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5860036                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       343033                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       343033                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6203069                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155933                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50636                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    185527680                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    185734821                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7281536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7281536                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               193016357                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           652692                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4246933                       # Request fanout histogram
+system.membus.trans_dist::ReadExReq            678893                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           659308                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        961191                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106727                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106727                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122554                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25446                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5713992                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5862068                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342759                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342759                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6204827                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155661                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50892                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    182954368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    183161477                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7272320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7272320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190433797                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           627031                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4226315                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4246933    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4226315    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4246933                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98658999                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4226315                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            98488499                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               53000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21380469                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21525971                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9518454911                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9456985184                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         8904498116                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8888143010                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          230513312                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228798971                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3865,56 +3883,57 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     11772030                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      5986527                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      2060183                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         193514                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       180675                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        12839                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              59758                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4863251                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38287                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38287                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          3950228                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1568757                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          493482                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        318513                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         811995                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          125                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          125                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1145198                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1145198                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4810734                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9122705                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6709100                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              15831805                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    283955252                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    196820081                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              480775333                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3520564                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         13735314                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.326662                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.470981                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests     12205155                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6621083                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1960564                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         171525                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       155955                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        15570                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              59699                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4664873                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38273                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38273                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      4247047                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1614803                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          750027                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        396749                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1146775                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          211                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          211                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1140836                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1140836                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4612412                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106727                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8853195                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7749082                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              16602277                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    269317869                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    224565592                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              493883461                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3357154                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          8803755                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.347401                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.479844                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                9261350     67.43%     67.43% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                4461125     32.48%     99.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  12839      0.09%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5760896     65.44%     65.44% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3027289     34.39%     99.82% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  15570      0.18%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           13735314                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9000721880                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8803755                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9517655622                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2650288                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2614297                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        5320683808                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4898920623                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4098533956                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4389147401                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   13032                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   12586                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5368                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    5763                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index 9406da48a..73bffeadf 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,141 +1,141 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.331518                       # Number of seconds simulated
-sim_ticks                                51331518104000                       # Number of ticks simulated
-final_tick                               51331518104000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.331535                       # Number of seconds simulated
+sim_ticks                                51331535316000                       # Number of ticks simulated
+final_tick                               51331535316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  87398                       # Simulator instruction rate (inst/s)
-host_op_rate                                   102692                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5304439586                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 679424                       # Number of bytes of host memory used
-host_seconds                                  9677.09                       # Real time elapsed on the host
-sim_insts                                   845761974                       # Number of instructions simulated
-sim_ops                                     993759083                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 107339                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126124                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6518614527                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 729844                       # Number of bytes of host memory used
+host_seconds                                  7874.61                       # Real time elapsed on the host
+sim_insts                                   845255961                       # Number of instructions simulated
+sim_ops                                     993175006                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       205120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       196736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5673888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          72271240                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        441728                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             78788712                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5673888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5673888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67330112                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       205184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       203136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5579360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          71974536                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        439872                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             78402088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5579360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5579360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     67218688                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67350692                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3205                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3074                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             104607                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1129251                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6902                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1247039                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1052033                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          67239268                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3206                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3174                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             103130                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1124615                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6873                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1240998                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1050292                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1054606                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           3996                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3833                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               110534                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1407931                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8605                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1534899                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          110534                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             110534                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1311672                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1052865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           3997                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           3957                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               108693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1402150                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8569                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1527367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          108693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             108693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1309501                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1312073                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1311672                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          3996                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3833                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              110534                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1408332                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8605                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2846972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1247039                       # Number of read requests accepted
-system.physmem.writeReqs                      1054606                       # Number of write requests accepted
-system.physmem.readBursts                     1247039                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1054606                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 79759552                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     50944                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  67349568                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  78788712                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               67350692                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      796                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1309902                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1309501                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          3997                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          3957                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              108693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1402551                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8569                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2837269                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1240998                       # Number of read requests accepted
+system.physmem.writeReqs                      1052865                       # Number of write requests accepted
+system.physmem.readBursts                     1240998                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1052865                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 79374080                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     49792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  67238272                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  78402088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               67239268                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      778                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         141264                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               74145                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               81438                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               79571                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               74681                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               75850                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               80076                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               74234                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               74770                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               71012                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              102127                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              78424                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              78933                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              75355                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              78384                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              73014                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              74229                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61794                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67391                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               68136                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               64875                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               65862                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               67755                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               63835                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65687                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               61691                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               69909                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65651                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67939                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              65356                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67578                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64108                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64770                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         323831                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               73630                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               80699                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               78276                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               74217                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               73666                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               79970                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               75195                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               74032                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               71713                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              100993                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              77049                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              78387                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              77207                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              77888                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              72930                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              74368                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61890                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               67926                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               67010                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               65080                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               64889                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               68021                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64968                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65143                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               62358                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               69100                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              64674                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              67475                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              66848                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              67005                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              63727                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64484                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51331516800500                       # Total gap between requests
+system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51331533904500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1225754                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1219713                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1052033                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    635607                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    328525                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    149631                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    126665                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       692                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       573                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       581                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1305                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       789                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       347                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      405                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      172                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      130                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      130                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       74                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1050292                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    631662                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    326376                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    149637                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    126770                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       678                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       576                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       562                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1325                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       777                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       342                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      166                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      165                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       76                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -159,120 +159,120 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    11652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    13577                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    31214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    44410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    55222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    63148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    64318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    64499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    66981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    65872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    66221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    71514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    66478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    79594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    84129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    64906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    68384                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      320                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       476504                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      308.725081                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     177.620621                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     336.470597                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         186131     39.06%     39.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       111955     23.50%     62.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        45179      9.48%     72.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23084      4.84%     76.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18337      3.85%     80.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11525      2.42%     83.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10900      2.29%     85.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8098      1.70%     87.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        61295     12.86%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         476504                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59915                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.799683                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      269.572248                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          59912     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    11849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    13848                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    31106                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    44112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    54434                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    62830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    64146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    65206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    66402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    65786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    66222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    71472                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    66143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    80247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    84167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    64432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    68381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    61265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      801                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      366                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      220                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       55                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       67                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       475699                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      308.203229                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.287854                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     336.241632                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         186276     39.16%     39.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       111535     23.45%     62.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        45072      9.47%     72.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        23389      4.92%     77.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18072      3.80%     80.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11535      2.42%     83.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10579      2.22%     85.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8108      1.70%     87.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        61133     12.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         475699                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59810                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.735663                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      269.812069                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          59807     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59915                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59915                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.563832                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.981523                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.290123                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           57069     95.25%     95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             858      1.43%     96.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              58      0.10%     96.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             312      0.52%     97.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              36      0.06%     97.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             354      0.59%     97.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             211      0.35%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              25      0.04%     98.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              62      0.10%     98.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             123      0.21%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              28      0.05%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              35      0.06%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             500      0.83%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              29      0.05%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              31      0.05%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             125      0.21%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               7      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           59810                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59810                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.565591                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.987331                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.225331                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           56970     95.25%     95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             839      1.40%     96.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              56      0.09%     96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             337      0.56%     97.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              42      0.07%     97.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             348      0.58%     97.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             200      0.33%     98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              22      0.04%     98.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              64      0.11%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             127      0.21%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              27      0.05%     98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              38      0.06%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             506      0.85%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              29      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              24      0.04%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             125      0.21%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::108-111             1      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            19      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             5      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59915                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    31917471814                       # Total ticks spent queuing
-system.physmem.totMemAccLat               55284528064                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6231215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25610.95                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            25      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59810                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    31819415784                       # Total ticks spent queuing
+system.physmem.totMemAccLat               55073540784                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6201100000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25656.27                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44360.95                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  44406.27                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.55                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.31                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.53                       # Average system read bandwidth in MiByte/s
@@ -281,56 +281,56 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.76                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1024444                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    797630                       # Number of row buffer hits during writes
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.21                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1019502                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    795615                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.20                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22302099.93                       # Average gap between requests
-system.physmem.pageHitRate                      79.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1809644760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  987405375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4795167000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3404170800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352725027600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1235982378375                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29714714061000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34314417854910                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.486362                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49432942986454                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1714072100000                       # Time in different power states
+system.physmem.writeRowHitRate                  75.73                       # Row buffer hit rate for writes
+system.physmem.avgGap                     22377767.94                       # Average gap between requests
+system.physmem.pageHitRate                      79.23                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1796611320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  980293875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4755496200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3401526960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1234173509595                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29716310123250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34314143605920                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.480817                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49435613390416                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1714072620000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    184500143546                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    181848672584                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1792725480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  978173625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4925481600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3414972960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352725027600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1238461921980                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29712539014500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34314837317745                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.494534                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49429295042072                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1714072100000                       # Time in different power states
+system.physmem_1.actEnergy                 1799673120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  981964500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4918173000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3406348080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1238619690855                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29712409964250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34314861858525                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.494809                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49429083175074                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1714072620000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    188150328928                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    188374993676                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst          400                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           436                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst          400                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          400                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst           25                       # Number of read requests responded to by this memory
+system.realview.nvmem.bytes_read::total           420                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst          384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
@@ -339,15 +339,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               223690256                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         149470273                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12181359                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157723580                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               103180902                       # Number of BTB hits
+system.cpu.branchPred.lookups               223536271                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         149385948                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12169974                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            157736918                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               103109650                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.418818                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30739943                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             342702                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.368115                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30707782                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             342742                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -378,87 +378,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    934978                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                934978                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15042                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       154863                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       425141                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       509837                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2238.847906                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14877.677912                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       506434     99.33%     99.33% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         1917      0.38%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607          986      0.19%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          211      0.04%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          153      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           25      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751           49      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287           51      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       509837                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       473320                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 22997.265064                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18038.108072                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20298.605153                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       462482     97.71%     97.71% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         7672      1.62%     99.33% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2249      0.48%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          179      0.04%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          532      0.11%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           62      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751          112      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           23      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       473320                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 784047304876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.724244                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.519446                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  781857637876     99.72%     99.72% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1171824000      0.15%     99.87% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     476098500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     199009000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     143211000      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    120940000      0.02%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     26747000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     49238000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2599500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 784047304876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        154864     91.15%     91.15% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15042      8.85%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       169906                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       934978                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks                    935593                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                935593                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15313                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       154778                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       425408                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       510185                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2222.203710                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14681.416911                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       506821     99.34%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         1912      0.37%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607          970      0.19%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          202      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          151      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           19      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751           50      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287           49      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       510185                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       473757                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23106.578900                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 18127.358359                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20599.365275                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       462892     97.71%     97.71% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         7688      1.62%     99.33% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         2250      0.47%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          174      0.04%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          494      0.10%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           87      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751          117      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           41      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       473757                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 784064516876                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.722483                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.520538                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  781865994376     99.72%     99.72% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    1176082000      0.15%     99.87% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     477234000      0.06%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     199500000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     146109500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    120981500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     26256500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     49725000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2626500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::18-19         7500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 784064516876                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        154779     91.00%     91.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         15313      9.00%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       170092                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       935593                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       934978                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       169906                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       935593                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       170092                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       169906                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1104884                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       170092                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1105685                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    168982671                       # DTB read hits
-system.cpu.dtb.read_misses                     669792                       # DTB read misses
-system.cpu.dtb.write_hits                   147065605                       # DTB write hits
-system.cpu.dtb.write_misses                    265186                       # DTB write misses
+system.cpu.dtb.read_hits                    168870430                       # DTB read hits
+system.cpu.dtb.read_misses                     669785                       # DTB read misses
+system.cpu.dtb.write_hits                   146966916                       # DTB write hits
+system.cpu.dtb.write_misses                    265808                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               39152                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid               39148                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1017                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    71824                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                    71844                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                        98                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   9312                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   9429                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69742                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                169652463                       # DTB read accesses
-system.cpu.dtb.write_accesses               147330791                       # DTB write accesses
+system.cpu.dtb.perms_faults                     69613                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                169540215                       # DTB read accesses
+system.cpu.dtb.write_accesses               147232724                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         316048276                       # DTB hits
-system.cpu.dtb.misses                          934978                       # DTB misses
-system.cpu.dtb.accesses                     316983254                       # DTB accesses
+system.cpu.dtb.hits                         315837346                       # DTB hits
+system.cpu.dtb.misses                          935593                       # DTB misses
+system.cpu.dtb.accesses                     316772939                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -488,180 +486,177 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    161206                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                161206                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1436                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       121549                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17620                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       143586                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1244.532893                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9274.227664                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       142628     99.33%     99.33% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          542      0.38%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303           55      0.04%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           79      0.06%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839          218      0.15%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           29      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            4      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                    161130                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                161130                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1443                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       121427                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17608                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       143522                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1275.602347                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  9467.048086                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       142512     99.30%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          586      0.41%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303           51      0.04%     99.74% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071           83      0.06%     99.80% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839          223      0.16%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           32      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911           14      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       143586                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       140605                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 28864.162014                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24089.686815                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 22873.385810                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       137806     98.01%     98.01% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071          710      0.50%     98.51% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1778      1.26%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143          108      0.08%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          117      0.08%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           38      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           35      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       140605                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 663785102088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.942542                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.233053                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     38191035356      5.75%      5.75% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    625543374232     94.24%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        49878500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          812000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            2000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 663785102088                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        121549     98.83%     98.83% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1436      1.17%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       122985                       # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       143522                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       140478                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 29089.590541                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24285.230021                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 22670.988579                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       137385     97.80%     97.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071          891      0.63%     98.43% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         1925      1.37%     99.80% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           93      0.07%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          119      0.08%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           27      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           23      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       140478                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 668097269884                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.944108                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.230056                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     37393446856      5.60%      5.60% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    630652469528     94.40%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        50695000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          657500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4            1000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 668097269884                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        121427     98.83%     98.83% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1443      1.17%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       122870                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161206                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       161206                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161130                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       161130                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122985                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       122985                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       284191                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    355626065                       # ITB inst hits
-system.cpu.itb.inst_misses                     161206                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122870                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       122870                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       284000                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    355391745                       # ITB inst hits
+system.cpu.itb.inst_misses                     161130                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               39152                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid               39148                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1017                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    52940                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    52871                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    369021                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    369048                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                355787271                       # ITB inst accesses
-system.cpu.itb.hits                         355626065                       # DTB hits
-system.cpu.itb.misses                          161206                       # DTB misses
-system.cpu.itb.accesses                     355787271                       # DTB accesses
-system.cpu.numCycles                       1638586091                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                355552875                       # ITB inst accesses
+system.cpu.itb.hits                         355391745                       # DTB hits
+system.cpu.itb.misses                          161130                       # DTB misses
+system.cpu.itb.accesses                     355552875                       # DTB accesses
+system.cpu.numCycles                       1639149006                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          642614268                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      998103903                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   223690256                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133920845                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     910005464                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                26014386                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3801464                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                28966                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9302327                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1031206                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          853                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 355240310                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6091194                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   48629                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1579791741                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.740255                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.146164                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          642133876                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      997446842                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   223536271                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          133817432                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     910640256                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                25987402                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3814067                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                27748                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9296817                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1023598                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          983                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 355005878                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6082209                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   48751                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1579931046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.739715                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.145918                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1024362050     64.84%     64.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                213190505     13.49%     78.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70458696      4.46%     82.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                271780490     17.20%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1024858413     64.87%     64.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                213048750     13.48%     78.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70422001      4.46%     82.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                271601882     17.19%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1579791741                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.136514                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.609125                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                522893988                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             566130284                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 431833495                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49726107                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9207867                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33553949                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3859168                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1081567524                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              28956293                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9207867                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                567372760                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                69190624                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      368823691                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 437050453                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             128146346                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1061861877                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6771880                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5087051                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 328687                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 662195                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               77193560                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20256                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1009820206                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1635273516                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1255804175                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1470464                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             944392449                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65427754                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           26765768                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23112103                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 102007080                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            173010630                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           150618329                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9860591                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8967243                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1027007600                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27059230                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1042343751                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3268943                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60307743                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33600701                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         312855                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1579791741                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.659798                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.917984                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1579931046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.136373                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.608515                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                522505611                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             567007663                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 431520293                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              49702709                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9194770                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33525771                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3859042                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1080875290                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              28941730                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9194770                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                566963257                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                68325752                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      370117398                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 436739828                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             128590041                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1061188804                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6761282                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               5074872                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 331009                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 667465                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               77645177                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            20261                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1009236679                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1634390089                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1255037462                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1470821                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             943893813                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65342863                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           26761446                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23109655                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 101993436                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            172887729                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           150512713                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9835963                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8956761                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1026341207                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27052915                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1041697414                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3264017                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        60219112                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33542548                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         311458                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1579931046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.659331                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.917837                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           934526324     59.16%     59.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           332943694     21.08%     80.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           234048480     14.82%     95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            71809082      4.55%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6444954      0.41%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19207      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           935073091     59.18%     59.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           332737212     21.06%     80.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           233873919     14.80%     95.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            71794095      4.54%     99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6433566      0.41%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19163      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1579791741                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1579931046                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                57575402     35.04%     35.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 100057      0.06%     35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26740      0.02%     35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                57548727     35.04%     35.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 100099      0.06%     35.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26751      0.02%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.12% # attempts to use FU when none available
@@ -684,19 +679,19 @@ system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.12% # at
 system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              764      0.00%     35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              757      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44168987     26.88%     62.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62424891     38.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44132085     26.87%     62.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              62410380     38.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             717769712     68.86%     68.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2531817      0.24%     69.10% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122691      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             717342377     68.86%     68.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2532202      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                122567      0.01%     69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   8      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
@@ -718,102 +713,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Ty
 system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         121277      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         121087      0.01%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            172853843     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           148944351     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            172736633     16.58%     85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           148842483     14.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1042343751                       # Type of FU issued
-system.cpu.iq.rate                           0.636124                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   164296841                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157623                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3829567748                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1113568735                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1024464263                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2477278                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             947290                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       909965                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1205083989                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1556592                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4287735                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1041697414                       # Type of FU issued
+system.cpu.iq.rate                           0.635511                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   164218799                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157645                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3828331710                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1112806179                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1023834597                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2476979                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             946356                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       909820                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1204359624                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1556578                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4281868                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13755130                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14415                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       142727                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6290239                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13732493                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14369                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       140572                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6281305                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2513645                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1546946                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2514322                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1544139                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9207867                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6935208                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9652893                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1054288001                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9194770                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6870613                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9053250                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1053615244                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             173010630                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            150618329                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           22687803                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  56498                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               9524585                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         142727                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3650015                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5096410                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8746425                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1031209628                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             168969861                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10209992                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             172887729                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            150512713                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           22684457                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  56400                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               8925068                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         140572                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3644333                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5090402                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8734735                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1030574997                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             168857481                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10197714                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        221171                       # number of nop insts executed
-system.cpu.iew.exec_refs                    316030804                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                195653401                       # Number of branches executed
-system.cpu.iew.exec_stores                  147060943                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.629329                       # Inst execution rate
-system.cpu.iew.wb_sent                     1026179606                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1025374228                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 436457494                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 705894723                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        221122                       # number of nop insts executed
+system.cpu.iew.exec_refs                    315819616                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                195518777                       # Number of branches executed
+system.cpu.iew.exec_stores                  146962135                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.628726                       # Inst execution rate
+system.cpu.iew.wb_sent                     1025549780                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1024744417                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 436186320                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 705504935                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.625768                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618304                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.625169                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.618261                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        51232529                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        26746375                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8382033                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1567845308                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.633837                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.270098                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        51156578                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        26741457                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8371043                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1568002280                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.633402                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.269603                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1057713558     67.46%     67.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    286814809     18.29%     85.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120141410      7.66%     93.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36433500      2.32%     95.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28325160      1.81%     97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13966043      0.89%     98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8603569      0.55%     98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4169387      0.27%     99.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11677872      0.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1058124948     67.48%     67.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    286691231     18.28%     85.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    120053535      7.66%     93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36420041      2.32%     95.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28336916      1.81%     97.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     13959603      0.89%     98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8598360      0.55%     98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4160425      0.27%     99.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11657221      0.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1567845308                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            845761974                       # Number of instructions committed
-system.cpu.commit.committedOps              993759083                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1568002280                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            845255961                       # Number of instructions committed
+system.cpu.commit.committedOps              993175006                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      303583589                       # Number of memory references committed
-system.cpu.commit.loads                     159255499                       # Number of loads committed
-system.cpu.commit.membars                     6904959                       # Number of memory barriers committed
-system.cpu.commit.branches                  188760643                       # Number of branches committed
-system.cpu.commit.fp_insts                     896514                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 913055926                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25211674                       # Number of function calls committed.
+system.cpu.commit.refs                      303386643                       # Number of memory references committed
+system.cpu.commit.loads                     159155235                       # Number of loads committed
+system.cpu.commit.membars                     6901293                       # Number of memory barriers committed
+system.cpu.commit.branches                  188640484                       # Number of branches committed
+system.cpu.commit.fp_insts                     896738                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 912506063                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25186659                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        687818920     69.21%     69.21% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2146460      0.22%     69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            98075      0.01%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        687431731     69.22%     69.22% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2146648      0.22%     69.43% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            97945      0.01%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
@@ -840,531 +835,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc       111997      0.01%     69.45% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       159255499     16.03%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      144328090     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       159155235     16.02%     85.48% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      144231408     14.52%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         993759083                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11677872                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2593635375                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2101836328                       # The number of ROB writes
-system.cpu.timesIdled                         8111566                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        58794350                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101024450248                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   845761974                       # Number of Instructions Simulated
-system.cpu.committedOps                     993759083                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.937408                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.937408                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.516154                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.516154                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1220647692                       # number of integer regfile reads
-system.cpu.int_regfile_writes               729132584                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1462075                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   783592                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 224479860                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                225129726                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2563991678                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               26780868                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9656863                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.972805                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           282353083                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9657375                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.237042                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        2742937500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.972805                       # Average occupied blocks per requestor
+system.cpu.commit.op_class_0::total         993175006                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11657221                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2593153041                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2100498051                       # The number of ROB writes
+system.cpu.timesIdled                         8123602                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59217960                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 101023921760                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   845255961                       # Number of Instructions Simulated
+system.cpu.committedOps                     993175006                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.939234                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.939234                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.515668                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.515668                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1219925781                       # number of integer regfile reads
+system.cpu.int_regfile_writes               728690424                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1462315                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   782072                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 224390859                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                225039549                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              2563491272                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               26777143                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9646522                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.972803                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           282175483                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9647034                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.249973                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.972803                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          383                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1233161168                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1233161168                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146769345                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146769345                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127879890                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127879890                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       376551                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        376551                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       324490                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       324490                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3281849                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3281849                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3677222                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3677222                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     274649235                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        274649235                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    275025786                       # number of overall hits
-system.cpu.dcache.overall_hits::total       275025786                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9521174                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9521174                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11203473                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11203473                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1164152                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1164152                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1231188                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1231188                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       446606                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       446606                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1232341715                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1232341715                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146679057                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146679057                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127793945                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127793945                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       377283                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        377283                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       324111                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       324111                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3281173                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3281173                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3676011                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3676011                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     274473002                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        274473002                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    274850285                       # number of overall hits
+system.cpu.dcache.overall_hits::total       274850285                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9506685                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9506685                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11193954                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11193954                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1163770                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1163770                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1231562                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1231562                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       446112                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       446112                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20724647                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20724647                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21888799                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21888799                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 166185133500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 166185133500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 435748871062                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 435748871062                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  89257967135                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  89257967135                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6843268000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6843268000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       276500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       276500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 601934004562                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 601934004562                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 601934004562                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 601934004562                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    156290519                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    156290519                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    139083363                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    139083363                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1540703                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1540703                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1555678                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1555678                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3728455                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3728455                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3677227                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3677227                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    295373882                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    295373882                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    296914585                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    296914585                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060920                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060920                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080552                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080552                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755598                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.755598                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791416                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.791416                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119783                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119783                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_misses::cpu.data     20700639                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20700639                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21864409                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21864409                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 165615263000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 165615263000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 435458645679                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 435458645679                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  89047451888                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  89047451888                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6832433500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6832433500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       275500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       275500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 601073908679                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 601073908679                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 601073908679                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 601073908679                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    156185742                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    156185742                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    138987899                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    138987899                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1541053                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1541053                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1555673                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1555673                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3727285                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3727285                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3676016                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3676016                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    295173641                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    295173641                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    296714694                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    296714694                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060868                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.060868                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080539                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080539                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755178                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.755178                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791659                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.791659                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119688                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119688                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070164                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070164                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073721                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073721                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17454.269137                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17454.269137                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38894.088562                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38894.088562                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72497.431046                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72497.431046                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15322.830414                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15322.830414                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55300                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55300                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29044.354992                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29044.354992                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27499.635981                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27499.635981                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     49670570                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070130                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070130                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073688                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073688                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17420.926748                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17420.926748                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38901.235942                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38901.235942                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72304.481535                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72304.481535                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15315.511576                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15315.511576                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55100                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55100                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29036.490549                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29036.490549                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27490.974427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27490.974427                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     49516087                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1593951                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1592102                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.161918                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.101077                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7468918                       # number of writebacks
-system.cpu.dcache.writebacks::total           7468918                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4425833                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4425833                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9207187                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9207187                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7019                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         7019                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219274                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       219274                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13633020                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13633020                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13633020                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13633020                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5095341                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5095341                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1996286                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1996286                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1157368                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1157368                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224169                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1224169                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227332                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       227332                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      7469877                       # number of writebacks
+system.cpu.dcache.writebacks::total           7469877                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4421127                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4421127                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9198347                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      9198347                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6981                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         6981                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218536                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       218536                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13619474                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total     13619474                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data     13619474                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13619474                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5085558                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5085558                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1995607                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1995607                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1156964                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1156964                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224581                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1224581                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227576                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       227576                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7091627                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7091627                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8248995                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8248995                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7081165                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7081165                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8238129                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8238129                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  83980884000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  83980884000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  76343937421                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  76343937421                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22998470000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22998470000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  87650245635                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  87650245635                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3191570000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3191570000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       271500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       271500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160324821421                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 160324821421                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183323291421                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 183323291421                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5829051500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5829051500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5836628967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5836628967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11665680467                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11665680467                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032602                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032602                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014353                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751195                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751195                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786904                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786904                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060972                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060972                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  83741631500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  83741631500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  76263176167                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  76263176167                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22882989500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22882989500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  87447550388                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  87447550388                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3189935000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3189935000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       270500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       270500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160004807667                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 160004807667                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182887797167                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182887797167                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192854000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192854000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228264964                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228264964                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12421118964                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12421118964                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032561                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032561                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014358                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014358                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.750762                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.750762                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787171                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787171                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061057                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061057                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024009                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024009                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027782                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027782                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16481.896697                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16481.896697                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38242.985935                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38242.985935                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19871.354660                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19871.354660                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71599.791887                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71599.791887                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14039.246564                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14039.246564                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54300                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54300                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22607.621836                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22607.621836                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22223.712273                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22223.712273                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173081.878378                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173081.878378                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173214.297454                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173214.297454                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173148.105605                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 173148.105605                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023990                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.023990                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027764                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027764                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16466.557160                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16466.557160                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38215.528492                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38215.528492                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19778.480143                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19778.480143                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71410.180615                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71410.180615                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14017.009702                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14017.009702                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54100                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54100                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22595.831006                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22595.831006                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22200.161853                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22200.161853                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183884.256785                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183884.256785                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184836.923196                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184836.923196                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184360.717250                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184360.717250                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          15000702                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.916861                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           339450182                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          15001214                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.628181                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       24732660500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.916861                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          14982836                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.916862                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           339236129                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          14983348                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.640876                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       24730722500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.916862                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999838                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999838                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         370220442                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        370220442                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    339450182                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       339450182                       # number of ReadReq hits
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-system.cpu.icache.demand_hits::total        339450182                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    339450182                       # number of overall hits
-system.cpu.icache.overall_hits::total       339450182                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15768830                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15768830                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15768830                       # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::cpu.inst     15768830                       # number of overall misses
-system.cpu.icache.overall_misses::total      15768830                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 212844795884                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 212844795884                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 212844795884                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 212844795884                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 212844795884                       # number of overall miss cycles
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-system.cpu.icache.ReadReq_accesses::cpu.inst    355219012                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    355219012                       # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total    355219012                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044392                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044392                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044392                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.044392                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.044392                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044392                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13497.817903                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13497.817903                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13497.817903                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13497.817903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13497.817903                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13497.817903                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        22619                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         369968151                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        369968151                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    339236129                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044364                       # miss rate for ReadReq accesses
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+system.cpu.icache.overall_miss_rate::total     0.044364                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13513.184590                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13513.184590                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13513.184590                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13513.184590                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        22549                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1385                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1395                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.331408                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.164158                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       767400                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       767400                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       767400                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       767400                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       767400                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       767400                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15001430                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     15001430                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     15001430                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     15001430                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     15001430                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     15001430                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21295                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.ReadReq_mshr_uncacheable::total        21295                       # number of ReadReq MSHR uncacheable
-system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total        21295                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190561779393                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 190561779393                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190561779393                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 190561779393                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190561779393                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 190561779393                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684494000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684494000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684494000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   2684494000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042231                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042231                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042231                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.042231                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042231                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.042231                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12702.907616                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12702.907616                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12702.907616                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12702.907616                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12702.907616                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12702.907616                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126062.174219                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126062.174219                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126062.174219                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126062.174219                       # average overall mshr uncacheable latency
+system.cpu.icache.writebacks::writebacks     14982836                       # number of writebacks
+system.cpu.icache.writebacks::total          14982836                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       764882                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total       764882                       # number of ReadReq MSHR hits
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+system.cpu.icache.overall_mshr_hits::total       764882                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     14983570                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     14983570                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     14983570                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total     14983570                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190589950887                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 190589950887                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190589950887                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 190589950887                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190589950887                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 190589950887                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042209                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.042209                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.042209                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12719.929288                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1125228                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65275.787267                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           45935367                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1186879                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.702654                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      22917959500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37021.466735                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   280.855675                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   393.338533                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8151.985016                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19428.141309                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.564903                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004286                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124389                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.296450                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996029                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          269                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61382                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          269                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          550                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2696                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5155                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52911                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004105                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.936615                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        407946828                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       407946828                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       779449                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       298283                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1077732                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      7468918                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      7468918                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9287                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9287                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.replacements          1120546                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65234.831512                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           45882504                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1182138                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            38.813154                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      22908442500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37014.981518                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   292.089334                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   422.524862                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8026.847283                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19478.388514                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.564804                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004457                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006447                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.122480                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.297217                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995405                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          295                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        61297                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          295                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2697                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5154                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52826                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004501                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.935318                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        407493288                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       407493288                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       779225                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       298670                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1077895                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      7469877                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      7469877                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     14980289                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     14980289                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         9372                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         9372                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1568942                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1568942                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14917877                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14917877                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6228350                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6228350                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       729417                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       729417                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       779449                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       298283                       # number of demand (read+write) hits
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-system.cpu.l2cache.demand_hits::total        23792901                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       779449                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       298283                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14917877                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7797292                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23792901                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3205                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3074                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6279                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        33824                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        33824                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1568886                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1568886                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14901485                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     14901485                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6220691                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6220691                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       731394                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       731394                       # number of InvalidateReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker       779225                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::total       23768957                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3206                       # number of ReadReq misses
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+system.cpu.l2cache.ReadReq_misses::total         6380                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data        33876                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total        33876                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       387344                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       387344                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83351                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        83351                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       248584                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       248584                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       494751                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       494751                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         3205                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         3074                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        83351                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       635928                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        725558                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         3205                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         3074                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        83351                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       635928                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       725558                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    442457500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    428037500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    870495000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1416950000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total   1416950000                       # number of UpgradeReq miss cycles
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+system.cpu.l2cache.ReadExReq_misses::total       386656                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        81874                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        81874                       # number of ReadCleanReq misses
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+system.cpu.l2cache.ReadSharedReq_misses::total       246229                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       493187                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       493187                       # number of InvalidateReq misses
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+system.cpu.l2cache.UpgradeReq_miss_latency::total   1421351500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  53765073500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11215140000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total  11215140000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  34510288000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  34510288000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  76701730500                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.InvalidateReq_miss_latency::total  76701730500                       # number of InvalidateReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    442457500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    428037500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  11215140000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    428037500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  11215140000                       # number of overall miss cycles
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-system.cpu.l2cache.Writeback_accesses::writebacks      7468918                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      7468918                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43111                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total        43111                       # number of UpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1956286                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1956286                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15001228                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     15001228                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6476934                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      6476934                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224168                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1224168                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       782654                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       301357                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     15001228                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      8433220                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     24518459                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       782654                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       301357                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     15001228                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      8433220                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     24518459                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004095                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010201                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.005792                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.784579                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.784579                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1955542                       # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     14983359                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6466920                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      6466920                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224581                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1224581                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       782431                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       301844                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       782431                       # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010515                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.005884                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.783296                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783296                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.198000                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.198000                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005556                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005556                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038380                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038380                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.404153                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.404153                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004095                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010201                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005556                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.075407                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.029592                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004095                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010201                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005556                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.075407                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.029592                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138052.262090                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139244.469746                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 138635.929288                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41891.851939                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41891.851939                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.197723                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.197723                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005464                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005464                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038075                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038075                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.402739                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402739                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for demand accesses
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41957.477270                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138804.456762                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138804.456762                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134553.154731                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134553.154731                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138827.470795                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138827.470795                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155030.976188                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155030.976188                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138052.262090                       # average overall miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134553.154731                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138813.452938                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 138322.500062                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138052.262090                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139244.469746                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134553.154731                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138813.452938                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 138322.500062                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138807.494258                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134607.335662                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134607.335662                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138900.901194                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138900.901194                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155058.604546                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155058.604546                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 138356.690596                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 138356.690596                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1373,200 +1374,201 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       945403                       # number of writebacks
-system.cpu.l2cache.writebacks::total           945403                       # number of writebacks
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           20                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           20                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           20                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           20                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           20                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           20                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3205                       # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_misses::total         6279                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1050                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1050                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33824                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        33824                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks       943662                       # number of writebacks
+system.cpu.l2cache.writebacks::total           943662                       # number of writebacks
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           19                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           19                       # number of ReadSharedReq MSHR hits
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+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
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 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       387344                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       387344                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83351                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83351                       # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       494751                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       494751                       # number of InvalidateReq MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54973                       # number of ReadReq MSHR uncacheable
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 system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21295                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88669                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    410407500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    397297500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    807705000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2393374500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2393374500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    405137000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    817584000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2397445500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2397445500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49891633500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49891633500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10381630000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10381630000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  32021997500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  32021997500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  71754220500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  71754220500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    410407500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    397297500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10381630000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  81913631000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  93102966000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    410407500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    397297500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10381630000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  81913631000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  93102966000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418306500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5408063000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7826369500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5444622000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5444622000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418306500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10852685000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  13270991500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004095                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010201                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005792                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49804190500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49804190500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10202101000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10202101000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31736616500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31736616500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  71541018000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  71541018000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    405137000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10202101000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  81540807000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  92560492000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    405137000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10202101000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  81540807000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  92560492000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5771724000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8190487000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836234500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836234500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607958500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14026721500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005884                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784579                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784579                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783296                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783296                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.198000                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.198000                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005556                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005556                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038377                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038377                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.404153                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.404153                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004095                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010201                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005556                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.075405                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.029592                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004095                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010201                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005556                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.075405                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.029592                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129244.469746                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128635.929288                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70759.652909                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70759.652909                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.197723                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.197723                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005464                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038072                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038072                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402739                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402739                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.029445                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.029445                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128147.962382                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70771.209706                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70771.209706                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128804.456762                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128804.456762                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124553.154731                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124553.154731                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128827.977905                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128827.977905                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145030.976188                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145030.976188                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129244.469746                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124553.154731                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128813.650717                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128322.659874                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129244.469746                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124553.154731                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128813.650717                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128322.659874                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160581.477522                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142367.516781                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161580.662393                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161580.662393                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161081.203432                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149668.897811                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128807.494258                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128807.494258                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124607.335662                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128900.599082                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128900.599082                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145058.604546                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145058.604546                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171379.654374                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148993.796842                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173202.590812                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173202.590812                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172291.366106                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158193.728290                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     50050277                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     25391485                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3463                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2168                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2168                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     49994853                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     25364266                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3498                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2149                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2149                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1617253                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23096406                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1617841                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23069110                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8520965                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     17374022                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43114                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8520195                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     14980289                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2361594                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43251                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43119                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1956286                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1956286                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     15001430                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6485775                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1330832                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1224168                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45043419                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29192673                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       728958                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1917333                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          76882383                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    960419312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1017977630                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2410856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6261232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1987069030                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1835462                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     52366647                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.013365                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.114833                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43256                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1955542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1955542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     14983570                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6475758                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1331245                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1224581                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     44989806                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29161893                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       729252                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1917892                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          76798843                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1918014176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1017349854                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2414752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6259448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2944038230                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1831110                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     27676926                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025201                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.156737                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           51666749     98.66%     98.66% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             699898      1.34%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           26979426     97.48%     97.48% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             697500      2.52%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       52366647                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    32990991996                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       27676926                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    47946942997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1490388                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1474889                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22530796241                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22505485675                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13336103780                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13321051501                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     427917846                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     427763271                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1135029759                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1135810761                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40289                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40289                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40286                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40286                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1585,11 +1587,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230936                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230936                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230930                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230930                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353720                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353714                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1606,104 +1608,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334176                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492096                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492072                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41870500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25173000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              168500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            36497500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              129000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565927033                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           565751099                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               44500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147696000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147690000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115449                       # number of replacements
-system.iocache.tags.tagsinuse               10.422254                       # Cycle average of tags in use
+system.iocache.tags.replacements               115446                       # number of replacements
+system.iocache.tags.tagsinuse               10.422238                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115465                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115462                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13103107121000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.543889                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.878365                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221493                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429898                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651391                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13103145499000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.543896                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.878342                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221494                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429896                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651390                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039569                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039569                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039542                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039542                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8804                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8841                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8801                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8838                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8804                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8844                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8801                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8841                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8804                       # number of overall misses
-system.iocache.overall_misses::total             8844                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5106000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1685439007                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1690545007                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8801                       # number of overall misses
+system.iocache.overall_misses::total             8841                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1693888006                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1698957506                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13827154026                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13827154026                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5457000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1685439007                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1690896007                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5457000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1685439007                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1690896007                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13866022593                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13866022593                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1693888006                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1699308506                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1693888006                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1699308506                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8804                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8841                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8801                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8838                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8804                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8844                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8801                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8841                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8804                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8844                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8801                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8841                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1717,55 +1719,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       138000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 191440.141640                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 191216.492139                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 192465.402341                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 192233.254809                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129632.809814                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129632.809814                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       136425                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 191440.141640                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 191191.316938                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       136425                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 191440.141640                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 191191.316938                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34672                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129997.211740                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129997.211740                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 192207.726049                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 192207.726049                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         36226                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3494                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3621                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.923297                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.004419                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8804                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8841                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8801                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8838                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8804                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8844                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8801                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8841                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8804                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8844                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3256000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1245239007                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1248495007                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8801                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8841                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1253838006                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1257057506                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8493954026                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8493954026                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3457000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1245239007                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1248696007                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3457000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1245239007                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1248696007                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8532822593                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8532822593                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1253838006                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1257258506                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1253838006                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1257258506                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1779,73 +1781,73 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        88000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141440.141640                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 141216.492139                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142465.402341                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 142233.254809                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79632.809814                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79632.809814                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        86425                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 141440.141640                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 141191.316938                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        86425                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 141440.141640                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 141191.316938                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79997.211740                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79997.211740                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54973                       # Transaction distribution
-system.membus.trans_dist::ReadResp             402008                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
+system.membus.trans_dist::ReadResp             398274                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::Writeback           1052033                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           186512                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34605                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1050292                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           182485                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34687                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           34608                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            881317                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           881317                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        347035                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           34690                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            879035                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           879035                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        343302                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           60                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3680509                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3810131                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342394                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342394                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4152525                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3662907                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3792527                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342336                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342336                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4134863                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          436                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    138873356                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    139043342                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7266048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7266048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               146309390                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2606                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2698981                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    138377164                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    138547134                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7264192                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               145811326                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2632                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2687314                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2698981    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2687314    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2698981                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           104149000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2687314                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103976500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               33000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy               32000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5470500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5452000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7144084722                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7124848125                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6645299856                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6613283400                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228305891                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227684837                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
index 7ab4128ed..62fa4c4f2 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
@@ -4,53 +4,53 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 549288                       # Simulator instruction rate (inst/s)
-host_op_rate                                   645503                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            28514691627                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 672288                       # Number of bytes of host memory used
-host_seconds                                  1792.45                       # Real time elapsed on the host
+host_inst_rate                                1110267                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1304746                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            57636324297                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 725492                       # Number of bytes of host memory used
+host_seconds                                   886.79                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker       412352                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker       376704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5543028                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         110110088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5485940                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         110128008                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide        442112                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            116884284                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5543028                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5543028                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103060480                       # Number of bytes written to this memory
+system.physmem.bytes_read::total            116845116                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5485940                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5485940                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103078272                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103081060                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103098852                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker         6443                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker         5886                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             127017                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1720483                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             126125                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1720763                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide           6908                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1866737                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1610320                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1866125                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1610598                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1612893                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1613171                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker           8068                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker           7370                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               108450                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2154326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               107334                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2154677                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide             8650                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2286865                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108450                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108450                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2016399                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2286098                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          107334                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107334                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2016747                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2016802                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2016399                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2017150                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2016747                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker          8068                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker          7370                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108450                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2154729                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              107334                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2155079                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide            8650                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4303666                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4303248                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8921279                       # number of writebacks
-system.cpu.dcache.writebacks::total           8921279                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      8921277                       # number of writebacks
+system.cpu.dcache.writebacks::total           8921277                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements          14295641                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
@@ -411,23 +411,25 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks     14295641                       # number of writebacks
+system.cpu.icache.writebacks::total          14295641                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1722572                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65341.862554                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46966735                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1785868                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            26.299108                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1723188                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65341.862570                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46967342                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1786484                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            26.290379                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.195568                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.733962                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6290.976194                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.566080                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 37239.479155                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.194068                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.716842                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6119.396908                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 21229.075596                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.568229                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004733                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006771                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095993                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.323461                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.093375                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.323930                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997038                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        63018                       # Occupied blocks per task id
@@ -439,33 +441,35 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4910
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54670                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961578                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        426185247                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       426185247                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses        426185861                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       426185861                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       506612                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255620                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         762232                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      8921279                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      8921279                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      8921277                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      8921277                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     14294063                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     14294063                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data        11223                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total        11223                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1692559                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1692559                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14212229                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14212229                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7504111                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      7504111                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       694322                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       694322                       # number of InvalidateReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1692549                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1692549                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14213121                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     14213121                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7503843                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      7503843                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       694318                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       694318                       # number of InvalidateReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker       506612                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker       255620                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14212229                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      9196670                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        24171131                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     14213121                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      9196392                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        24171745                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker       506612                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker       255620                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14212229                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      9196670                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       24171131                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     14213121                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      9196392                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       24171745                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6443                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5886                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total        12329                       # number of ReadReq misses
@@ -473,29 +477,31 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data        39917
 system.cpu.l2cache.UpgradeReq_misses::total        39917                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       826558                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       826558                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83929                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        83929                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       344087                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       344087                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       551027                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       551027                       # number of InvalidateReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       826568                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       826568                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83037                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        83037                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       344355                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       344355                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       551031                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       551031                       # number of InvalidateReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker         6443                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker         5886                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        83929                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1170645                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1266903                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        83037                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1170923                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1266289                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker         6443                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker         5886                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        83929                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1170645                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1266903                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        83037                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1170923                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1266289                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       513055                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       261506                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       774561                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      8921279                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      8921279                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      8921277                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      8921277                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     14294063                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     14294063                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data        51140                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total        51140                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
@@ -525,24 +531,24 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780544
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780544                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328114                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.328114                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005871                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005871                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043843                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043843                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442468                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442468                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328118                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.328118                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005808                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005808                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043877                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043877                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442471                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442471                       # miss rate for InvalidateReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022508                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005871                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.112917                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.049803                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005808                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.112944                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.049779                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022508                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005871                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.112917                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.049803                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005808                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.112944                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.049779                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -551,21 +557,22 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1503689                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1503689                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1503967                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1503967                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     52457192                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     26548378                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1747                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2719                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2719                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2724                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2724                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq        1227763                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp      23372119                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33606                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8921279                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     16984756                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8921277                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     14294063                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2690695                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq        51140                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp        51141                       # Transaction distribution
@@ -580,23 +587,23 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758224                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1543944                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total          80348699                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    915126612                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1234659686                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1829946644                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1234659558                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032896                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6175776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2158994970                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1954373                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     55082670                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size::total         3073814874                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1954989                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     55083286                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.010814                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.103427                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           54487002     98.92%     98.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             595668      1.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           54487613     98.92%     98.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             595673      1.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       55082670                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       55083286                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                40246                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40246                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
@@ -710,47 +717,47 @@ system.iocache.writebacks::writebacks          106631                       # nu
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
-system.membus.trans_dist::ReadResp             525878                       # Transaction distribution
+system.membus.trans_dist::ReadResp             525254                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::Writeback           1610320                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           225581                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40484                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1610598                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           224691                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            40486                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40485                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1377021                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1377021                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        449199                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           40487                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1377033                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1377033                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        448575                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5529643                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5658835                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5527811                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5657003                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       344374                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       344374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6003209                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6001377                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    212740640                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    212909690                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    212719264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    212888314                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7391040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      7391040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               220300730                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               220279354                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3921686                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3920464                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3921686    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3920464    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3921686                       # Request fanout histogram
+system.membus.snoop_fanout::total             3920464                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
index 3e7b5ca50..1811873d2 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -4,74 +4,74 @@ sim_seconds                                 47.216814                       # Nu
 sim_ticks                                47216814145000                       # Number of ticks simulated
 final_tick                               47216814145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 645560                       # Simulator instruction rate (inst/s)
-host_op_rate                                   759443                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            31248192864                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 683532                       # Number of bytes of host memory used
-host_seconds                                  1511.03                       # Real time elapsed on the host
+host_inst_rate                                1058185                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1244860                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            51221233754                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 733588                       # Number of bytes of host memory used
+host_seconds                                   921.82                       # Real time elapsed on the host
 sim_insts                                   975457230                       # Number of instructions simulated
 sim_ops                                    1147538415                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       152640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       127168                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3766772                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         62976200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       221312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       220864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2509128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         46395632                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        419264                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            116788980                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3766772                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2509128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6275900                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    100984448                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       152064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       126912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3862964                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         62933832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       221952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       220096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2661000                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         46409840                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        419200                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            117007860                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3862964                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2661000                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6523964                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    100926976                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         101005032                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2385                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1987                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             99263                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            984016                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3458                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         3451                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             39312                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            724948                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6551                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1865371                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1577882                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total         100947560                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2376                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1983                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            100766                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            983354                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         3468                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         3439                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             41685                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            725170                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6550                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1868791                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1576984                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1580456                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3233                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               79776                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1333766                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          4687                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          4678                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               53141                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              982608                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8880                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2473462                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          79776                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          53141                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             132917                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2138739                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1579558                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3221                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2688                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               81813                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1332869                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          4701                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          4661                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               56357                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              982909                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8878                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2478097                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          81813                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          56357                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             138170                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2137522                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                436                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2139175                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2138739                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3233                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              79776                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1334202                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         4687                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         4678                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              53141                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             982608                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8880                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4612637                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2137958                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2137522                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3221                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2688                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              81813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1333305                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         4701                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         4661                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              56357                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             982909                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8878                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4616055                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
@@ -321,36 +321,36 @@ system.cpu0.dcache.tags.tag_accesses        363162248                       # Nu
 system.cpu0.dcache.tags.data_accesses       363162248                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data     86214911                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total       86214911                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     80919852                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      80919852                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     80912298                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      80912298                       # number of WriteReq hits
 system.cpu0.dcache.SoftPFReq_hits::cpu0.data       215654                       # number of SoftPFReq hits
 system.cpu0.dcache.SoftPFReq_hits::total       215654                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       262009                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       262009                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       262024                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       262024                       # number of WriteLineReq hits
 system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2076466                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total      2076466                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2036568                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      2036568                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    167134763                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       167134763                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    167350417                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      167350417                       # number of overall hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2036634                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      2036634                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    167127209                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       167127209                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    167342863                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      167342863                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data      3309382                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      3309382                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1475590                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1475590                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1483144                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1483144                       # number of WriteReq misses
 system.cpu0.dcache.SoftPFReq_misses::cpu0.data       772139                       # number of SoftPFReq misses
 system.cpu0.dcache.SoftPFReq_misses::total       772139                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       831711                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       831711                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       831696                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       831696                       # number of WriteLineReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       119816                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total       119816                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       158575                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       158575                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4784972                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4784972                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5557111                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5557111                       # number of overall misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       158509                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       158509                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      4792526                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4792526                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5564665                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5564665                       # number of overall misses
 system.cpu0.dcache.ReadReq_accesses::cpu0.data     89524293                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total     89524293                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data     82395442                       # number of WriteReq accesses(hits+misses)
@@ -369,20 +369,20 @@ system.cpu0.dcache.overall_accesses::cpu0.data    172907528
 system.cpu0.dcache.overall_accesses::total    172907528                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036966                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.036966                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017909                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.017909                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018000                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018000                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781681                       # miss rate for SoftPFReq accesses
 system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781681                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.760442                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.760442                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.760429                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.760429                       # miss rate for WriteLineReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054554                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054554                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.072239                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.072239                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027833                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027833                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032139                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032139                       # miss rate for overall accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.072209                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.072209                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027877                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.027877                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032183                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.032183                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -391,8 +391,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      4465852                       # number of writebacks
-system.cpu0.dcache.writebacks::total          4465852                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks      6272771                       # number of writebacks
+system.cpu0.dcache.writebacks::total          6272771                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements          5539081                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.989005                       # Cycle average of tags in use
@@ -443,6 +443,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks::writebacks      5539081                       # number of writebacks
+system.cpu0.icache.writebacks::total          5539081                       # number of writebacks
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
@@ -450,96 +452,96 @@ system.cpu0.l2cache.prefetcher.pfBufferHit            0                       #
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2711851                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16210.481258                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          18787660                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2727832                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.887396                       # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.replacements         2670833                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16144.496707                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          15583793                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2686790                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            5.800153                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  5681.130997                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    53.077110                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    57.001745                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4560.666382                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  5858.605025                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.346749                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003240                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003479                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.278361                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.357581                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.989409                       # Average percentage of cache occupancy
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-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15935                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 16059.102143                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    41.665572                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    43.728993                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.980170                       # Average percentage of cache occupancy
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+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15907                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           35                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          229                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1157                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4616                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5323                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4610                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.002808                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.972595                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       396153496                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      396153496                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       271024                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       142798                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        413822                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      4465852                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      4465852                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data         3520                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total         3520                       # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       634528                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       634528                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4971317                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      4971317                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2943098                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2943098                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       222986                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       222986                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       271024                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       142798                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      4971317                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3577626                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        8962765                       # number of demand (read+write) hits
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-system.cpu0.l2cache.overall_hits::cpu0.inst      4971317                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3577626                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       8962765                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11253                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8486                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        19739                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       128216                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       128216                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       158575                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       158575                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       709702                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       709702                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       568281                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       568281                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1258239                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total      1258239                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       608349                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       608349                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11253                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8486                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       568281                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1967941                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      2555961                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11253                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8486                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       568281                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1967941                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      2555961                       # number of overall misses
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       282277                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       151284                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       433561                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks      4465852                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total      4465852                       # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       131736                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       131736                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       158575                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       158575                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          242                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1465                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4378                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5313                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         4509                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003052                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.970886                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       397685392                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      397685392                       # Number of data accesses
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+system.cpu0.l2cache.ReadReq_hits::total        457410                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      4459579                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      4459579                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      7350874                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      7350874                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          760                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total          760                       # number of UpgradeReq hits
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+system.cpu0.l2cache.ReadExReq_hits::total       635944                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5035825                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5035825                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2962064                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2962064                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       223971                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       223971                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       298097                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       159313                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      5035825                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3598008                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        9091243                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       298097                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       159313                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      5035825                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3598008                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       9091243                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11326                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8418                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        19744                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       138515                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       138515                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       158509                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       158509                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       708286                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       708286                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       503773                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       503773                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1239273                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total      1239273                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       607364                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       607364                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11326                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8418                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       503773                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1947559                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      2471076                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11326                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8418                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       503773                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1947559                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      2471076                       # number of overall misses
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       309423                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       167731                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       477154                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4459579                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      4459579                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      7350874                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      7350874                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       139275                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       139275                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       158509                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       158509                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1344230                       # number of ReadExReq accesses(hits+misses)
 system.cpu0.l2cache.ReadExReq_accesses::total      1344230                       # number of ReadExReq accesses(hits+misses)
 system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5539598                       # number of ReadCleanReq accesses(hits+misses)
@@ -548,41 +550,41 @@ system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4201337
 system.cpu0.l2cache.ReadSharedReq_accesses::total      4201337                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       831335                       # number of InvalidateReq accesses(hits+misses)
 system.cpu0.l2cache.InvalidateReq_accesses::total       831335                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       282277                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       151284                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       309423                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       167731                       # number of demand (read+write) accesses
 system.cpu0.l2cache.demand_accesses::cpu0.inst      5539598                       # number of demand (read+write) accesses
 system.cpu0.l2cache.demand_accesses::cpu0.data      5545567                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     11518726                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       282277                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       151284                       # number of overall (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total     11562319                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       309423                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       167731                       # number of overall (read+write) accesses
 system.cpu0.l2cache.overall_accesses::cpu0.inst      5539598                       # number of overall (read+write) accesses
 system.cpu0.l2cache.overall_accesses::cpu0.data      5545567                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     11518726                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.039865                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.056093                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.045528                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.973280                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.973280                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.overall_accesses::total     11562319                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.036604                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.050188                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.041379                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.994543                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.994543                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.527962                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.527962                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.102585                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.102585                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.299485                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.299485                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.731774                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.731774                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.039865                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.056093                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.102585                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.354867                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.221896                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.039865                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.056093                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.102585                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.354867                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.221896                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.526908                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.526908                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.090940                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.090940                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.294971                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.294971                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.730589                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.730589                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.036604                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.050188                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.090940                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.351192                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.213718                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.036604                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.050188                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.090940                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.351192                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.213718                       # miss rate for overall accesses
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -591,24 +593,24 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1571493                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1571493                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks      1567377                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1567377                       # number of writebacks
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     24275029                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12358536                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_requests     24282502                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12366009                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1399                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       471082                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       471076                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      1791227                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1790958                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          269                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu0.toL2Bus.trans_dist::ReadReq        623009                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadResp     10363944                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteReq        32419                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::WriteResp        32419                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      4465852                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      7344601                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       131736                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       158575                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       290311                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      4459579                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      7350874                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       139275                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       158509                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       297784                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadExReq      1344230                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadExResp      1344230                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5539598                       # Transaction distribution
@@ -616,27 +618,27 @@ system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4201337
 system.cpu0.toL2Bus.trans_dist::InvalidateReq       831335                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::InvalidateResp       831335                       # Transaction distribution
 system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16703618                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19736583                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19751529                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       366654                       # Packet count per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       728076                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         37534931                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    354706772                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    640924169                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         37549877                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    709149780                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    756535625                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1466616                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2912304                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1000009861                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    4846239                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     29334646                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.024894                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.155804                       # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size::total        1470064325                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    6119333                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     30615399                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.066982                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.250025                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          28604393     97.51%     97.51% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            730247      2.49%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2                 6      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          28565001     93.30%     93.30% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2050129      6.70%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               269      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      29334646                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total      30615399                       # Request fanout histogram
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -853,36 +855,36 @@ system.cpu1.dcache.tags.tag_accesses        348813711                       # Nu
 system.cpu1.dcache.tags.data_accesses       348813711                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data     83697564                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total       83697564                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     76990146                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      76990146                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     76981821                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      76981821                       # number of WriteReq hits
 system.cpu1.dcache.SoftPFReq_hits::cpu1.data       187854                       # number of SoftPFReq hits
 system.cpu1.dcache.SoftPFReq_hits::total       187854                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        63440                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        63440                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        63451                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        63451                       # number of WriteLineReq hits
 system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2062256                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total      2062256                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2048851                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      2048851                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    160687710                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       160687710                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    160875564                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      160875564                       # number of overall hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2048602                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      2048602                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    160679385                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       160679385                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    160867239                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      160867239                       # number of overall hits
 system.cpu1.dcache.ReadReq_misses::cpu1.data      3358222                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total      3358222                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1453330                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1453330                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1461655                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1461655                       # number of WriteReq misses
 system.cpu1.dcache.SoftPFReq_misses::cpu1.data       792351                       # number of SoftPFReq misses
 system.cpu1.dcache.SoftPFReq_misses::total       792351                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       427059                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       427059                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       427048                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       427048                       # number of WriteLineReq misses
 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       146820                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total       146820                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       158898                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       158898                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4811552                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4811552                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5603903                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5603903                       # number of overall misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       159147                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       159147                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4819877                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4819877                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5612228                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5612228                       # number of overall misses
 system.cpu1.dcache.ReadReq_accesses::cpu1.data     87055786                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total     87055786                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::cpu1.data     78443476                       # number of WriteReq accesses(hits+misses)
@@ -901,20 +903,20 @@ system.cpu1.dcache.overall_accesses::cpu1.data    166479467
 system.cpu1.dcache.overall_accesses::total    166479467                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038576                       # miss rate for ReadReq accesses
 system.cpu1.dcache.ReadReq_miss_rate::total     0.038576                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018527                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018527                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018633                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.018633                       # miss rate for WriteReq accesses
 system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.808352                       # miss rate for SoftPFReq accesses
 system.cpu1.dcache.SoftPFReq_miss_rate::total     0.808352                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.870662                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.870662                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.870640                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.870640                       # miss rate for WriteLineReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.066462                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.066462                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.071973                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.071973                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029073                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.029073                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033661                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.033661                       # miss rate for overall accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.072086                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.072086                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029123                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.029123                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033711                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.033711                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -923,8 +925,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      4029235                       # number of writebacks
-system.cpu1.dcache.writebacks::total          4029235                       # number of writebacks
+system.cpu1.dcache.writebacks::writebacks      5945049                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5945049                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.icache.tags.replacements          4741297                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          496.426080                       # Cycle average of tags in use
@@ -974,6 +976,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu1.icache.writebacks::writebacks      4741297                       # number of writebacks
+system.cpu1.icache.writebacks::total          4741297                       # number of writebacks
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
 system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
@@ -981,98 +985,96 @@ system.cpu1.l2cache.prefetcher.pfBufferHit            0                       #
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
 system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2280083                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13449.950084                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          17410791                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2296131                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            7.582664                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9726491516500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  5225.723861                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    68.459971                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    87.577044                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2849.184130                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  5219.005079                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.318953                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004178                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005345                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.173900                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.318543                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.820920                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023          105                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15943                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           68                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           11                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1612                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5944                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4501                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3801                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006409                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.973083                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       360471879                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      360471879                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       324612                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       139654                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        464266                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      4029235                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      4029235                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         3866                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total         3866                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       614223                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       614223                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4216163                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4216163                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3057520                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      3057520                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       161092                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       161092                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       324612                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       139654                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4216163                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3671743                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8352172                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       324612                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       139654                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4216163                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3671743                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8352172                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12357                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9710                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        22067                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       133787                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       133787                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       158898                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       158898                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       701667                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       701667                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       525646                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       525646                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1239873                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total      1239873                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       265754                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       265754                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12357                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9710                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       525646                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1941540                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      2489253                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12357                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9710                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       525646                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1941540                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      2489253                       # number of overall misses
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       336969                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       149364                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       486333                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      4029235                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      4029235                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       137653                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       137653                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       158898                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       158898                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.tags.replacements         2235881                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13334.612647                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          14249550                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2251891                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            6.327815                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9713557375000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 13222.980748                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    46.246601                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    65.385297                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.807067                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002823                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003991                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.813880                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           89                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15921                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           56                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           14                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           19                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1627                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         6185                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4247                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3746                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005432                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.971741                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       361919913                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      361919913                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       346945                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       153602                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        500547                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      4020160                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      4020160                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      6665818                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      6665818                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1056                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total         1056                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       614983                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       614983                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4283593                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4283593                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3077520                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total      3077520                       # number of ReadSharedReq hits
+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       161463                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       161463                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       346945                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       153602                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      4283593                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3692503                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        8476643                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       346945                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       153602                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4283593                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3692503                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       8476643                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12460                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9763                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        22223                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       144911                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       144911                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       159147                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       159147                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       700907                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       700907                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       458216                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       458216                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1219873                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total      1219873                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       265383                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       265383                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12460                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9763                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       458216                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1920780                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      2401219                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12460                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9763                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       458216                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1920780                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      2401219                       # number of overall misses
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       359405                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       163365                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       522770                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      4020160                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      4020160                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      6665818                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      6665818                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       145967                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       145967                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       159147                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       159147                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1315890                       # number of ReadExReq accesses(hits+misses)
 system.cpu1.l2cache.ReadExReq_accesses::total      1315890                       # number of ReadExReq accesses(hits+misses)
 system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4741809                       # number of ReadCleanReq accesses(hits+misses)
@@ -1081,41 +1083,41 @@ system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4297393
 system.cpu1.l2cache.ReadSharedReq_accesses::total      4297393                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       426846                       # number of InvalidateReq accesses(hits+misses)
 system.cpu1.l2cache.InvalidateReq_accesses::total       426846                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       336969                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       149364                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       359405                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       163365                       # number of demand (read+write) accesses
 system.cpu1.l2cache.demand_accesses::cpu1.inst      4741809                       # number of demand (read+write) accesses
 system.cpu1.l2cache.demand_accesses::cpu1.data      5613283                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     10841425                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       336969                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       149364                       # number of overall (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     10877862                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       359405                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       163365                       # number of overall (read+write) accesses
 system.cpu1.l2cache.overall_accesses::cpu1.inst      4741809                       # number of overall (read+write) accesses
 system.cpu1.l2cache.overall_accesses::cpu1.data      5613283                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     10841425                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.036671                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.065009                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.045374                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.971915                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.971915                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.overall_accesses::total     10877862                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.034668                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.059762                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.042510                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.992765                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.992765                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.533226                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.533226                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.110853                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.110853                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.288517                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.288517                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.622599                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.622599                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.036671                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.065009                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.110853                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.345883                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.229606                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.036671                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.065009                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.110853                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.345883                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.229606                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.532649                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.532649                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.096633                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.096633                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.283863                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.283863                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.621730                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.621730                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.034668                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.059762                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.096633                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.342185                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.220744                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.034668                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.059762                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.096633                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.342185                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.220744                       # miss rate for overall accesses
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1124,24 +1126,24 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1182496                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1182496                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks      1179503                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1179503                       # number of writebacks
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     22040452                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11258515                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_requests     22049015                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11267078                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          368                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       465210                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       465207                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      1760820                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1760650                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          170                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu1.toL2Bus.trans_dist::ReadReq        606211                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadResp      9645413                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq         6383                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp         6383                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      4029235                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      6656743                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       137653                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       158898                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       296551                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4020160                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      6665818                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       145967                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       159147                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       305114                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadExReq      1315890                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadExResp      1315890                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4741809                       # Transaction distribution
@@ -1149,27 +1151,27 @@ system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4297393
 system.cpu1.toL2Bus.trans_dist::InvalidateReq       426846                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::InvalidateResp       426846                       # Transaction distribution
 system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14225112                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18643588                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18660714                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       364008                       # Packet count per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       835436                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         34068144                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    303476296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    617159548                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         34085270                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    606915272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    739752124                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1456032                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3341744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         925433620                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    4444908                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     26656221                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.027820                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.164457                       # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size::total        1351465172                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    5690396                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     27910438                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.072996                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.260153                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          25914657     97.22%     97.22% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            741561      2.78%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2                 3      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          25873264     92.70%     92.70% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2037004      7.30%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               170      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      26656221                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total      27910438                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136634                       # Transaction distribution
@@ -1282,192 +1284,191 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks          106694                       # number of writebacks
 system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1756378                       # number of replacements
-system.l2c.tags.tagsinuse                62298.874763                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4716146                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1814465                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.599194                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1759418                       # number of replacements
+system.l2c.tags.tagsinuse                62296.253449                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4473392                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1817492                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.461299                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   34280.883889                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    45.238820                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker    58.953050                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3333.891398                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6982.835280                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   308.005625                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   424.754545                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2990.314104                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    13873.998053                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.523085                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000690                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000900                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.050871                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.106550                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004700                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.006481                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.045629                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.211700                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.950605                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          228                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        57859                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          227                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          548                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3455                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5562                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        48240                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003479                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.882858                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 74820318                       # Number of tag accesses
-system.l2c.tags.data_accesses                74820318                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2753989                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2753989                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           13132                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           10939                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               24071                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          1512                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          1301                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              2813                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           319600                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           264468                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               584068                       # number of ReadExReq hits
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-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4584                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       512119                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       747634                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::cpu1.inst       486435                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       695595                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2461663                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          6283                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4584                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              512119                       # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.inst              486435                       # number of demand (read+write) hits
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-system.l2c.demand_hits::total                 3045731                       # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.inst             512119                       # number of overall hits
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-system.l2c.overall_hits::cpu1.inst             486435                       # number of overall hits
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-system.l2c.overall_hits::total                3045731                       # number of overall hits
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-system.l2c.UpgradeReq_misses::cpu1.data         54120                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            112817                       # number of UpgradeReq misses
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-system.l2c.SCUpgradeReq_misses::total           15209                       # number of SCUpgradeReq misses
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-system.l2c.ReadExReq_misses::total            1363359                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2385                       # number of ReadSharedReq misses
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-system.l2c.ReadSharedReq_misses::total         475211                       # number of ReadSharedReq misses
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-system.l2c.overall_misses::total              1838570                       # number of overall misses
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.831860                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.824156                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.195610                       # miss rate for ReadSharedReq accesses
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-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.388408                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.491665                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.074596                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::total          0.376424                       # miss rate for overall accesses
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+system.l2c.tags.occ_blocks::cpu0.dtb.walker    42.521667                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    58.768031                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3224.697109                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     7016.159468                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   270.222583                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   416.861208                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2985.929949                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    13907.449654                       # Average occupied blocks per requestor
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+system.l2c.tags.data_accesses                73042126                       # Number of data accesses
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+system.l2c.overall_misses::total              1841838                       # number of overall misses
+system.l2c.WritebackDirty_accesses::writebacks      2746880                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2746880                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        82740                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data        76160                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          158900                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         9313                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         8745                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         18058                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data      1131892                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       809577                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          1941469                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         8724                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6543                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       503773                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       912814                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         9041                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7061                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst       458216                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       863413                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      2769585                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         8724                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6543                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          503773                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         2044706                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         9041                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7061                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          458216                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         1672990                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4711054                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8724                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6543                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         503773                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        2044706                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         9041                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7061                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         458216                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        1672990                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4711054                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.822649                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.831565                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.826923                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.841834                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.854889                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.848156                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.720649                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.675605                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.701866                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.272352                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.303072                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.114466                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.198813                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.383586                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.487041                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.090752                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.216806                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.173018                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.272352                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.303072                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.114466                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.487687                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.383586                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.487041                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.090752                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.438823                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.390961                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.272352                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.303072                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.114466                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.487687                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.383586                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.487041                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.090752                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.438823                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.390961                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1476,51 +1477,51 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1471188                       # number of writebacks
-system.l2c.writebacks::total                  1471188                       # number of writebacks
+system.l2c.writebacks::writebacks             1470290                       # number of writebacks
+system.l2c.writebacks::total                  1470290                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               82131                       # Transaction distribution
-system.membus.trans_dist::ReadResp             566255                       # Transaction distribution
+system.membus.trans_dist::ReadResp             570231                       # Transaction distribution
 system.membus.trans_dist::WriteReq              38802                       # Transaction distribution
 system.membus.trans_dist::WriteResp             38802                       # Transaction distribution
-system.membus.trans_dist::Writeback           1577882                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           244930                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           328773                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         314660                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          150374                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1610566                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1341014                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        484124                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1576984                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           244820                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           347427                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         314914                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          168909                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1611622                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1340459                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        488100                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122570                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27558                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6497230                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      6647450                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       344319                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       344319                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6991769                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6542117                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      6692337                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       344320                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       344320                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                7036657                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155677                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55116                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    210588188                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    210799185                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    210749660                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    210960657                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7398848                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      7398848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               218198033                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               218359505                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4791150                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4814081                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4791150    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4814081    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4791150                       # Request fanout histogram
+system.membus.snoop_fanout::total             4814081                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1573,41 +1574,41 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     11435399                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      5875226                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1762842                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         121928                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       112531                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops         9397                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     11103531                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      5720804                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1657088                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         128474                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       115294                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        13180                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadReq              82133                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           3715978                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           3545235                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             38802                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            38802                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          2753989                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1064741                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          330496                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        317473                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         647969                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2216979                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2216979                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      3633845                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9232436                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7825750                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17058186                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    301171869                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    249940932                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              551112801                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1989284                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         13543939                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.291452                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.455956                       # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty      2746880                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1000532                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          352734                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        317656                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         670390                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2212632                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2212632                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      3463102                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9045879                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7635651                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              16681530                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    295373981                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    244078084                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              539452065                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1992317                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         13215112                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.283607                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.452956                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                9605923     70.92%     70.92% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3928619     29.01%     99.93% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                   9397      0.07%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                9480390     71.74%     71.74% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3721542     28.16%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  13180      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           13543939                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           13215112                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
index 4a667c177..938cba50a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -4,53 +4,53 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 625482                       # Simulator instruction rate (inst/s)
-host_op_rate                                   735044                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32470102586                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 669952                       # Number of bytes of host memory used
-host_seconds                                  1574.10                       # Real time elapsed on the host
+host_inst_rate                                1109940                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1304361                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            57619334274                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 720500                       # Number of bytes of host memory used
+host_seconds                                   887.05                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker       412352                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker       376704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5543028                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         110110088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5485940                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         110128008                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide        442112                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            116884284                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5543028                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5543028                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103060480                       # Number of bytes written to this memory
+system.physmem.bytes_read::total            116845116                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5485940                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5485940                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103078272                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103081060                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103098852                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker         6443                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker         5886                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             127017                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1720483                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             126125                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1720763                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide           6908                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1866737                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1610320                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1866125                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1610598                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1612893                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1613171                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker           8068                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker           7370                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               108450                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2154326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               107334                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2154677                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide             8650                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2286865                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108450                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108450                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2016399                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2286098                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          107334                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107334                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2016747                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2016802                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2016399                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2017150                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2016747                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker          8068                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker          7370                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108450                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2154729                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              107334                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2155079                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide            8650                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4303666                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4303248                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8921279                       # number of writebacks
-system.cpu.dcache.writebacks::total           8921279                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      8921277                       # number of writebacks
+system.cpu.dcache.writebacks::total           8921277                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements          14295641                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.984599                       # Cycle average of tags in use
@@ -411,23 +411,25 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks     14295641                       # number of writebacks
+system.cpu.icache.writebacks::total          14295641                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1722572                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65341.862554                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           46966735                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1785868                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            26.299108                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1723188                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65341.862570                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46967342                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1786484                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            26.290379                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle        395986000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.195568                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.733962                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6290.976194                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.566080                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 37239.479155                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   310.194068                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   443.716842                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6119.396908                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 21229.075596                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.568229                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004733                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006771                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.095993                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.323461                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.093375                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.323930                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997038                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023          278                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        63018                       # Occupied blocks per task id
@@ -439,33 +441,35 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4910
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54670                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004242                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961578                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        426185247                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       426185247                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses        426185861                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       426185861                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       506612                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       255620                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         762232                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      8921279                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      8921279                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      8921277                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      8921277                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     14294063                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     14294063                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data        11223                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total        11223                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1692559                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1692559                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14212229                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14212229                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7504111                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      7504111                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       694322                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       694322                       # number of InvalidateReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1692549                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1692549                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14213121                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     14213121                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      7503843                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      7503843                       # number of ReadSharedReq hits
+system.cpu.l2cache.InvalidateReq_hits::cpu.data       694318                       # number of InvalidateReq hits
+system.cpu.l2cache.InvalidateReq_hits::total       694318                       # number of InvalidateReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker       506612                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker       255620                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14212229                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      9196670                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        24171131                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst     14213121                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      9196392                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        24171745                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker       506612                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker       255620                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14212229                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      9196670                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       24171131                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst     14213121                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      9196392                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       24171745                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         6443                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         5886                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total        12329                       # number of ReadReq misses
@@ -473,29 +477,31 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data        39917
 system.cpu.l2cache.UpgradeReq_misses::total        39917                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       826558                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       826558                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83929                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        83929                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       344087                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       344087                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       551027                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       551027                       # number of InvalidateReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       826568                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       826568                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83037                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        83037                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       344355                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       344355                       # number of ReadSharedReq misses
+system.cpu.l2cache.InvalidateReq_misses::cpu.data       551031                       # number of InvalidateReq misses
+system.cpu.l2cache.InvalidateReq_misses::total       551031                       # number of InvalidateReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker         6443                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker         5886                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        83929                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1170645                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1266903                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        83037                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1170923                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1266289                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker         6443                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker         5886                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        83929                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1170645                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1266903                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        83037                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1170923                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1266289                       # number of overall misses
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       513055                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       261506                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       774561                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      8921279                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      8921279                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      8921277                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      8921277                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     14294063                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     14294063                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data        51140                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total        51140                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
@@ -525,24 +531,24 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780544
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780544                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328114                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.328114                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005871                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005871                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043843                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043843                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442468                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442468                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.328118                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.328118                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005808                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005808                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043877                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043877                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.442471                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.442471                       # miss rate for InvalidateReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.022508                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005871                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.112917                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.049803                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005808                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.112944                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.049779                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.012558                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.022508                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005871                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.112917                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.049803                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005808                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.112944                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.049779                       # miss rate for overall accesses
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -551,21 +557,22 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1503689                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1503689                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1503967                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1503967                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     52457192                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     26548378                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1747                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2719                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2719                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2724                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2724                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq        1227763                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp      23372119                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33606                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8921279                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     16984756                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8921277                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     14294063                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2690695                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq        51140                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp        51141                       # Transaction distribution
@@ -580,23 +587,23 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       758224                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1543944                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total          80348699                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    915126612                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1234659686                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1829946644                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1234659558                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      3032896                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6175776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2158994970                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1954373                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     55082670                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size::total         3073814874                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1954989                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     55083286                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.010814                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.103427                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           54487002     98.92%     98.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             595668      1.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           54487613     98.92%     98.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             595673      1.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       55082670                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total       55083286                       # Request fanout histogram
 system.iobus.trans_dist::ReadReq                40246                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40246                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
@@ -710,47 +717,47 @@ system.iocache.writebacks::writebacks          106631                       # nu
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
-system.membus.trans_dist::ReadResp             525878                       # Transaction distribution
+system.membus.trans_dist::ReadResp             525254                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::Writeback           1610320                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           225581                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40484                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1610598                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           224691                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            40486                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40485                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1377021                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1377021                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        449199                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           40487                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1377033                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1377033                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        448575                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5529643                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5658835                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5527811                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5657003                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       344374                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       344374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6003209                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6001377                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    212740640                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    212909690                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    212719264                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    212888314                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7391040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      7391040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               220300730                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               220279354                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3921686                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3920464                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3921686    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3920464    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3921686                       # Request fanout histogram
+system.membus.snoop_fanout::total             3920464                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index 538ad9900..bc095ccdb 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -1,170 +1,170 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.474700                       # Number of seconds simulated
-sim_ticks                                47474700369500                       # Number of ticks simulated
-final_tick                               47474700369500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.602568                       # Number of seconds simulated
+sim_ticks                                47602567962500                       # Number of ticks simulated
+final_tick                               47602567962500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 794386                       # Simulator instruction rate (inst/s)
-host_op_rate                                   934446                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            42775515400                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 715280                       # Number of bytes of host memory used
-host_seconds                                  1109.86                       # Real time elapsed on the host
-sim_insts                                   881655060                       # Number of instructions simulated
-sim_ops                                    1037101350                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 587112                       # Simulator instruction rate (inst/s)
+host_op_rate                                   690746                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            32025707663                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 784812                       # Number of bytes of host memory used
+host_seconds                                  1486.39                       # Real time elapsed on the host
+sim_insts                                   872675802                       # Number of instructions simulated
+sim_ops                                    1026715135                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       127360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       143744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3459124                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         40376840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     12078528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        91584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        86464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2488056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         17058000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     14991744                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        410816                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             91312260                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3459124                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2488056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5947180                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     77042688                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        97216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       105280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3176436                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         39189384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     13261312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        67968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        64704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2473528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         13920528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher      8902656                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        417088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             81676100                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3176436                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2473528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5649964                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69006208                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          77063272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1990                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2246                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             94456                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            630901                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       188727                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1431                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1351                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             38964                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            266544                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       234246                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6419                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1467275                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1203792                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          69026792                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1519                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1645                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             90039                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            612347                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       207208                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1062                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1011                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             38737                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            217521                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       139104                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6517                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1316710                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1078222                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1206366                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2683                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          3028                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               72862                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              850492                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       254420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1929                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1821                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               52408                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              359307                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       315784                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8653                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1923388                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          72862                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          52408                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             125271                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1622816                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                433                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1080796                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2042                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2212                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               66728                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              823262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       278584                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1359                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               51962                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              292432                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       187020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8762                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1715792                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          66728                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          51962                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             118690                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1449632                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                432                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1623249                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1622816                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2683                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         3028                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              72862                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             850925                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       254420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1929                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1821                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              52408                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             359307                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       315784                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8653                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3546637                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1467275                       # Number of read requests accepted
-system.physmem.writeReqs                      1206366                       # Number of write requests accepted
-system.physmem.readBursts                     1467275                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1206366                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 93873920                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     31680                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  77062336                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  91312260                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               77063272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      495                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         220616                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               87562                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               88840                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               82797                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               92927                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               90148                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               93986                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               87799                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               94269                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               90753                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              132105                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              81290                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              92144                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              81361                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              87555                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              92182                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              91062                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               71771                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               74672                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               72652                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               78055                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               74620                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               78875                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               73591                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               76891                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               77107                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               78277                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              71128                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              78119                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              70456                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              74533                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              76600                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              76752                       # Per bank write bursts
+system.physmem.bw_write::total                1450064                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1449632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2042                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2212                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              66728                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             823694                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       278584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              51962                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             292432                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       187020                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3165856                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1316710                       # Number of read requests accepted
+system.physmem.writeReqs                      1080796                       # Number of write requests accepted
+system.physmem.readBursts                     1316710                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1080796                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 84239104                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     30336                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  69025088                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  81676100                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               69026792                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      474                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         461546                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               74138                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               82827                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               74957                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               82122                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               83077                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               87558                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               81167                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               84127                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               76730                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              122410                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              70954                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              80684                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              75912                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              81292                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              78761                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              79520                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61777                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               69166                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               64147                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               68304                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               69323                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               73404                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               67894                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               70420                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65275                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               69986                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              62072                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              68038                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64002                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              68951                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              67347                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              68411                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          39                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47474697259000                       # Total gap between requests
+system.physmem.numWrRetry                          25                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47602564597000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1424050                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1273485                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1203792                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::19                       51                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1078222                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -188,162 +188,163 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::57                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      114                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::60                       89                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      107                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       940579                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      181.734800                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     113.091903                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     237.596263                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         569137     60.51%     60.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       185879     19.76%     80.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        61156      6.50%     86.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        31438      3.34%     90.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        21576      2.29%     92.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13250      1.41%     93.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9973      1.06%     94.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9805      1.04%     95.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        38365      4.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         940579                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         68336                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.464104                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      309.922160                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          68334    100.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::56                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       70                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       845861                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      181.192513                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     111.718720                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     240.356894                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         524023     61.95%     61.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       157589     18.63%     80.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52244      6.18%     86.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        27763      3.28%     90.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18582      2.20%     92.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11693      1.38%     93.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8942      1.06%     94.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         9176      1.08%     95.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        35849      4.24%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         845861                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60416                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.786182                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      329.918437                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          60413    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           68336                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         68336                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.620273                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.104093                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.841865                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           64690     94.66%     94.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            1540      2.25%     96.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             239      0.35%     97.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             282      0.41%     97.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              82      0.12%     97.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             291      0.43%     98.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             162      0.24%     98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              86      0.13%     98.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              81      0.12%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             117      0.17%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              30      0.04%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              46      0.07%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             391      0.57%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              42      0.06%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              42      0.06%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             142      0.21%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              21      0.03%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             7      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            20      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           68336                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    37142962355                       # Total ticks spent queuing
-system.physmem.totMemAccLat               64645087355                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   7333900000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25322.79                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           60416                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60416                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.851513                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.268088                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.277078                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           56734     93.91%     93.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1553      2.57%     96.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             255      0.42%     96.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             285      0.47%     97.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              70      0.12%     97.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             285      0.47%     97.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             159      0.26%     98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              94      0.16%     98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              78      0.13%     98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             106      0.18%     98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              41      0.07%     98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              61      0.10%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             428      0.71%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              38      0.06%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              49      0.08%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             117      0.19%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              11      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            24      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             5      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60416                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    28673044871                       # Total ticks spent queuing
+system.physmem.totMemAccLat               53352469871                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6581180000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       21784.12                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44072.79                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.98                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.62                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.62                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40534.12                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.45                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.72                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.45                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.94                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1168360                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    561939                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.65                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  46.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                     17756571.38                       # Average gap between requests
-system.physmem.pageHitRate                      64.78                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3585949920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1956619500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                5602958400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3895302960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3100816442880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1230768339570                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27405197149500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31751822762730                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.815694                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45589938065590                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1585284480000                       # Time in different power states
+system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.42                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1054044                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    494841                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.08                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  45.88                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19855034.61                       # Average gap between requests
+system.physmem.pageHitRate                      64.68                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3265088400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1781546250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5069789400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3527867520                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3109168015200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1219382745750                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27491903982750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31834099035270                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.747581                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45734675361714                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1589554200000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    299474968160                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    278338023286                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3524827320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1923268875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5837886600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3907258560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3100816442880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1224297828675                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27410873036250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31751180549160                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.802167                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45599398366763                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1585284480000                       # Time in different power states
+system.physmem_1.actEnergy                 3129537600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1707585000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5196804600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3460818960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3109168015200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1215349697925                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27495441752250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31833454211535                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.734035                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45740562014248                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1589554200000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    290016828237                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    272450963752                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -374,9 +375,9 @@ system.realview.nvmem.bw_total::total               4                       # To
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
+system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -407,66 +408,69 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   101051                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               101051                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         8300                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        78014                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       101044                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         101044    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       101044                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        86321                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22610.900013                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 19675.452020                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 23315.454382                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        84871     98.32%     98.32% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          161      0.19%     98.51% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1103      1.28%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           41      0.05%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           57      0.07%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           25      0.03%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           42      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           13      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        86321                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   1368339312                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean    -0.519630                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     2079369704    151.96%    151.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1     -711030392    -51.96%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   1368339312                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        78015     90.38%     90.38% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M         8300      9.62%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        86315                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       101051                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   111926                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               111926                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10169                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        86471                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore           18                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       111908                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean     0.232334                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev    77.721788                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047       111907    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       111908                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        96658                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23040.705374                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21274.900589                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 18509.319790                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        95612     98.92%     98.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          152      0.16%     99.08% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          763      0.79%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           18      0.02%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           39      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           23      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           37      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        96658                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    444719432                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean    -3.785405                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     2128162704    478.54%    478.54% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    -1683443272   -378.54%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    444719432                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        86471     89.48%     89.48% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        10169     10.52%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        96640                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       111926                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       101051                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        86315                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       111926                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        96640                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        86315                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       187366                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        96640                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       208566                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    83039604                       # DTB read hits
-system.cpu0.dtb.read_misses                     74585                       # DTB read misses
-system.cpu0.dtb.write_hits                   76137695                       # DTB write hits
-system.cpu0.dtb.write_misses                    26466                       # DTB write misses
+system.cpu0.dtb.read_hits                    87929647                       # DTB read hits
+system.cpu0.dtb.read_misses                     85158                       # DTB read misses
+system.cpu0.dtb.write_hits                   79744109                       # DTB write hits
+system.cpu0.dtb.write_misses                    26768                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              42668                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   37690                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              39890                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   37859                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4076                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  3884                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10173                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                83114189                       # DTB read accesses
-system.cpu0.dtb.write_accesses               76164161                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10087                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                88014805                       # DTB read accesses
+system.cpu0.dtb.write_accesses               79770877                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        159177299                       # DTB hits
-system.cpu0.dtb.misses                         101051                       # DTB misses
-system.cpu0.dtb.accesses                    159278350                       # DTB accesses
+system.cpu0.dtb.hits                        167673756                       # DTB hits
+system.cpu0.dtb.misses                         111926                       # DTB misses
+system.cpu0.dtb.accesses                    167785682                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -496,238 +500,237 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    61250                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                61250                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          499                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        55525                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        61250                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          61250    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        61250                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        56024                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26762.682065                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 22405.547992                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 30987.782128                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        54387     97.08%     97.08% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071           41      0.07%     97.15% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         1384      2.47%     99.62% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           41      0.07%     99.69% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           72      0.13%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           22      0.04%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           55      0.10%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287           10      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    61252                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                61252                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          842                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        54849                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        61252                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          61252    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        61252                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        55691                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26308.021045                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23499.981275                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 25689.449100                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        54619     98.08%     98.08% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071           42      0.08%     98.15% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          884      1.59%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           24      0.04%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           48      0.09%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           19      0.03%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           35      0.06%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::524288-589823            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        56024                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples   1978837204                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     1978837204    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total   1978837204                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        55525     99.11%     99.11% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          499      0.89%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        56024                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::655360-720895            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        55691                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples   1979242204                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     1979242204    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total   1979242204                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        54849     98.49%     98.49% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          842      1.51%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        55691                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        61250                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        61250                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        61252                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        61252                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        56024                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        56024                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       117274                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   441205116                       # ITB inst hits
-system.cpu0.itb.inst_misses                     61250                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        55691                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        55691                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       116943                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   467202921                       # ITB inst hits
+system.cpu0.itb.inst_misses                     61252                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              42668                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   26202                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              39890                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   27100                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               441266366                       # ITB inst accesses
-system.cpu0.itb.hits                        441205116                       # DTB hits
-system.cpu0.itb.misses                          61250                       # DTB misses
-system.cpu0.itb.accesses                    441266366                       # DTB accesses
-system.cpu0.numCycles                     94949400739                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               467264173                       # ITB inst accesses
+system.cpu0.itb.hits                        467202921                       # DTB hits
+system.cpu0.itb.misses                          61252                       # DTB misses
+system.cpu0.itb.accesses                    467264173                       # DTB accesses
+system.cpu0.numCycles                     95205135902                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5268                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  440958495                       # Number of instructions committed
-system.cpu0.committedOps                    519578987                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            478066113                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                531836                       # Number of float alu accesses
-system.cpu0.num_func_calls                   26928397                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     66358328                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   478066113                       # number of integer instructions
-system.cpu0.num_fp_insts                       531836                       # number of float instructions
-system.cpu0.num_int_register_reads          691558601                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         378884875                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              853461                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             460304                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           113354931                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          113143261                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    159167445                       # number of memory refs
-system.cpu0.num_load_insts                   83034076                       # Number of load instructions
-system.cpu0.num_store_insts                  76133369                       # Number of store instructions
-system.cpu0.num_idle_cycles              93735186324.296036                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1214214414.703974                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.012788                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.987212                       # Percentage of idle cycles
-system.cpu0.Branches                         98314010                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                359396375     69.13%     69.13% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1169846      0.23%     69.36% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    59621      0.01%     69.37% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                 21      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.37% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             75402      0.01%     69.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.38% # Class of executed instruction
-system.cpu0.op_class::MemRead                83034076     15.97%     85.36% # Class of executed instruction
-system.cpu0.op_class::MemWrite               76133369     14.64%    100.00% # Class of executed instruction
+system.cpu0.kern.inst.quiesce                    5123                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  466948479                       # Number of instructions committed
+system.cpu0.committedOps                    548389991                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            504092161                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                464416                       # Number of float alu accesses
+system.cpu0.num_func_calls                   27983491                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     70438282                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   504092161                       # number of integer instructions
+system.cpu0.num_fp_insts                       464416                       # number of float instructions
+system.cpu0.num_int_register_reads          728885661                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         399652952                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              772857                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             344936                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           120908457                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          120465396                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    167663327                       # number of memory refs
+system.cpu0.num_load_insts                   87924608                       # Number of load instructions
+system.cpu0.num_store_insts                  79738719                       # Number of store instructions
+system.cpu0.num_idle_cycles              93943889977.646729                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1261245924.353277                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.013248                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.986752                       # Percentage of idle cycles
+system.cpu0.Branches                        104008564                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                379698158     69.20%     69.20% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1212773      0.22%     69.42% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    66852      0.01%     69.43% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             46447      0.01%     69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.44% # Class of executed instruction
+system.cpu0.op_class::MemRead                87924608     16.02%     85.47% # Class of executed instruction
+system.cpu0.op_class::MemWrite               79738719     14.53%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 519868732                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          5565465                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          503.695844                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          153367622                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5565977                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.554484                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       6293402000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   503.695844                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.983781                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.983781                       # Average percentage of cache occupancy
+system.cpu0.op_class::total                 548687557                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          5767473                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          506.102777                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          161665939                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5767985                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.028148                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       6293818000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.102777                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988482                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988482                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          429                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          336                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        323920102                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       323920102                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     77284320                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       77284320                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     71935312                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      71935312                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       189585                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       189585                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       125588                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       125588                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1730584                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1730584                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1699772                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1699772                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    149219632                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       149219632                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    149409217                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      149409217                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3014242                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3014242                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1370827                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1370827                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       635540                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       635540                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       782263                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       782263                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       168057                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       168057                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       197269                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       197269                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4385069                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4385069                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5020609                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5020609                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52298763500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  52298763500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33070874000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  33070874000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  65701301500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  65701301500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2847254500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2847254500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4866222000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   4866222000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      3481500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      3481500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  85369637500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  85369637500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  85369637500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  85369637500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     80298562                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     80298562                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73306139                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     73306139                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       825125                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       825125                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       907851                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       907851                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1898641                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1898641                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1897041                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1897041                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    153604701                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    153604701                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    154429826                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    154429826                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037538                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.037538                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018700                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.018700                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.770235                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.770235                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.861665                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.861665                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088514                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088514                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.103988                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.103988                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028548                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.028548                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032511                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032511                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.552311                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17350.552311                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 24124.761184                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 24124.761184                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83988.762731                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83988.762731                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16942.195208                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16942.195208                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24667.950869                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24667.950869                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses        341141490                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       341141490                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     81909684                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       81909684                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     75364450                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      75364450                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       195602                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       195602                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       139312                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       139312                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1827663                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1827663                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1798607                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1798607                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    157274134                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       157274134                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    157469736                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      157469736                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3156555                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3156555                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1440320                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1440320                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       651795                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       651795                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       776738                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       776738                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       172749                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       172749                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       200464                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       200464                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      4596875                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4596875                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      5248670                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      5248670                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52100226500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  52100226500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36687284500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  36687284500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  65915448000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  65915448000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2830376000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2830376000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5792176500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5792176500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      4797000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      4797000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  88787511000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  88787511000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  88787511000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  88787511000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     85066239                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     85066239                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     76804770                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     76804770                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       847397                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       847397                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       916050                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       916050                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2000412                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2000412                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1999071                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1999071                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    161871009                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    161871009                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    162718406                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    162718406                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037107                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.037107                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018753                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018753                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.769173                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.769173                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.847921                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.847921                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086357                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086357                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.100279                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.100279                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028398                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.028398                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032256                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.032256                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16505.407477                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 16505.407477                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25471.620543                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25471.620543                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 84861.881355                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 84861.881355                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16384.326393                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16384.326393                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28893.848771                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28893.848771                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19468.254091                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19468.254091                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17003.841068                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17003.841068                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19314.754262                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19314.754262                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16916.192293                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16916.192293                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -736,157 +739,158 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      3771246                       # number of writebacks
-system.cpu0.dcache.writebacks::total          3771246                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        38597                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        38597                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21414                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21414                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        46766                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        46766                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        60011                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        60011                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        60011                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        60011                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2975645                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2975645                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1349413                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1349413                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       629920                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       629920                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       782263                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       782263                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       121291                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       121291                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       197269                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       197269                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4325058                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4325058                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4954978                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4954978                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17296                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        17296                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18619                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18619                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        35915                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        35915                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  46589316500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  46589316500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  30941514500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  30941514500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17872150500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17872150500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  64919038500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  64919038500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1795061500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1795061500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4668993000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4668993000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      3441500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      3441500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  77530831000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  77530831000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  95402981500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  95402981500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2879350000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2879350000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3091479000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3091479000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5970829000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5970829000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037057                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037057                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018408                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018408                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.763424                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.763424                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.861665                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.861665                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.063883                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.063883                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.103988                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.103988                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028157                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028157                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032086                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032086                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15656.879937                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15656.879937                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22929.610505                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22929.610505                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 28372.095663                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 28372.095663                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82988.762731                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82988.762731                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14799.626518                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14799.626518                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23668.153638                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23668.153638                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5767473                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5767473                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        27282                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        27282                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21266                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21266                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        44626                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        44626                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        48548                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        48548                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        48548                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        48548                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3129273                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3129273                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1419054                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1419054                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       650511                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       650511                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       776738                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       776738                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       128123                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       128123                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       200464                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       200464                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4548327                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4548327                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5198838                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5198838                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15619                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        15619                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16479                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16479                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32098                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        32098                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  47104061500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  47104061500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  34681725000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  34681725000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15920895000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15920895000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  65138711000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  65138711000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1795303000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1795303000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5591766500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5591766500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      4743000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      4743000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  81785786500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  81785786500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  97706681500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  97706681500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2690935500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2690935500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2795849000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2795849000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5486784500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5486784500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036786                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036786                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018476                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018476                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.767658                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.767658                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.847921                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.847921                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064048                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064048                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.100279                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.100279                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028098                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028098                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031950                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031950                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15052.717197                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15052.717197                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24440.031880                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24440.031880                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24474.443937                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24474.443937                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 83861.882643                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 83861.882643                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14012.339705                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14012.339705                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27894.118146                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27894.118146                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17925.963305                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17925.963305                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19253.966718                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19253.966718                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166474.907493                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166474.907493                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166038.938719                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166038.938719                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 166248.893220                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 166248.893220                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17981.509795                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17981.509795                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18793.946166                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18793.946166                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172286.029835                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172286.029835                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169661.326537                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169661.326537                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170938.516418                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170938.516418                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          5319178                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.824621                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          435885421                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5319690                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            81.938124                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      59948153000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.824621                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999657                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999657                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements          5175196                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.827248                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          462027213                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5175708                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            89.268408                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      59167640000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.827248                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999663                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999663                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          114                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        887729927                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       887729927                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    435885421                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      435885421                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    435885421                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       435885421                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    435885421                       # number of overall hits
-system.cpu0.icache.overall_hits::total      435885421                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5319695                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      5319695                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5319695                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       5319695                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5319695                       # number of overall misses
-system.cpu0.icache.overall_misses::total      5319695                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  59521353000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  59521353000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  59521353000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  59521353000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  59521353000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  59521353000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    441205116                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    441205116                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    441205116                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    441205116                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    441205116                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    441205116                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012057                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.012057                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012057                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.012057                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012057                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.012057                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11188.865715                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 11188.865715                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11188.865715                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 11188.865715                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11188.865715                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11188.865715                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        939581550                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       939581550                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    462027213                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      462027213                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    462027213                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       462027213                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    462027213                       # number of overall hits
+system.cpu0.icache.overall_hits::total      462027213                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      5175708                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      5175708                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      5175708                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       5175708                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      5175708                       # number of overall misses
+system.cpu0.icache.overall_misses::total      5175708                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  57336545500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  57336545500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  57336545500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  57336545500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  57336545500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  57336545500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    467202921                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    467202921                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    467202921                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    467202921                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    467202921                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    467202921                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011078                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011078                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011078                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011078                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011078                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011078                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11078.010100                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 11078.010100                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11078.010100                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 11078.010100                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11078.010100                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 11078.010100                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -895,252 +899,252 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5319695                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      5319695                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      5319695                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      5319695                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      5319695                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      5319695                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      5175196                       # number of writebacks
+system.cpu0.icache.writebacks::total          5175196                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5175708                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      5175708                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      5175708                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      5175708                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      5175708                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      5175708                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  56861505500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  56861505500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  56861505500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  56861505500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  56861505500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  56861505500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5953877000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5953877000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5953877000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   5953877000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.012057                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012057                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.012057                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.012057                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.012057                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.012057                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10688.865715                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10688.865715                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10688.865715                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10688.865715                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10688.865715                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10688.865715                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138060.915942                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138060.915942                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  54748691500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  54748691500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  54748691500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  54748691500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  54748691500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  54748691500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5954209000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   5954209000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011078                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011078                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011078                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.011078                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011078                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.011078                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10578.010100                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10578.010100                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10578.010100                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10578.010100                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10578.010100                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10578.010100                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7344223                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7344239                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7857654                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7857701                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           41                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       976449                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2329725                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16186.065873                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          18053337                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2345760                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            7.696157                       # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle     55834398000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks  6981.301122                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    64.056568                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    81.620115                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4075.206909                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data  4054.876060                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   929.005098                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.426105                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003910                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004982                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.248731                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.247490                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.056702                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.987919                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1345                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           47                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14643                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          280                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          619                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          442                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           20                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          806                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4474                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5446                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3835                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.082092                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.002869                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.893738                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       367456425                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      367456425                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       210868                       # number of ReadReq hits
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-system.cpu0.l2cache.ReadReq_hits::total        355653                       # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks      3771244                       # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total      3771244                       # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        99488                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total        99488                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        31647                       # number of SCUpgradeReq hits
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-system.cpu0.l2cache.InvalidateReq_hits::total       232290                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       210868                       # number of demand (read+write) hits
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-system.cpu0.l2cache.InvalidateReq_misses::total       548738                       # number of InvalidateReq misses
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-system.cpu0.l2cache.InvalidateReq_miss_latency::total  62221144000                       # number of InvalidateReq miss cycles
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-system.cpu0.l2cache.ReadCleanReq_accesses::total      5319695                       # number of ReadCleanReq accesses(hits+misses)
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-system.cpu0.l2cache.InvalidateReq_accesses::total       781028                       # number of InvalidateReq accesses(hits+misses)
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-system.cpu0.l2cache.ReadReq_miss_rate::total     0.051840                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.550133                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.550133                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.839565                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.839565                       # miss rate for SCUpgradeReq accesses
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+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          161                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
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+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          827                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4392                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6793                       # Occupied blocks per task id
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+system.cpu0.l2cache.WritebackDirty_hits::total      3807067                       # number of WritebackDirty hits
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+system.cpu0.l2cache.WritebackClean_hits::total      7134877                       # number of WritebackClean hits
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+system.cpu0.l2cache.InvalidateReq_hits::total       208597                       # number of InvalidateReq hits
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+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  18800277000                       # number of ReadCleanReq miss cycles
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+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  62566205500                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  62566205500                       # number of InvalidateReq miss cycles
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+system.cpu0.l2cache.demand_miss_latency::cpu0.data  56420942499                       # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    425309500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    392962000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  18800277000                       # number of overall miss cycles
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+system.cpu0.l2cache.WritebackDirty_accesses::total      3807067                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      7134877                       # number of WritebackClean accesses(hits+misses)
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+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998150                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
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 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.217140                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.217140                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.096437                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.096437                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.255746                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.255746                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.702584                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.702584                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.046963                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.058854                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.096437                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.246670                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.164124                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.046963                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.058854                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.096437                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.246670                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.164124                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47647.820229                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54495.747736                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 50836.358961                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31401.785274                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31401.785274                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23891.217318                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23891.217318                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 281708.166667                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 281708.166667                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67802.108755                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67802.108755                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39423.617392                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39423.617392                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44732.004029                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44732.004029                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 113389.530158                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 113389.530158                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47647.820229                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54495.747736                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39423.617392                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 49506.383466                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 46538.781860                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47647.820229                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54495.747736                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39423.617392                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 49506.383466                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 46538.781860                       # average overall miss latency
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+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.093220                       # miss rate for ReadCleanReq accesses
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+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.730710                       # miss rate for InvalidateReq accesses
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+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14378.128193                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10306.919827                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10306.919827                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 423772.727273                       # average SCUpgradeFailReq miss latency
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+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63704.610717                       # average ReadExReq miss latency
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+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38965.919831                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38965.919831                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41875.806300                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41875.806300                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 110536.702637                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 110536.702637                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42247.889143                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47904.669024                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38965.919831                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46617.628224                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 44440.458504                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42247.889143                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47904.669024                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38965.919831                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46617.628224                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 44440.458504                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1149,222 +1153,219 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1299353                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1299353                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         4520                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         4520                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          530                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          530                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5050                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         5050                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5050                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         5050                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10391                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         9054                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        19445                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks        93813                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.CleanEvict_mshr_misses::total        93813                       # number of CleanEvict MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       630880                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       630880                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       121662                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       121662                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       165610                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       165610                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           12                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           12                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       244205                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       244205                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       513016                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       513016                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       952600                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       952600                       # number of ReadSharedReq MSHR misses
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-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       548738                       # number of InvalidateReq MSHR misses
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-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1196805                       # number of demand (read+write) MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       513016                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1196805                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total      2360146                       # number of overall MSHR misses
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        17296                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        60421                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18619                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18619                       # number of WriteReq MSHR uncacheable
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 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        35915                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        79040                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    432762500                       # number of ReadReq MSHR miss cycles
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-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    871843000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  35559655965                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  35559655965                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4486256000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4486256000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3173949000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3173949000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      3140498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3140498                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  14883734000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  14883734000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  17146850500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  17146850500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  36873595000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  36873595000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  58928716000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  58928716000                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    432762500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    439080500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  17146850500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  51757329000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  69776022500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    432762500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    439080500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  17146850500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  51757329000                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total 105335678465                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5630439500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2740982000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8371421500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2951836500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2951836500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   5630439500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5692818500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11323258000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.046963                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.058854                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.051840                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        32098                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        75223                       # number of overall MSHR uncacheable misses
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+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    708651500                       # number of ReadReq MSHR miss cycles
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+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  38668799279                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7913903000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7913903000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   4087252500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   4087252500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4337500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4337500                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  15905397000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  15905397000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  33944380000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  33944380000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  59170079500                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  59170079500                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    364907500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  15905397000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.demand_mshr_miss_latency::total  65159065499                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  15905397000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  48545016999                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total 103827864778                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2565627500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8196399000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2671857000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2671857000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5237484500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10868256000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.036636                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.049402                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.041444                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.550133                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.550133                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.839565                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.839565                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998150                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998150                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.213194                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.213194                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.096437                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096437                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.255604                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.255604                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.702584                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.702584                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.046963                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.058854                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.096437                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.245634                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.163646                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.046963                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.058854                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.096437                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.245634                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.216200                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.216200                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.093220                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.093220                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.242291                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242291                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.730710                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.730710                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.036636                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.049402                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.093220                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.236196                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.159125                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.036636                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.049402                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.093220                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.236196                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.223348                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44836.358961                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56365.166062                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 36874.751360                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36874.751360                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19165.201377                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19165.201377                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 261708.166667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261708.166667                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60947.703773                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60947.703773                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33423.617392                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33423.617392                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38708.371824                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38708.371824                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107389.530158                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107389.530158                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33423.617392                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43246.250642                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40350.080612                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33423.617392                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43246.250642                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44631.000991                       # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158474.907493                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138551.521822                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158538.938719                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 158538.938719                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 158508.102464                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143259.843117                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226475                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38787.712096                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53581.196364                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32088.420617                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32088.420617                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.078971                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20390.078971                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 394318.181818                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 394318.181818                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56701.943312                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56701.943312                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32965.919831                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32965.919831                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35849.796694                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35849.796694                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 104536.713237                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 104536.713237                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32965.919831                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40308.131038                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38214.264224                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32965.919831                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40308.131038                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42784.139329                       # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164263.237083                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139527.424077                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162137.083561                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162137.083561                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 163171.677363                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144480.491339                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     22509328                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11536373                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          848                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       485130                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       485124                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        537841                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      9675681                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        18620                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        18619                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback      5107009                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      8757288                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       798537                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       405076                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       363715                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       481157                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           40                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           68                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1220841                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1155337                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5319695                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4658319                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       788798                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       781028                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16044388                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17944373                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       336960                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       515556                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         34841277                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    340632980                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    559762054                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1230712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1770072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         903395818                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    5410368                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     27976627                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.025738                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.158355                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests     22685684                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11636633                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          725                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      1868386                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1868205                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          181                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        566458                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      9760546                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        16479                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        16479                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5331858                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      7134877                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2347214                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       886122                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       438453                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       361903                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       524601                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           85                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          128                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1264261                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1203854                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5175708                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4797612                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       779730                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       774618                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     15612584                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18673898                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       348811                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       599734                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         35235027                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    662612564                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    703409885                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1328368                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2198296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1369549113                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    6346450                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     18158816                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.116500                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.320855                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          27256564     97.43%     97.43% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            720057      2.57%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2                 6      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          16043491     88.35%     88.35% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2115144     11.65%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               181      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      27976627                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   15196832497                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      18158816                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   22462112497                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    183439903                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    223807892                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   8022667500                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   7806687000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7935130422                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8283648998                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    183121000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    182765499                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    294297000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    324947000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1395,69 +1396,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   111674                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               111674                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        10360                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        85053                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore           21                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       111653                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.241821                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    61.696123                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047       111651    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::6144-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::18432-20479            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       111653                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        95434                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 21055.163778                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 19260.807562                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 16557.880011                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        94629     99.16%     99.16% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          150      0.16%     99.31% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          551      0.58%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           22      0.02%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           39      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215            7      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           21      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           13      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                    92112                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                92112                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         7185                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        70441                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        92107                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.086856                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    26.359895                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511        92106    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        92107                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        77631                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 22794.154397                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21108.718713                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 17037.529740                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        76846     98.99%     98.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          174      0.22%     99.21% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          527      0.68%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           17      0.02%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           28      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           18      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        95434                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  10744163364                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     1.061708                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     -663005280     -6.17%     -6.17% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    11407168644    106.17%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  10744163364                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        85053     89.14%     89.14% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        10360     10.86%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        95413                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       111674                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total        77631                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -5456316576                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.616394                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.486264                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -2093077220     38.36%     38.36% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -3363239356     61.64%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -5456316576                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        70442     90.74%     90.74% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         7185      9.26%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        77627                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        92112                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       111674                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        95413                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        92112                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        77627                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        95413                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       207087                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        77627                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       169739                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    82869257                       # DTB read hits
-system.cpu1.dtb.read_misses                     83659                       # DTB read misses
-system.cpu1.dtb.write_hits                   74681159                       # DTB write hits
-system.cpu1.dtb.write_misses                    28015                       # DTB write misses
+system.cpu1.dtb.read_hits                    76812549                       # DTB read hits
+system.cpu1.dtb.read_misses                     67403                       # DTB read misses
+system.cpu1.dtb.write_hits                   69811450                       # DTB write hits
+system.cpu1.dtb.write_misses                    24709                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              42668                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   37721                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              39890                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   34729                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4459                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4304                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    10437                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                82952916                       # DTB read accesses
-system.cpu1.dtb.write_accesses               74709174                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     9295                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                76879952                       # DTB read accesses
+system.cpu1.dtb.write_accesses               69836159                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        157550416                       # DTB hits
-system.cpu1.dtb.misses                         111674                       # DTB misses
-system.cpu1.dtb.accesses                    157662090                       # DTB accesses
+system.cpu1.dtb.hits                        146623999                       # DTB hits
+system.cpu1.dtb.misses                          92112                       # DTB misses
+system.cpu1.dtb.accesses                    146716111                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1487,235 +1488,236 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    54727                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                54727                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          669                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        48424                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        54727                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          54727    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        54727                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        49093                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 23909.080724                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 21093.336913                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 23672.932713                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        48315     98.42%     98.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071           33      0.07%     98.48% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          627      1.28%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           24      0.05%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           39      0.08%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           15      0.03%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           29      0.06%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        49093                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  -1309982220                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    -1309982220    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  -1309982220                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        48424     98.64%     98.64% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          669      1.36%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        49093                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                    54749                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                54749                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          360                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        49211                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        54749                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          54749    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        54749                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        49571                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 25509.592302                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23251.815503                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 21686.807401                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        48865     98.58%     98.58% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071           34      0.07%     98.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          581      1.17%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           14      0.03%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           29      0.06%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           16      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           25      0.05%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        49571                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  -2103779220                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -2103779220    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -2103779220                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        49211     99.27%     99.27% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          360      0.73%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        49571                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        54727                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        54727                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        54749                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        54749                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        49093                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        49093                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       103820                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   441006552                       # ITB inst hits
-system.cpu1.itb.inst_misses                     54727                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        49571                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        49571                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       104320                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   406021553                       # ITB inst hits
+system.cpu1.itb.inst_misses                     54749                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              42668                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1040                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   26047                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              39890                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   24319                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               441061279                       # ITB inst accesses
-system.cpu1.itb.hits                        441006552                       # DTB hits
-system.cpu1.itb.misses                          54727                       # DTB misses
-system.cpu1.itb.accesses                    441061279                       # DTB accesses
-system.cpu1.numCycles                     94949400719                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               406076302                       # ITB inst accesses
+system.cpu1.itb.hits                        406021553                       # DTB hits
+system.cpu1.itb.misses                          54749                       # DTB misses
+system.cpu1.itb.accesses                    406076302                       # DTB accesses
+system.cpu1.numCycles                     95205135925                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13508                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  440696565                       # Number of instructions committed
-system.cpu1.committedOps                    517522363                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            474820793                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                365483                       # Number of float alu accesses
-system.cpu1.num_func_calls                   25816030                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     67531060                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   474820793                       # number of integer instructions
-system.cpu1.num_fp_insts                       365483                       # number of float instructions
-system.cpu1.num_int_register_reads          694878928                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         377300064                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              605102                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             276864                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           116712375                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          116303175                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    157542729                       # number of memory refs
-system.cpu1.num_load_insts                   82867724                       # Number of load instructions
-system.cpu1.num_store_insts                  74675005                       # Number of store instructions
-system.cpu1.num_idle_cycles              93871458813.181076                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1077941905.818921                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.011353                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.988647                       # Percentage of idle cycles
-system.cpu1.Branches                         98303933                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                359137164     69.35%     69.35% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1056908      0.20%     69.56% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    59454      0.01%     69.57% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.57% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             36204      0.01%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.58% # Class of executed instruction
-system.cpu1.op_class::MemRead                82867724     16.00%     85.58% # Class of executed instruction
-system.cpu1.op_class::MemWrite               74675005     14.42%    100.00% # Class of executed instruction
+system.cpu1.kern.inst.quiesce                   14029                       # number of quiesce instructions executed
+system.cpu1.committedInsts                  405727323                       # Number of instructions committed
+system.cpu1.committedOps                    478325144                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            439907771                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                446670                       # Number of float alu accesses
+system.cpu1.num_func_calls                   24605699                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     61596178                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   439907771                       # number of integer instructions
+system.cpu1.num_fp_insts                       446670                       # number of float instructions
+system.cpu1.num_int_register_reads          637924838                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         348926241                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              708486                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             403472                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           104772444                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          104573998                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    146614371                       # number of memory refs
+system.cpu1.num_load_insts                   76808885                       # Number of load instructions
+system.cpu1.num_store_insts                  69805486                       # Number of store instructions
+system.cpu1.num_idle_cycles              94195407146.248016                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1009728778.751979                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.010606                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.989394                       # Percentage of idle cycles
+system.cpu1.Branches                         90553045                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                330876771     69.13%     69.13% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1002715      0.21%     69.34% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    57816      0.01%     69.35% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.35% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             67767      0.01%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.37% # Class of executed instruction
+system.cpu1.op_class::MemRead                76808885     16.05%     85.42% # Class of executed instruction
+system.cpu1.op_class::MemWrite               69805486     14.58%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 517832459                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements          5147651                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          420.489425                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          152204564                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5148159                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.564853                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     8409197794000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   420.489425                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.821268                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.821268                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          443                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        320234661                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       320234661                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     77182580                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       77182580                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     70763723                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      70763723                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       181716                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       181716                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       197136                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       197136                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1768276                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1768276                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1725683                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1725683                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    147946303                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       147946303                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    148128019                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      148128019                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      2911211                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      2911211                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1304261                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1304261                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       646630                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       646630                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       461157                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       461157                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       158092                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       158092                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       198973                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       198973                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      4215472                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       4215472                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      4862102                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      4862102                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  46228111000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  46228111000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  27445585000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  27445585000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  22477695000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  22477695000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2400515000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2400515000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4867748500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   4867748500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2101500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2101500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  73673696000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  73673696000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  73673696000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  73673696000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     80093791                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     80093791                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     72067984                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     72067984                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       828346                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       828346                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       658293                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       658293                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1926368                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1926368                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1924656                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1924656                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    152161775                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    152161775                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    152990121                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    152990121                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036348                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.036348                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018098                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018098                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.780628                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.780628                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.700535                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.700535                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.082067                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.082067                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103381                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103381                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027704                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.027704                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031780                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.031780                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15879.340591                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15879.340591                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21043.015930                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21043.015930                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 48741.957728                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 48741.957728                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15184.291425                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15184.291425                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24464.367025                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24464.367025                       # average StoreCondReq miss latency
+system.cpu1.op_class::total                 478619483                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements          4731492                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          440.215275                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          141682703                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          4732003                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.941381                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     8408412782000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   440.215275                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.859795                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.859795                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          405                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        297963795                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       297963795                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     71617652                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       71617652                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     66171444                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      66171444                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       174206                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       174206                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       185116                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       185116                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1590024                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1590024                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1548743                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1548743                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    137789096                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       137789096                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    137963302                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      137963302                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      2694357                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      2694357                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1213090                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1213090                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       558664                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       558664                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       466794                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       466794                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       154053                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       154053                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       194127                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       194127                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      3907447                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       3907447                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      4466111                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      4466111                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  40157954500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  40157954500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  28157091500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  28157091500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20750751000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  20750751000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2380134500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2380134500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5345117000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5345117000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      6929500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      6929500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  68315046000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  68315046000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  68315046000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  68315046000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     74312009                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     74312009                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     67384534                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     67384534                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       732870                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       732870                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       651910                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       651910                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1744077                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1744077                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1742870                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1742870                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    141696543                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    141696543                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    142429413                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    142429413                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036257                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036257                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018002                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.018002                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.762296                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.762296                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.716041                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.716041                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.088329                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.088329                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.111384                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.111384                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027576                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.027576                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031357                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.031357                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14904.466817                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14904.466817                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23211.049057                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 23211.049057                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 44453.765473                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 44453.765473                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15450.101588                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15450.101588                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27534.124568                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27534.124568                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17476.974346                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17476.974346                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15152.643034                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15152.643034                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17483.294335                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17483.294335                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.316191                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15296.316191                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1724,158 +1726,157 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      3396408                       # number of writebacks
-system.cpu1.dcache.writebacks::total          3396408                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16912                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        16912                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          462                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total          462                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        41725                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        41725                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        17374                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        17374                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        17374                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        17374                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2894299                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2894299                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1303799                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1303799                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       646630                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       646630                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       461157                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       461157                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116367                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116367                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       198973                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       198973                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4198098                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4198098                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4844728                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4844728                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        20770                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        20770                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        19330                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        19330                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        40100                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        40100                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41851387000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41851387000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26109084500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26109084500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14515592000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14515592000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  22016538000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  22016538000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1587242500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1587242500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4668803500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4668803500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2073500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2073500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  67960471500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  67960471500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  82476063500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  82476063500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3614060000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3614060000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3361466500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3361466500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   6975526500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   6975526500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036136                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036136                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018091                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018091                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.780628                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.780628                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.700535                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.700535                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060407                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.060407                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103381                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103381                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027590                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027590                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031667                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031667                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14459.939004                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14459.939004                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20025.390800                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20025.390800                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22448.064581                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22448.064581                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 47741.957728                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 47741.957728                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13639.970954                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13639.970954                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23464.507747                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23464.507747                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      4731492                       # number of writebacks
+system.cpu1.dcache.writebacks::total          4731492                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        13909                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        13909                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          323                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total          323                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44168                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44168                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        14232                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        14232                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        14232                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        14232                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2680448                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2680448                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1212767                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1212767                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       558664                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       558664                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       466794                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       466794                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       109885                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       109885                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       194127                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       194127                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      3893215                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      3893215                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4451879                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4451879                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        23611                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        23611                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        22620                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        22620                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        46231                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        46231                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  36382655000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  36382655000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26928760500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26928760500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12609688500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12609688500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  20283957000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  20283957000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1540230500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1540230500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5151064000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5151064000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      6855500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      6855500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  63311415500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  63311415500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  75921104000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  75921104000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4287453000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4287453000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   4160988000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   4160988000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   8448441000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   8448441000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036070                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036070                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017998                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017998                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.762296                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.762296                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.716041                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.716041                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063005                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.063005                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.111384                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.111384                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027476                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027476                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031257                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031257                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13573.348560                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13573.348560                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22204.397465                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22204.397465                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22571.149206                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22571.149206                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 43453.765473                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 43453.765473                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14016.749329                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14016.749329                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26534.505762                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26534.505762                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16188.395673                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16188.395673                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17023.879050                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17023.879050                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174003.851709                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174003.851709                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173898.939472                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173898.939472                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173953.279302                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173953.279302                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16261.987971                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16261.987971                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17053.721361                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17053.721361                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181587.099233                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181587.099233                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183951.724138                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183951.724138                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182744.067833                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182744.067833                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          4679241                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          495.918258                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          436326798                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          4679753                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            93.237143                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     8409166313000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   495.918258                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968590                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.968590                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements          4831573                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          495.969883                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          401189463                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          4832085                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            83.026160                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     8408381586000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   495.969883                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968691                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.968691                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           48                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          359                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          278                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        886692857                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       886692857                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    436326798                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      436326798                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    436326798                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       436326798                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    436326798                       # number of overall hits
-system.cpu1.icache.overall_hits::total      436326798                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      4679754                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      4679754                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      4679754                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       4679754                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      4679754                       # number of overall misses
-system.cpu1.icache.overall_misses::total      4679754                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  52951180000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  52951180000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  52951180000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  52951180000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  52951180000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  52951180000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    441006552                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    441006552                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    441006552                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    441006552                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    441006552                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    441006552                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.010612                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.010612                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.010612                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.010612                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.010612                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.010612                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11314.949461                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 11314.949461                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11314.949461                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 11314.949461                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11314.949461                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 11314.949461                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        816875196                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       816875196                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    401189463                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      401189463                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    401189463                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       401189463                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    401189463                       # number of overall hits
+system.cpu1.icache.overall_hits::total      401189463                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      4832090                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      4832090                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      4832090                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       4832090                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      4832090                       # number of overall misses
+system.cpu1.icache.overall_misses::total      4832090                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  52408341000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  52408341000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  52408341000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  52408341000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  52408341000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  52408341000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    406021553                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    406021553                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    406021553                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    406021553                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    406021553                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    406021553                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011901                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.011901                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011901                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.011901                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011901                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.011901                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10845.895047                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10845.895047                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10845.895047                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10845.895047                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10845.895047                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10845.895047                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1884,255 +1885,252 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4679754                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      4679754                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      4679754                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      4679754                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      4679754                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      4679754                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      4831573                       # number of writebacks
+system.cpu1.icache.writebacks::total          4831573                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4832090                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      4832090                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      4832090                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      4832090                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      4832090                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      4832090                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  50611303500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  50611303500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  50611303500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  50611303500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  50611303500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  50611303500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14521500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14521500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14521500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total     14521500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.010612                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.010612                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.010612                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.010612                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.010612                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.010612                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10814.949568                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10814.949568                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10814.949568                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10814.949568                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10814.949568                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10814.949568                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132013.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132013.636364                       # average overall mshr uncacheable latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  49992296000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  49992296000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  49992296000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  49992296000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  49992296000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  49992296000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14799500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14799500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14799500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total     14799500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011901                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011901                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011901                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.011901                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011901                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.011901                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10345.895047                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10345.895047                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10345.895047                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10345.895047                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10345.895047                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10345.895047                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7337880                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7337888                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6380299                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6380331                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       899040                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2034185                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13437.783654                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          16644740                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2049737                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            8.120427                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9820320151000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks  6510.894270                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    71.649917                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    96.755911                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  2809.884427                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3040.183540                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   908.415590                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.397393                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004373                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.005906                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.171502                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.185558                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.055445                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.820177                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1547                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           77                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13928                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          214                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          697                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          636                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           36                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2599                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5864                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5395                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.094421                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.004700                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.850098                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       332457854                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      332457854                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       236423                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       125548                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        361971                       # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks      3396406                       # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total      3396406                       # number of Writeback hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        63344                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total        63344                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        31004                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total        31004                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       898756                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       898756                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4166985                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4166985                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2749875                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2749875                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       193932                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       193932                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       236423                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       125548                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4166985                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3648631                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8177587                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       236423                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       125548                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4166985                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3648631                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8177587                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9552                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7233                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        16785                       # number of ReadReq misses
-system.cpu1.l2cache.Writeback_misses::writebacks            1                       # number of Writeback misses
-system.cpu1.l2cache.Writeback_misses::total            1                       # number of Writeback misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       123356                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       123356                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       167961                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       167961                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            8                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       219942                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       219942                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       512769                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       512769                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       907421                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       907421                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       265828                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       265828                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9552                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7233                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       512769                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1127363                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1656917                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9552                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7233                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       512769                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1127363                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1656917                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    404155000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    336372500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    740527500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3749073000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   3749073000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   4008183000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   4008183000                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2030999                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2030999                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12972852500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  12972852500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  18777464000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  18777464000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  34592386500                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  34592386500                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  20042243500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  20042243500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    404155000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    336372500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  18777464000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  47565239000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  67083230500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    404155000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    336372500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  18777464000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  47565239000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  67083230500                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       245975                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       132781                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       378756                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks      3396407                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total      3396407                       # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       186700                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       186700                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       198965                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       198965                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1118698                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1118698                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4679754                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      4679754                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3657296                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3657296                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       459760                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       459760                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       245975                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       132781                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      4679754                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4775994                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      9834504                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       245975                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       132781                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      4679754                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4775994                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      9834504                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.038833                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.054473                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.044316                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_miss_rate::writebacks     0.000000                       # miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_miss_rate::total     0.000000                       # miss rate for Writeback accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.660718                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.660718                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.844174                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.844174                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       802101                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         1778912                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13269.685648                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          14051315                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         1794926                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.828353                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    10084696105000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12213.003078                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    33.894206                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    34.650770                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   988.137594                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.745423                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002069                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.002115                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.060311                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.809917                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1110                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           86                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14818                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          249                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          669                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          184                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           72                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          972                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4464                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8114                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1200                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.067749                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005249                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.904419                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       324313053                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      324313053                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       211999                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       140481                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        352480                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      2988895                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      2988895                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      6573071                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      6573071                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          239                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total          239                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       778234                       # number of ReadExReq hits
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+system.cpu1.l2cache.ReadCleanReq_hits::total      4410501                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2517428                       # number of ReadSharedReq hits
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+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       200602                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       200602                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       211999                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       140481                       # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       211999                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       140481                       # number of overall hits
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+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9285                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7506                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        16791                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       201343                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       201343                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       194101                       # number of SCUpgradeReq misses
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+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           26                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total           26                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       235513                       # number of ReadExReq misses
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+system.cpu1.l2cache.ReadCleanReq_misses::total       421589                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       831569                       # number of ReadSharedReq misses
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+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       263822                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       263822                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9285                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7506                       # number of demand (read+write) misses
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+system.cpu1.l2cache.demand_misses::total      1505462                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9285                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7506                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       421589                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1067082                       # number of overall misses
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+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    349092500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    301051000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    650143500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3162483500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   3162483500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1860693500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1860693500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      6744500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      6744500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12440298999                       # number of ReadExReq miss cycles
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+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  16234081000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  16234081000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  29105216000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  29105216000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  18219271500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  18219271500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    349092500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    301051000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16234081000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  41545514999                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    349092500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    301051000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16234081000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  41545514999                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  58429739499                       # number of overall miss cycles
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+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       147987                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       369271                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      2988895                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      2988895                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      6573071                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      6573071                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       201582                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       201582                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       194101                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       194101                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           26                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           26                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1013747                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1013747                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4832090                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      4832090                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3348997                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3348997                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       464424                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       464424                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       221284                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       147987                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      4832090                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4362744                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total      9564105                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       221284                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       147987                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      4832090                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4362744                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total      9564105                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.041960                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050721                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.045471                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998814                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998814                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.196605                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.196605                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.109572                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.109572                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.248113                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.248113                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.578189                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.578189                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.038833                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.054473                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.109572                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.236048                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.168480                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.038833                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.054473                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.109572                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.236048                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.168480                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42311.034338                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46505.253698                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44118.409294                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30392.303577                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30392.303577                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23863.771947                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23863.771947                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 253874.875000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 253874.875000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58983.061443                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58983.061443                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36619.733252                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36619.733252                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38121.650810                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38121.650810                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 75395.532073                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 75395.532073                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42311.034338                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46505.253698                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36619.733252                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42191.591351                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 40486.777853                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42311.034338                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46505.253698                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36619.733252                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42191.591351                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 40486.777853                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.232319                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.232319                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.087248                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.087248                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.248304                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.248304                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.568063                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.568063                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.041960                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050721                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.087248                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.244590                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.157408                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.041960                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050721                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.087248                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.244590                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.157408                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37597.469036                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40108.046896                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 38719.760586                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15706.945362                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15706.945362                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9586.212848                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9586.212848                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259403.846154                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259403.846154                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52822.132957                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52822.132957                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38506.889411                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38506.889411                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35000.361966                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35000.361966                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69058.954522                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69058.954522                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37597.469036                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40108.046896                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38506.889411                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38933.760479                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 38811.832845                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37597.469036                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40108.046896                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38506.889411                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38933.760479                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 38811.832845                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2141,234 +2139,227 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1015409                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1015409                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         7242                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         7242                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          595                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          595                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.writebacks::writebacks       983057                       # number of writebacks
+system.cpu1.l2cache.writebacks::total          983057                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3912                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         3912                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          475                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          475                       # number of ReadSharedReq MSHR hits
 system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            1                       # number of InvalidateReq MSHR hits
 system.cpu1.l2cache.InvalidateReq_mshr_hits::total            1                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7837                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         7837                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7837                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         7837                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9552                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7233                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        16785                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::writebacks            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.Writeback_mshr_misses::total            1                       # number of Writeback MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks        96130                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.CleanEvict_mshr_misses::total        96130                       # number of CleanEvict MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       687356                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       687356                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       123356                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       123356                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       167961                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       167961                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            8                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       212700                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       212700                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       512769                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       512769                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       906826                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       906826                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       265827                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       265827                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker         9552                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7233                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       512769                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1119526                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1649080                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker         9552                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7233                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       512769                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1119526                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       687356                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2336436                       # number of overall MSHR misses
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4387                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         4387                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4387                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         4387                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9285                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7506                       # number of ReadReq MSHR misses
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+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       603476                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       603476                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       201343                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       201343                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       194101                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       194101                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           26                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           26                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       231601                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       231601                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       421589                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       421589                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       831094                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       831094                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       263821                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       263821                       # number of InvalidateReq MSHR misses
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+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1062695                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2104551                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        20770                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        20880                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        19330                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        19330                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        23611                       # number of ReadReq MSHR uncacheable
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+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        22620                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        22620                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        40100                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        40210                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    346843000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    292974500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    639817500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  44220457933                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  44220457933                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4206113500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4206113500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3161211000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3161211000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1862999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1862999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  10724509000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  10724509000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  15700856000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  15700856000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  29099850500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  29099850500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  18447195500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  18447195500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    346843000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    292974500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  15700856000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  39824359500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  56165033000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    346843000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    292974500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  15700856000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  39824359500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  44220457933                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total 100385490933                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13696500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3447900000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3461596500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3216491500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3216491500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13696500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   6664391500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   6678088000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.038833                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.054473                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.044316                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.Writeback_mshr_miss_rate::total     0.000000                       # mshr miss rate for Writeback accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        46231                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        46341                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    293382500                       # number of ReadReq MSHR miss cycles
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+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    549397500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27540952434                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  27540952434                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6429356000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6429356000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3693933999                       # number of SCUpgradeReq MSHR miss cycles
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+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      6300500                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13704547000                       # number of ReadCleanReq MSHR miss cycles
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+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  24076200000                       # number of ReadSharedReq MSHR miss cycles
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+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16636263000                       # number of InvalidateReq MSHR miss cycles
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+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13974500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   8088822000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   8102796500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.041960                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050721                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.045471                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.660718                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.660718                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.844174                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.844174                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.998814                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.998814                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.190132                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.190132                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.109572                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.109572                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.247950                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.247950                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.578186                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.578186                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.038833                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.054473                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.109572                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234407                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.167683                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.038833                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.054473                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.109572                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234407                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.228460                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.228460                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.087248                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.248162                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248162                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.568061                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.568061                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.041960                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050721                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.243584                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.156949                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.041960                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050721                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.243584                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.237575                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38118.409294                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64334.141163                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 34097.356432                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34097.356432                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18821.101327                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18821.101327                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 232874.875000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 232874.875000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50420.822755                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50420.822755                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30619.744953                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30619.744953                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32089.784038                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32089.784038                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69395.492181                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69395.492181                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30619.744953                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35572.518637                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34058.404080                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30619.744953                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35572.518637                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42965.221788                       # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166003.851709                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165785.272989                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166398.939472                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166398.939472                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 166194.301746                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 166080.278538                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.220047                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.760586                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45637.195902                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31932.354241                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31932.354241                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19030.989016                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19030.989016                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242326.923077                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242326.923077                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.471993                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.471993                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32506.889411                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32506.889411                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28969.286266                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28969.286266                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63058.903575                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63058.903575                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32506.889411                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32612.368553                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32583.945172                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32506.889411                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32612.368553                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36326.940014                       # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173566.134429                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173350.385734                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176425.817860                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176425.817860                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174965.326296                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174851.567726                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     20369965                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10454543                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1008                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       477453                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       477447                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        508237                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      8929000                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        19330                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        19330                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback      4444983                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      8042862                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       852297                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       366971                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       363003                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       446864                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           48                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           68                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1185291                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1125998                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4679754                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4554667                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       467005                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       459760                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14038440                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16622497                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       296146                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       569967                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         31527050                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    299504632                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    528992733                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1062248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1967800                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         831527413                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5090691                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     25485456                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.028305                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.165844                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests     19832170                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10173061                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1095                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      1632026                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1631848                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          178                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq        456067                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      8724452                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        22620                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        22620                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      3978006                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      6573071                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2099842                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       741149                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       395876                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       358205                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       460652                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           80                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          128                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1084167                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1021480                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4832090                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4231593                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       474723                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       464424                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14495311                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15429373                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       311743                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       489874                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         30726301                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    618432504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    588237954                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1183896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1770272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1209624626                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    5375046                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     15685523                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.117781                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.322383                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          24764094     97.17%     97.17% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            721356      2.83%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2                 6      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          13838252     88.22%     88.22% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           1847093     11.78%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               178      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      25485456                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   13733891999                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      15685523                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   19622729498                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    167318993                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    175341179                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7019739500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   7248245000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7617418010                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7009474930                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    163365000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    163756499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    323992499                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    268590000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40317                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40317                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136619                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136619                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47666                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40469                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40469                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              137017                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             137017                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47986                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2378,18 +2369,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122600                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231192                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231192                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       123128                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231764                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231764                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353872                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47686                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354972                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48006                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2399,110 +2390,110 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155707                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338784                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338784                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156143                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355408                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7355408                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496577                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36194000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7513637                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             37181500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               13000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            26640000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              168000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            37419000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565735913                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           566572505                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               30500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92712000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            93098000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147888000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           148204000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115577                       # number of replacements
-system.iocache.tags.tagsinuse               11.281807                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115593                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9206321837000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.831702                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.450105                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.239481                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.465632                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705113                       # Average percentage of cache occupancy
+system.iocache.tags.replacements               115869                       # number of replacements
+system.iocache.tags.tagsinuse               11.294988                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      4                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs               115885                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000035                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         9206093766000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.821408                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.473580                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.238838                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.467099                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705937                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040721                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040721                       # Number of data accesses
+system.iocache.tags.tag_accesses              1043293                       # Number of tag accesses
+system.iocache.tags.data_accesses             1043293                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8868                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8905                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8898                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8935                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8868                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8908                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8898                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8938                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8868                       # number of overall misses
-system.iocache.overall_misses::total             8908                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5195000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1668103306                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1673298306                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8898                       # number of overall misses
+system.iocache.overall_misses::total             8938                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5199500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1681517592                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1686717092                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13929903607                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13929903607                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5564000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1668103306                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1673667306                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5564000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1668103306                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1673667306                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  14021691413                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  14021691413                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5568500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1681517592                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1687086092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5568500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1681517592                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1687086092                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8868                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8905                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8898                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8935                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8868                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8908                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8898                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8938                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8868                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8908                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8898                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8938                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2516,55 +2507,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 188103.665539                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 187905.480741                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 188977.027647                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 188776.395299                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130517.798581                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130517.798581                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 188103.665539                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 187883.622137                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       139100                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 188103.665539                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 187883.622137                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33272                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 131063.443253                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 131063.443253                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 188977.027647                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 188754.317744                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 188977.027647                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 188754.317744                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         36073                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3491                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3617                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.530793                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.973182                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106694                       # number of writebacks
-system.iocache.writebacks::total               106694                       # number of writebacks
+system.iocache.writebacks::writebacks          106957                       # number of writebacks
+system.iocache.writebacks::total               106957                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8868                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8905                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8898                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8935                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8868                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8908                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8898                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8938                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8868                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8908                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3345000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1224703306                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1228048306                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8898                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8938                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3349500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1236617592                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1239967092                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8593503607                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8593503607                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3564000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1224703306                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1228267306                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3564000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1224703306                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1228267306                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8672491413                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8672491413                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3568500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1236617592                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1240186092                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3568500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1236617592                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1240186092                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2578,613 +2569,614 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138103.665539                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 137905.480741                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138977.027647                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 138776.395299                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80517.798581                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80517.798581                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 138103.665539                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 137883.622137                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89100                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 138103.665539                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 137883.622137                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 81063.443253                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 81063.443253                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 138977.027647                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 138754.317744                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 138977.027647                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 138754.317744                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1400633                       # number of replacements
-system.l2c.tags.tagsinuse                63705.794368                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5028924                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1460176                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.444053                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1210264                       # number of replacements
+system.l2c.tags.tagsinuse                62755.466878                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5212344                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1269955                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.104353                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   18928.346727                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   167.390384                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   216.986390                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4428.367994                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    11717.643832                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11340.141344                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   156.822011                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   230.353384                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2614.971757                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     4665.203250                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  9239.567296                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.288824                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002554                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003311                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.067572                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.178797                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.173037                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002393                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003515                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.039901                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.071185                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.140985                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.972073                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10769                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          294                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        48480                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          265                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3          409                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        10095                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          294                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1411                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5015                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        41942                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.164322                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004486                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.739746                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 64230359                       # Number of tag accesses
-system.l2c.tags.data_accesses                64230359                       # Number of data accesses
-system.l2c.Writeback_hits::writebacks         2314762                       # number of Writeback hits
-system.l2c.Writeback_hits::total              2314762                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data           28623                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           30874                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               59497                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          6079                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data          5789                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             11868                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           160432                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           145801                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               306233                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5516                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4550                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       461560                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       521601                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       265120                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         4769                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         3407                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       473807                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       524703                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       267683                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2532716                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          5516                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4550                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              461560                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              682033                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       265120                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          4769                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          3407                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              473807                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              670504                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       267683                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2838949                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         5516                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4550                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             461560                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             682033                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       265120                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         4769                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         3407                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             473807                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             670504                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       267683                       # number of overall hits
-system.l2c.overall_hits::total                2838949                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         45739                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         41402                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             87141                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        10551                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        10041                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           20592                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         478288                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         167740                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             646028                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1990                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2246                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        51456                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       156048                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       188933                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1431                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1351                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        38962                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       102025                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       234272                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         778714                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1990                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2246                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             51456                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            634336                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       188933                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1431                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1351                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             38962                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            269765                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       234272                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1424742                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1990                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2246                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            51456                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           634336                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       188933                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1431                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1351                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            38962                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           269765                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       234272                       # number of overall misses
-system.l2c.overall_misses::total              1424742                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    656419000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    602429500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   1258848500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    138505500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    121106000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    259611500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  64575954000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  22241696500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  86817650500                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    275343500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    312648500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6939841000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  21911323500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  30784141526                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    199825500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    189752500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5267042000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  14361628000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  39331165000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 119572711026                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    275343500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    312648500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6939841000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  86487277500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  30784141526                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    199825500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    189752500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   5267042000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  36603324500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  39331165000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    206390361526                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    275343500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    312648500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6939841000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  86487277500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  30784141526                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    199825500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    189752500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   5267042000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  36603324500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  39331165000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   206390361526                       # number of overall miss cycles
-system.l2c.Writeback_accesses::writebacks      2314762                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          2314762                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        74362                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        72276                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          146638                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        16630                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        15830                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         32460                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       638720                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       313541                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           952261                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7506                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         6796                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       513016                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       677649                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       454053                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6200                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         4758                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       512769                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       626728                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       501955                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3311430                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         7506                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6796                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          513016                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1316369                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       454053                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         6200                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         4758                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          512769                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          940269                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       501955                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4263691                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         7506                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6796                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         513016                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1316369                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       454053                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         6200                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         4758                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         512769                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         940269                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       501955                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4263691                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.615086                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.572832                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.594259                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.634456                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.634302                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.634381                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.748823                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.534986                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.678415                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.265121                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.330489                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.100301                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.230279                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.230806                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.283943                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.075984                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.162790                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.235159                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.265121                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.330489                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.100301                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.481883                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.230806                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.283943                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.075984                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.286902                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.334157                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.265121                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.330489                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.100301                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.481883                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.230806                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.283943                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.075984                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.286902                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.334157                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14351.406896                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14550.734264                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 14446.110327                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13127.239124                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12061.149288                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 12607.396076                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 135014.790252                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132596.259091                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 134386.823017                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138363.567839                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 139202.359751                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134869.422419                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140413.997616                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139640.461216                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140453.367876                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135184.076793                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140765.773095                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 153551.510601                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138363.567839                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 139202.359751                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 134869.422419                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 136343.006703                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139640.461216                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140453.367876                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 135184.076793                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 135685.965563                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 144861.568990                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138363.567839                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 139202.359751                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 134869.422419                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 136343.006703                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 162936.816363                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139640.461216                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140453.367876                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 135184.076793                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 135685.965563                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167886.751298                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 144861.568990                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               455                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   23285.968480                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   218.650031                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   386.944281                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4588.836094                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    10476.813165                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 13833.010748                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    53.974082                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker    79.219380                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3039.104298                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3132.206690                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  3660.739630                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.355316                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003336                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.005904                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.070020                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.159863                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.211075                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000824                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.001209                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.046373                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.047794                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.055858                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.957572                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022        10565                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          231                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        48895                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1           43                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          159                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         1447                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         8916                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          229                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1774                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        10274                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        36522                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.161209                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003525                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.746078                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 66950820                       # Number of tag accesses
+system.l2c.tags.data_accesses                66950820                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      2504481                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2504481                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          166895                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          113960                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              280855                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         38875                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         34247                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             73122                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           158326                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           166214                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               324540                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5191                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4009                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       435451                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5208                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::total          2438938                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          5191                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          4009                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              435451                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              720731                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       296765                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.data              646339                       # number of demand (read+write) hits
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+system.l2c.demand_hits::total                 2763478                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         5191                       # number of overall hits
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+system.l2c.overall_hits::total                2763478                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         67422                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         57259                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total            124681                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        14532                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total           25546                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         480698                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         148334                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             629032                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1519                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::total         647095                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1519                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1645                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             47029                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            616840                       # number of demand (read+write) misses
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+system.l2c.demand_misses::cpu1.data            221722                       # number of demand (read+write) misses
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+system.l2c.demand_misses::total               1276127                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1519                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1645                       # number of overall misses
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+system.l2c.overall_misses::cpu1.l2cache.prefetcher       139305                       # number of overall misses
+system.l2c.overall_misses::total              1276127                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data    993921500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data    971150500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total   1965072000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data    192356500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data    170135500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total    362492000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  63553941500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data  19410172500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  82964114000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    210107500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    226821000                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu0.data  18616948500                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    146053000                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu1.data  10187553500                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::total  97218987006                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    210107500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    226821000                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu1.dtb.walker    146053000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    143461000                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::total    180183101006                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    210107500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    226821000                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::total   180183101006                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2504481                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2504481                       # number of WritebackDirty accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data       171219                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          405536                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        53407                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::total         98668                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu1.data       553513                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       401970                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3086033                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         6710                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         5654                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu0.data         1337571                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.dtb.walker         6270                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.data          868061                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       401970                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4039605                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         6710                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.inst         482480                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       504004                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         6270                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       401970                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4039605                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.287738                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.334420                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.307447                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.272099                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.243344                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.258909                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.752238                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.471578                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.659659                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.226379                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.290944                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.097473                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.194893                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.169378                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.190899                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.091926                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.132586                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.209685                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.226379                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.290944                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.097473                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.461164                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.169378                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.190899                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.091926                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.255422                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.315904                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.226379                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.290944                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.097473                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.461164                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.169378                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.190899                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.091926                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.255422                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.315904                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14741.797929                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16960.661206                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 15760.797555                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13236.753372                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15447.203559                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 14189.775307                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132211.786818                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130854.507395                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 131891.722520                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138319.618170                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 137885.106383                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134408.386315                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136746.547722                       # average ReadSharedReq miss latency
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 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        5                       # number of cycles access was blocked
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 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
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 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1097098                       # number of writebacks
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-system.l2c.CleanEvict_mshr_misses::total        44502                       # number of CleanEvict MSHR misses
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-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11716500                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2887877500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5523181000                       # number of WriteReq MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::total  15892763500                       # number of overall MSHR uncacheable cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::total   9184891500                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.overall_mshr_uncacheable_latency::total  16821313000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.615086                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.572832                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.594259                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.634456                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.634302                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.634381                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.748823                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.534986                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.678415                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.265121                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.330489                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.100104                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.230236                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.230806                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.283943                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.075829                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.162772                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.235093                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.265121                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.330489                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.100104                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.481861                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.230806                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.283943                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.075829                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.286890                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.334105                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.265121                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.330489                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.100104                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.481861                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.416103                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.230806                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.283943                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.075829                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.286890                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.466719                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.334105                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73914.176086                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73271.255012                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73608.714612                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76644.014785                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76597.649636                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76621.406371                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 125014.790252                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122596.259091                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 124386.823017                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124901.898549                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130417.195983                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125233.765399                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130769.864921                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143562.269621                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124901.898549                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 126343.607275                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125233.765399                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125687.305842                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 134866.106684                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128363.567839                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129202.359751                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124901.898549                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 126343.607275                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152936.816363                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129640.461216                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130453.367876                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125233.765399                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125687.305842                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157886.751298                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 134866.106684                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140473.866790                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148018.152928                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 127548.709086                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 141538.401633                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149398.732540                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145542.201376                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112560.904348                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 141025.741334                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106513.636364                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148683.687466                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 133274.885113                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.287738                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.334420                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.307447                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.272099                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.243344                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.258909                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.752238                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.471578                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.659659                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.226379                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.290944                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.097312                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.194882                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.169378                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.190899                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.091660                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.132539                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.209612                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.226379                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.290944                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.097312                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.461158                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.169378                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.190899                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.091660                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.255392                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.315848                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.226379                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.290944                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.097312                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.461158                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.169378                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.190899                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.091660                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.255392                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.315848                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73808.148676                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73501.082799                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73667.130517                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76654.176989                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76510.668240                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76592.304079                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122211.786818                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120854.507395                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 121891.722520                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124431.598901                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126748.428019                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124741.078591                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128826.061176                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140249.842714                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124431.598901                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123213.017483                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124741.078591                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123492.394991                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 131199.119373                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124431.598901                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123213.017483                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124741.078591                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123492.394991                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 131199.119373                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146258.531276                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155577.788132                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131258.418927                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145118.029007                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159414.235190                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153388.833474                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145673.001433                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157454.974150                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 138376.408746                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               81299                       # Transaction distribution
-system.membus.trans_dist::ReadResp             868698                       # Transaction distribution
-system.membus.trans_dist::WriteReq              37949                       # Transaction distribution
-system.membus.trans_dist::WriteResp             37949                       # Transaction distribution
-system.membus.trans_dist::Writeback           1203792                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           220565                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           376258                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         321655                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          113911                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            660250                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           639853                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        787399                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122600                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               82463                       # Transaction distribution
+system.membus.trans_dist::ReadResp             738269                       # Transaction distribution
+system.membus.trans_dist::WriteReq              39099                       # Transaction distribution
+system.membus.trans_dist::WriteResp             39099                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1078222                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           196131                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           410883                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         321341                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          158448                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            644070                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           620815                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        655806                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106983                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106983                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123128                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24206                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5071225                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5218123                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341689                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       341689                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5559812                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155707                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        28306                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4701222                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4852748                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342712                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342712                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5195460                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156143                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        48412                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    161136300                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    161340623                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7239232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7239232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               168579855                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           607627                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3798608                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        56612                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    143440556                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    143653515                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7262336                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7262336                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               150915851                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           600183                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3537604                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3798608    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3537604    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3798608                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           101169498                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3537604                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           101645000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            20972999                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            23516499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8203462570                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7437675124                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7924808506                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7217345032                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          230064369                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228825593                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3195,11 +3187,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             162                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              162                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -3238,52 +3230,52 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     10304168                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      5242935                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1823032                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         155703                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       143721                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        11982                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              81301                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4203748                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             37949                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            37949                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          3518592                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1268318                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          429580                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        333523                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         763103                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           68                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           68                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1086913                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1086913                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4129694                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7476293                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6448186                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              13924479                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    230559242                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    190965829                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              421525071                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3161630                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         12055300                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.328437                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.471756                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests     10517449                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      5725465                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1766756                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         114752                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       104186                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        10566                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              82465                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           3940978                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             39099                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            39099                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3582727                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1240251                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          683521                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        394463                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1077983                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          128                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          128                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1083401                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1083400                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      3865739                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106983                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8168699                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6135080                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              14303779                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    247232417                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    172105066                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              419337483                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2918298                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          7581961                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.362851                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.483712                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                8107870     67.26%     67.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3935448     32.64%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  11982      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4841404     63.85%     63.85% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                2729991     36.01%     99.86% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  10566      0.14%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           12055300                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         7945670452                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            7581961                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8230397518                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2561165                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2646637                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4404072117                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4512530115                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3899520231                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3554923231                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index b90977aa0..414f238d4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -1,137 +1,137 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.811426                       # Number of seconds simulated
-sim_ticks                                51811426272500                       # Number of ticks simulated
-final_tick                               51811426272500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.811412                       # Number of seconds simulated
+sim_ticks                                51811412441500                       # Number of ticks simulated
+final_tick                               51811412441500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 429786                       # Simulator instruction rate (inst/s)
-host_op_rate                                   505081                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            26846252166                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 669952                       # Number of bytes of host memory used
-host_seconds                                  1929.93                       # Real time elapsed on the host
-sim_insts                                   829457901                       # Number of instructions simulated
-sim_ops                                     974772546                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 619887                       # Simulator instruction rate (inst/s)
+host_op_rate                                   728480                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            38746850862                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 721116                       # Number of bytes of host memory used
+host_seconds                                  1337.18                       # Real time elapsed on the host
+sim_insts                                   828899207                       # Number of instructions simulated
+sim_ops                                     974107036                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       136896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       149440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           4672052                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          65294216                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        405248                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             70657852                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      4672052                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4672052                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     61426304                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       133568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       141632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           4651380                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          65025608                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        401792                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             70353980                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      4651380                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         4651380                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     61199552                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          61446884                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         2139                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         2335                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             113408                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1020235                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6332                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1144449                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          959786                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          61220132                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         2087                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         2213                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             113085                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1016038                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6278                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1139701                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          956243                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               962359                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           2884                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst                90174                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1260228                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7822                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1363750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           90174                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              90174                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1185574                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               958816                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2578                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           2734                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                89775                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1255044                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7755                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1357886                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           89775                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              89775                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1181198                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1185972                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1185574                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2642                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          2884                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               90174                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1260625                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7822                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2549722                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1144449                       # Number of read requests accepted
-system.physmem.writeReqs                       962359                       # Number of write requests accepted
-system.physmem.readBursts                     1144449                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     962359                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 73193536                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     51200                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  61446016                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  70657852                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               61446884                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      800                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2245                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         140011                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               69107                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               74090                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               73242                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               69271                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               67156                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               73972                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               66324                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               66322                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               69640                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              111279                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              69249                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              69472                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              65127                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              68635                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              67352                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              63411                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               57809                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               62464                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               62675                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               60788                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               58616                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63580                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               58138                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               59016                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               60306                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               62192                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              60798                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              61491                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              56659                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              60390                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              59031                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              56141                       # Per bank write bursts
+system.physmem.bw_write::total                1181596                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1181198                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2578                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          2734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               89775                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1255441                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7755                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2539481                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1139701                       # Number of read requests accepted
+system.physmem.writeReqs                       958816                       # Number of write requests accepted
+system.physmem.readBursts                     1139701                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     958816                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 72891072                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     49792                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  61218752                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  70353980                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               61220132                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      778                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         295779                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               70381                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               75813                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               71139                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               67493                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               63564                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               70698                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               65929                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               63583                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               66194                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              109788                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              68376                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              70520                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              68080                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              71994                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              69489                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              65882                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               58404                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               62356                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60883                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               59981                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               56389                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               60703                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               57931                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               57426                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               58562                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               60878                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              59750                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              62184                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              59419                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              62742                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              60987                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              57948                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          31                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51811423590500                       # Total gap between requests
+system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51811409612500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1101333                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1096585                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 959786                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1115953                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     21968                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       419                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       345                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       482                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       537                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       511                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1143                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       670                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       290                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      346                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      111                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 956243                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1112094                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     21162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       399                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       340                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       468                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       547                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       537                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       625                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       281                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      324                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      151                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      107                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       95                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                       91                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       70                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       53                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       71                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       51                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -159,160 +159,161 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16                    16531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    54388                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    55199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    56950                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    56683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    57911                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    58143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    59332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    58934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    59348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    63120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    58684                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    57432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    58229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    56389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    55725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    55034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      972                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      470                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      482                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::39                      346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      287                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      257                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      272                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       82                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       451899                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      297.940982                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     172.093990                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     328.963355                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         180364     39.91%     39.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       110273     24.40%     64.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        39544      8.75%     73.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23126      5.12%     78.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15873      3.51%     81.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11951      2.64%     84.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         9990      2.21%     86.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8720      1.93%     88.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        52058     11.52%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         451899                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         54067                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.152052                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      336.366692                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          54065    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    13699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    16507                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples       450541                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      297.663263                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     171.634069                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.395643                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         180604     40.09%     40.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       109821     24.38%     64.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        39191      8.70%     73.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        22619      5.02%     78.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15643      3.47%     81.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11800      2.62%     84.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10101      2.24%     86.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8767      1.95%     88.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        51995     11.54%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         450541                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         53849                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.149826                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      337.005181                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          53847    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           54067                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         54067                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.757486                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.129918                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.530147                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           51801     95.81%     95.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             269      0.50%     96.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              70      0.13%     96.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             325      0.60%     97.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              45      0.08%     97.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             331      0.61%     97.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             216      0.40%     98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              22      0.04%     98.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              68      0.13%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             136      0.25%     98.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              27      0.05%     98.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              36      0.07%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             464      0.86%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              28      0.05%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              27      0.05%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             146      0.27%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              11      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             6      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            21      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           54067                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    14370740504                       # Total ticks spent queuing
-system.physmem.totMemAccLat               35814159254                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5718245000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12565.69                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           53849                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         53849                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.763431                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.132779                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.573717                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           51569     95.77%     95.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             271      0.50%     96.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              82      0.15%     96.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             312      0.58%     97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              52      0.10%     97.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             350      0.65%     97.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             234      0.43%     98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              17      0.03%     98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              58      0.11%     98.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             145      0.27%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              23      0.04%     98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              22      0.04%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             441      0.82%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              31      0.06%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              32      0.06%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             152      0.28%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               4      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               4      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             3      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            26      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           53849                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    14314490470                       # Total ticks spent queuing
+system.physmem.totMemAccLat               35669296720                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5694615000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12568.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31315.69                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31318.44                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.41                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.19                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.18                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.36                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.19                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.18                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.25                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     921781                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    730062                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.04                       # Row buffer hit rate for writes
-system.physmem.avgGap                     24592380.32                       # Average gap between requests
-system.physmem.pageHitRate                      78.52                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1754978400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  957577500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4363975200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3130397280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3384070123200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1298615760765                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29947715800500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34640608612845                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.590209                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49820119093739                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1730097200000                       # Time in different power states
+system.physmem.avgWrQLen                        27.89                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     918030                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    726894                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.61                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.99                       # Row buffer hit rate for writes
+system.physmem.avgGap                     24689535.33                       # Average gap between requests
+system.physmem.pageHitRate                      78.50                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1704243240                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  929894625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4279041000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3071993040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3384069106080                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1294968358125                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29950905933000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34639928569110                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.577285                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49825452803142                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1730096680000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    261204441261                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    255862301858                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1661378040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  906505875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4556448000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3091011840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3384070123200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1293042304755                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29952604797000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34639932568710                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.577161                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49828251258491                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1730097200000                       # Time in different power states
+system.physmem_1.actEnergy                 1701846720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  928587000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4604519400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3126405600                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3384069106080                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1295387816850                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29950537986750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34640356268400                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.585540                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49824790858475                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1730096680000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    253077157009                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    256517624025                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -366,69 +367,70 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    184770                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                184770                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        12350                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       144149                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore           17                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       184753                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean     0.216505                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev    70.872440                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-2047       184751    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                    185269                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                185269                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        12948                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       144056                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore           19                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       185250                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean     0.215924                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev    70.777306                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-2047       185248    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       184753                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       156516                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 24678.339595                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 20707.909662                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 17878.729982                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       155309     99.23%     99.23% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         1041      0.67%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143           36      0.02%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           66      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           20      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           39      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       156516                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples  -8954848740                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     1.174586                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0      1563388704    -17.46%    -17.46% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::1    -10518237444    117.46%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total  -8954848740                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        144150     92.11%     92.11% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         12350      7.89%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       156500                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       184770                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::total       185250                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       157023                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 24782.458621                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 20866.161950                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 18013.175833                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       155872     99.27%     99.27% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071            4      0.00%     99.27% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607          991      0.63%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143           17      0.01%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           68      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           22      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           34      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287            6      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       157023                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples   3934185148                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.600903                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.489713                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0      1570120704     39.91%     39.91% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::1      2364064444     60.09%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total   3934185148                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        144057     91.75%     91.75% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         12948      8.25%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       157005                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       185269                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       184770                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       156500                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       185269                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       157005                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       156500                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       341270                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       157005                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       342274                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    156218154                       # DTB read hits
-system.cpu.dtb.read_misses                     137197                       # DTB read misses
-system.cpu.dtb.write_hits                   141774250                       # DTB write hits
-system.cpu.dtb.write_misses                     47573                       # DTB write misses
+system.cpu.dtb.read_hits                    156094559                       # DTB read hits
+system.cpu.dtb.read_misses                     137688                       # DTB read misses
+system.cpu.dtb.write_hits                   141675607                       # DTB write hits
+system.cpu.dtb.write_misses                     47581                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               37807                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid               37806                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                     999                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    70344                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                    70732                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   7209                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   6720                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     18555                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                156355351                       # DTB read accesses
-system.cpu.dtb.write_accesses               141821823                       # DTB write accesses
+system.cpu.dtb.perms_faults                     18565                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                156232247                       # DTB read accesses
+system.cpu.dtb.write_accesses               141723188                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         297992404                       # DTB hits
-system.cpu.dtb.misses                          184770                       # DTB misses
-system.cpu.dtb.accesses                     298177174                       # DTB accesses
+system.cpu.dtb.hits                         297770166                       # DTB hits
+system.cpu.dtb.misses                          185269                       # DTB misses
+system.cpu.dtb.accesses                     297955435                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -458,95 +460,93 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    119016                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                119016                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walks                    118504                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                118504                       # Table walker walks initiated with long descriptors
 system.cpu.itb.walker.walksLongTerminationLevel::Level2         1110                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       107588                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       119016                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          119016    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       119016                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       108698                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 28702.878618                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24805.101383                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 21517.827982                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       107219     98.64%     98.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071            1      0.00%     98.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1293      1.19%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           35      0.03%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           66      0.06%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           33      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           38      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       107076                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       118504                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          118504    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       118504                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       108186                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28679.602721                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24825.752216                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 21031.513378                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       106793     98.71%     98.71% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071            1      0.00%     98.71% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         1215      1.12%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           32      0.03%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           67      0.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           29      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           34      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::851968-917503            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       108698                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples   1449242704                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0      1449242704    100.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total   1449242704                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        107588     98.98%     98.98% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1110      1.02%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       108698                       # Table walker page sizes translated
+system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       108186                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples   1449611704                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0      1449611704    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total   1449611704                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        107076     98.97%     98.97% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1110      1.03%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       108186                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       119016                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       119016                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       118504                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       118504                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       108698                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       108698                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       227714                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    829969192                       # ITB inst hits
-system.cpu.itb.inst_misses                     119016                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       108186                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       108186                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       226690                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    829409821                       # ITB inst hits
+system.cpu.itb.inst_misses                     118504                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               37807                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid               37806                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                     999                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    50385                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    50494                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                830088208                       # ITB inst accesses
-system.cpu.itb.hits                         829969192                       # DTB hits
-system.cpu.itb.misses                          119016                       # DTB misses
-system.cpu.itb.accesses                     830088208                       # DTB accesses
-system.cpu.numCycles                     103622852545                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                829528325                       # ITB inst accesses
+system.cpu.itb.hits                         829409821                       # DTB hits
+system.cpu.itb.misses                          118504                       # DTB misses
+system.cpu.itb.accesses                     829528325                       # DTB accesses
+system.cpu.numCycles                     103622824883                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    15973                       # number of quiesce instructions executed
-system.cpu.committedInsts                   829457901                       # Number of instructions committed
-system.cpu.committedOps                     974772546                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             896189211                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 901491                       # Number of float alu accesses
-system.cpu.num_func_calls                    49868985                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    125722281                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    896189211                       # number of integer instructions
-system.cpu.num_fp_insts                        901491                       # number of float instructions
-system.cpu.num_int_register_reads          1296374406                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          710181687                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              1455753                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              759888                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            214623564                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           214015228                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     297970911                       # number of memory refs
-system.cpu.num_load_insts                   156208355                       # Number of load instructions
-system.cpu.num_store_insts                  141762556                       # Number of store instructions
-system.cpu.num_idle_cycles               100538268245.312057                       # Number of idle cycles
-system.cpu.num_busy_cycles               3084584299.687941                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.029767                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.970233                       # Percentage of idle cycles
-system.cpu.Branches                         185080610                       # Number of branches fetched
+system.cpu.committedInsts                   828899207                       # Number of instructions committed
+system.cpu.committedOps                     974107036                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             895578515                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 899571                       # Number of float alu accesses
+system.cpu.num_func_calls                    49817464                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    125652530                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    895578515                       # number of integer instructions
+system.cpu.num_fp_insts                        899571                       # number of float instructions
+system.cpu.num_int_register_reads          1295563811                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          709708276                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              1453001                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              757712                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            214507812                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           213899539                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     297748170                       # number of memory refs
+system.cpu.num_load_insts                   156084233                       # Number of load instructions
+system.cpu.num_store_insts                  141663937                       # Number of store instructions
+system.cpu.num_idle_cycles               100539253419.334061                       # Number of idle cycles
+system.cpu.num_busy_cycles               3083571463.665941                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.029758                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.970242                       # Percentage of idle cycles
+system.cpu.Branches                         184944487                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 675027682     69.21%     69.21% # Class of executed instruction
-system.cpu.op_class::IntMult                  2118642      0.22%     69.43% # Class of executed instruction
-system.cpu.op_class::IntDiv                     97301      0.01%     69.44% # Class of executed instruction
+system.cpu.op_class::IntAlu                 674583276     69.21%     69.21% # Class of executed instruction
+system.cpu.op_class::IntMult                  2119587      0.22%     69.43% # Class of executed instruction
+system.cpu.op_class::IntDiv                     97316      0.01%     69.44% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     69.44% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     69.44% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     69.44% # Class of executed instruction
@@ -573,120 +573,120 @@ system.cpu.op_class::SimdFloatMisc             112382      0.01%     69.45% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     69.45% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.45% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.45% # Class of executed instruction
-system.cpu.op_class::MemRead                156208355     16.02%     85.47% # Class of executed instruction
-system.cpu.op_class::MemWrite               141762556     14.53%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                156084233     16.01%     85.47% # Class of executed instruction
+system.cpu.op_class::MemWrite               141663937     14.53%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  975326961                       # Class of executed instruction
-system.cpu.dcache.tags.replacements           9274254                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.942797                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           288519025                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9274766                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             31.107957                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        5829979500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.942797                       # Average occupied blocks per requestor
+system.cpu.op_class::total                  974660774                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           9257757                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.942792                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           288314388                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9258269                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             31.141284                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        5830299500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.942792                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999888                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999888                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          412                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1200910515                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1200910515                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146286950                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146286950                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    134627740                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      134627740                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       371143                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        371143                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       331538                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       331538                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3288519                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3288519                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3571476                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3571476                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     280914690                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        280914690                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    281285833                       # number of overall hits
-system.cpu.dcache.overall_hits::total       281285833                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4843075                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4843075                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1971266                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1971266                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1110209                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1110209                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1222439                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1222439                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       284576                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       284576                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            3                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      6814341                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        6814341                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7924550                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7924550                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  83223241000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  83223241000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  66964103500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  66964103500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  73311177500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  73311177500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4361265000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4361265000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       247000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       247000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 150187344500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 150187344500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 150187344500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 150187344500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    151130025                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    151130025                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    136599006                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    136599006                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1481352                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1481352                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1553977                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1553977                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3573095                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3573095                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3571479                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3571479                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    287729031                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    287729031                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    289210383                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    289210383                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032046                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032046                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014431                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.014431                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.749457                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.749457                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786652                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.786652                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079644                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079644                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.tags.tag_accesses        1200005027                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1200005027                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146175483                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146175483                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    134535173                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      134535173                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       372977                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        372977                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       334025                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       334025                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3285857                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3285857                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3569334                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3569334                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     280710656                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        280710656                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    281083633                       # number of overall hits
+system.cpu.dcache.overall_hits::total       281083633                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4833353                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4833353                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1968837                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1968837                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1108112                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1108112                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1218438                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1218438                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       285095                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       285095                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      6802190                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        6802190                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7910302                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7910302                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  82947634000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  82947634000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  66857595000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  66857595000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  73267815000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  73267815000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4367237000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   4367237000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 149805229000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 149805229000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 149805229000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 149805229000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    151008836                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    151008836                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    136504010                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    136504010                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1481089                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1481089                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1552463                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1552463                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3570952                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3570952                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3569336                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3569336                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    287512846                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    287512846                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    288993935                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    288993935                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032007                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032007                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014423                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.014423                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.748174                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.748174                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.784842                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.784842                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079837                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079837                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023683                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023683                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.027401                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.027401                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17183.967004                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17183.967004                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33970.100179                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33970.100179                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 59971.235784                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 59971.235784                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15325.484229                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15325.484229                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82333.333333                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82333.333333                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22039.892706                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22039.892706                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18952.160627                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18952.160627                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023659                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023659                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.027372                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.027372                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17161.509619                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17161.509619                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33957.912717                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33957.912717                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60132.575478                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60132.575478                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15318.532419                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15318.532419                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.088005                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22023.088005                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18937.991116                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18937.991116                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -695,154 +695,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7273356                       # number of writebacks
-system.cpu.dcache.writebacks::total           7273356                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        23715                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        23715                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21271                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        21271                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        68399                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        68399                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        44986                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        44986                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        44986                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        44986                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      4819360                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      4819360                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1949995                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1949995                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1108464                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1108464                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1222439                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1222439                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       216177                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       216177                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            3                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      6769355                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      6769355                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      7877819                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      7877819                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      7254734                       # number of writebacks
+system.cpu.dcache.writebacks::total           7254734                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        23450                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        23450                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21299                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        21299                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        67486                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        67486                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        44749                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        44749                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        44749                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        44749                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      4809903                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      4809903                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1947538                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1947538                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1106332                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1106332                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1218438                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1218438                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       217609                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       217609                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      6757441                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      6757441                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      7863773                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      7863773                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33708                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67410                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67410                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  77027858500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  77027858500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  64047484500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  64047484500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  21144827000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  21144827000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  72088738500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  72088738500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2970895000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2970895000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       244000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       244000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141075343000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 141075343000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162220170000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 162220170000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5832027500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5832027500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5823842500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5823842500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11655870000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11655870000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.031889                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031889                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014275                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014275                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.748279                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.748279                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786652                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786652                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060501                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060501                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  76766734500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  76766734500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  63925265000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  63925265000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20988734000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20988734000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  72049377000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  72049377000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2989622500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2989622500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       163500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       163500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140691999500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 140691999500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161680733500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 161680733500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6200659500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6200659500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6217612000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6217612000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12418271500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12418271500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.031852                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031852                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.746972                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.746972                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.784842                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.784842                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060939                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060939                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023527                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.023527                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027239                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027239                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15983.005731                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15983.005731                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32844.948064                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32844.948064                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19075.790463                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19075.790463                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 58971.235784                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 58971.235784                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13742.881990                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13742.881990                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81333.333333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81333.333333                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20840.293204                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20840.293204                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20592.015379                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20592.015379                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173046.925998                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173046.925998                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172773.303073                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172773.303073                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172910.102359                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172910.102359                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023503                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.023503                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027211                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027211                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15960.141920                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15960.141920                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32823.629115                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32823.629115                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18971.460647                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18971.460647                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59132.575478                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59132.575478                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13738.505760                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13738.505760                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81750                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20820.307495                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20820.307495                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20560.198457                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20560.198457                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183984.911875                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.911875                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.084846                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.084846                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184220.019285                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184220.019285                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          13424392                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.782428                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           816544283                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          13424904                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             60.823100                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       61690343500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.782428                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements          13402148                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.782420                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           816007156                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          13402660                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             60.883970                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       61704805500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.782420                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999575                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999575                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          194                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          198                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         843394101                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        843394101                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    816544283                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       816544283                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     816544283                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        816544283                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    816544283                       # number of overall hits
-system.cpu.icache.overall_hits::total       816544283                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     13424909                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      13424909                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     13424909                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       13424909                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     13424909                       # number of overall misses
-system.cpu.icache.overall_misses::total      13424909                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 183122611500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 183122611500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 183122611500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 183122611500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 183122611500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 183122611500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    829969192                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    829969192                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    829969192                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    829969192                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    829969192                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    829969192                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016175                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016175                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016175                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016175                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016175                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016175                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13640.510450                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13640.510450                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13640.510450                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13640.510450                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13640.510450                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13640.510450                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         842812486                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        842812486                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    816007156                       # number of ReadReq hits
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+system.cpu.icache.demand_hits::cpu.inst     816007156                       # number of demand (read+write) hits
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+system.cpu.icache.ReadReq_misses::cpu.inst     13402665                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::total      13402665                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 183016744500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 183016744500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 183016744500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 183016744500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 183016744500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 183016744500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    829409821                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    829409821                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    829409821                       # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::cpu.inst    829409821                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    829409821                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016159                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016159                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016159                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016159                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016159                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016159                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13655.250243                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13655.250243                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13655.250243                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13655.250243                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13655.250243                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13655.250243                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -851,224 +851,230 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13424909                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     13424909                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     13424909                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     13424909                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     13424909                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     13424909                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     13402148                       # number of writebacks
+system.cpu.icache.writebacks::total          13402148                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13402665                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     13402665                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     13402665                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::cpu.inst     13402665                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     13402665                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169697702500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 169697702500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169697702500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 169697702500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169697702500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 169697702500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   5436505000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   5436505000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   5436505000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total   5436505000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016175                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016175                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016175                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016175                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016175                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016175                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12640.510450                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12640.510450                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12640.510450                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12640.510450                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12640.510450                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12640.510450                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126063.884058                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126063.884058                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126063.884058                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126063.884058                       # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169614079500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 169614079500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169614079500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 169614079500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169614079500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 169614079500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   5436787000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   5436787000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   5436787000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total   5436787000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016159                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016159                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016159                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016159                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016159                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016159                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12655.250243                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12655.250243                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12655.250243                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12655.250243                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12655.250243                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12655.250243                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1005896                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65240.839104                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           41644910                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1067543                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            39.010054                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      56084638500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37646.783176                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   207.132082                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   316.131551                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8682.647548                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 18388.144746                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.574444                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.003161                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.004824                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.132487                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.280581                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995496                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          202                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61445                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          202                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          409                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2441                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5535                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53023                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003082                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.937576                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        372207477                       # Number of tag accesses
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-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       308614                       # number of ReadReq hits
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-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.786897                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.tags.avg_refs            39.151498                       # Average number of references to valid blocks.
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+system.cpu.l2cache.InvalidateReq_accesses::total      1218438                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       311814                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       244191                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     13402665                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      8039845                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     21998515                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       311814                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       244191                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     13402665                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      8039845                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     21998515                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006693                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.009063                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.007734                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.787154                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.787154                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.166777                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.166777                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005238                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005238                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.036387                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.036387                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.392330                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.392330                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006883                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.009514                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005238                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.067289                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.027986                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006883                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.009514                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005238                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.067289                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.027986                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135398.550725                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137891.862955                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 136699.821189                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41847.997193                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41847.997193                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79833.333333                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79833.333333                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130988.049380                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130988.049380                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132155.290102                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132155.290102                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133117.622326                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133117.622326                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130223.655129                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130223.655129                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135398.550725                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137891.862955                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132155.290102                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131866.725049                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 131934.700182                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135398.550725                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137891.862955                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132155.290102                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131866.725049                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 131934.700182                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.166390                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.166390                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005223                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005223                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.035964                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.035964                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.393538                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.393538                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006693                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.009063                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005223                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.066884                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.027822                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006693                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.009063                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005223                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.066884                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.027822                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137105.414471                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137321.057388                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137216.395349                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41543.522143                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41543.522143                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130983.207732                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130983.207732                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132181.686358                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132181.686358                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133185.935765                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133185.935765                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130266.161559                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130266.161559                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137105.414471                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137321.057388                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132181.686358                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131886.832734                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 131957.998928                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137105.414471                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137321.057388                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132181.686358                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131886.832734                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 131957.998928                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1077,35 +1083,33 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       853156                       # number of writebacks
-system.cpu.l2cache.writebacks::total           853156                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         2139                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2335                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4474                       # number of ReadReq MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1011                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1011                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        32779                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        32779                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       318268                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       318268                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        70320                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        70320                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       223563                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       223563                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       479600                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       479600                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         2139                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2335                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        70320                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       541831                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       616625                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         2139                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2335                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        70320                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       541831                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       616625                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks::writebacks       849613                       # number of writebacks
+system.cpu.l2cache.writebacks::total           849613                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         2087                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2213                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4300                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        32696                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        32696                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       317140                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       317140                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        69997                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        69997                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       220595                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       220595                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       479502                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       479502                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         2087                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2213                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        69997                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       537735                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       612032                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         2087                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2213                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        69997                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       537735                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       612032                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76827                       # number of ReadReq MSHR uncacheable
@@ -1114,154 +1118,153 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33708
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67410                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110535                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    268227500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    298627500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    566855000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2316135000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2316135000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       209500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       209500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  38506624500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  38506624500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   8589960000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   8589960000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27524545000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27524545000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  57659265000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  57659265000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    268227500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    298627500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8589960000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  66031169500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  75187984500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    268227500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    298627500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8589960000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  66031169500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  75187984500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   4897442500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5410752500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  10308195000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5436200500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5436200500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   4897442500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10846953000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  15744395500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006883                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009514                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008044                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.786897                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.786897                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    265269000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    281761500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    547030500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2311098000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2311098000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  38368614500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  38368614500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   8552351500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   8552351500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27174201500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27174201500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  57667865000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  57667865000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    265269000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    281761500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8552351500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  65542816000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  74642198000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    265269000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    281761500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8552351500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  65542816000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  74642198000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5778581000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  10676305500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5829959000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5829959000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11608540000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  16506264500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006693                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009063                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.007734                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.787154                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.787154                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.166777                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.166777                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005238                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005238                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.036387                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.036387                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.392330                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.392330                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006883                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009514                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005238                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.067289                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.027986                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006883                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009514                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005238                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.067289                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.027986                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127891.862955                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126699.821189                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70659.111016                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70659.111016                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120988.049380                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120988.049380                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122155.290102                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122155.290102                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123117.622326                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123117.622326                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120223.655129                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120223.655129                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127891.862955                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122155.290102                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121866.725049                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121934.700182                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127891.862955                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122155.290102                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121866.725049                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121934.700182                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113563.884058                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160546.925998                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134174.118474                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161273.303073                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161273.303073                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113563.884058                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160910.146862                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 142438.101054                       # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.166390                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.166390                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005223                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005223                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.035964                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.035964                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.393538                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.393538                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006693                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009063                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005223                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.066884                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.027822                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006693                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009063                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005223                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.066884                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.027822                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127321.057388                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127216.395349                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70684.426230                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70684.426230                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120983.207732                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120983.207732                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122181.686358                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122181.686358                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123185.935765                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123185.935765                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120266.161559                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120266.161559                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127321.057388                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122181.686358                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121886.832734                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121957.998928                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127321.057388                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122181.686358                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121886.832734                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121957.998928                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171461.070560                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138965.539459                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.758514                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.758514                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172207.981012                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149330.659972                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     45918929                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     23219248                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1752                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2704                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2704                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     45838189                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     23177247                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1749                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2695                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2695                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         973260                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      20543031                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         972617                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      20509993                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33708                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33708                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      8233173                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     15585132                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        41659                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        41662                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1908339                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1908339                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     13424909                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6152877                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1329103                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1222439                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     40358865                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     28042657                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       601098                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       851524                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          69854144                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    859366676                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    981090094                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1963488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2486024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1844906282                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1578062                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     47683915                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.010174                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.100353                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8211016                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     13400558                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2162503                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        41540                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        41542                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1906001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1906001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     13402665                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6142720                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1325102                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1218438                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     40292138                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27992932                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       598317                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       853478                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          69736865                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1715578772                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    979098990                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1953528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2494512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2699125802                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1572119                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     24940276                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.019256                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.137423                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           47198764     98.98%     98.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             485151      1.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           24460029     98.07%     98.07% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             480247      1.93%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       47683915                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    30513690500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       24940276                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    43858094500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1602380                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1606889                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   20180488500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   20147122500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   12761129471                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   12740327469                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     355662000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     354126000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     540771000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     541664000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                40324                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40324                       # Transaction distribution
@@ -1309,37 +1312,37 @@ system.iobus.pkt_size_system.realview.ide.dma::total      7334456
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  7492376                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             42148000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               16500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25746500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              169000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            38603000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              122000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565894582                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           565448922                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               30500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
@@ -1348,16 +1351,16 @@ system.iobus.respLayer3.utilization               0.0                       # La
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements               115484                       # number of replacements
-system.iocache.tags.tagsinuse               10.446961                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               10.446943                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs               115500                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13183666451000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.511449                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.935511                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219466                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.433469                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.652935                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13183709784000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.511467                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.935476                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219467                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433467                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.652934                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1376,19 +1379,19 @@ system.iocache.demand_misses::total              8879                       # nu
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
 system.iocache.overall_misses::realview.ide         8839                       # number of overall misses
 system.iocache.overall_misses::total             8879                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1643284102                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1648353102                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1627645138                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1632715138                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13826197480                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13826197480                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1643284102                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1648704102                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1643284102                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1648704102                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13865007784                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13865007784                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1627645138                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1633066138                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1627645138                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1633066138                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8839                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8876                       # number of ReadReq accesses(hits+misses)
@@ -1415,24 +1418,24 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 185912.897613                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 185709.002028                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184143.583890                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 183947.176431                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129623.841971                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129623.841971                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 185912.897613                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 185685.786913                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 185912.897613                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 185685.786913                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32536                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.697667                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129987.697667                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 184143.583890                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183924.556594                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 184143.583890                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183924.556594                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         33671                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3376                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3496                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.637441                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.631293                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1451,19 +1454,19 @@ system.iocache.demand_mshr_misses::total         8879                       # nu
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::realview.ide         8839                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total         8879                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1201334102                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1204553102                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1185695138                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1188915138                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8492997480                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8492997480                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1201334102                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1204754102                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1201334102                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1204754102                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8531807784                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8531807784                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1185695138                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1189116138                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1185695138                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1189116138                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1477,73 +1480,73 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135912.897613                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 135709.002028                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134143.583890                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 133947.176431                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79623.841971                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79623.841971                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 135912.897613                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 135685.786913                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 135912.897613                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 135685.786913                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79987.697667                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79987.697667                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 134143.583890                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 133924.556594                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 134143.583890                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 133924.556594                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               76827                       # Transaction distribution
-system.membus.trans_dist::ReadResp             384060                       # Transaction distribution
+system.membus.trans_dist::ReadResp             380595                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33708                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33708                       # Transaction distribution
-system.membus.trans_dist::Writeback            959786                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           158940                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            33352                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           33355                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            797298                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           797298                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        307233                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       956243                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           155849                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            33272                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           33274                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            796069                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           796069                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        303768                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6930                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3354625                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3484317                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341373                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       341373                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3825690                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3338566                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3468258                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341194                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341194                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3809452                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13860                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    124875168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    125044994                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7229568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7229568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               132274562                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3206                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2476492                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    124348000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    124517826                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7226112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7226112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               131743938                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3260                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2465217                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2476492    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2465217    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2476492                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           107338500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2465217                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           106924000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5425000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5793500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          6302386470                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          6289776705                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6068941451                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6042674003                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228333558                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227496341                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index 2bef0a385..efee64ea0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -4,71 +4,71 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 564761                       # Simulator instruction rate (inst/s)
-host_op_rate                                   663687                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            29317960092                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 669948                       # Number of bytes of host memory used
-host_seconds                                  1743.34                       # Real time elapsed on the host
+host_inst_rate                                1108699                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1302904                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            57554949131                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 721016                       # Number of bytes of host memory used
+host_seconds                                   888.04                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker       203392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker       187968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3317876                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         64750152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3272948                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         64755976                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker       208384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker       188480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2225152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         45360128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2212992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         45372224                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide        442112                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            116883644                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3317876                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2225152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5543028                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103060608                       # Number of bytes written to this memory
+system.physmem.bytes_read::total            116844476                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3272948                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2212992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5485940                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    103078400                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103081188                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         103098980                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker         3178                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker         2937                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             92249                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           1011734                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             91547                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           1011825                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker         3256                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker         2945                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             34768                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            708752                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             34578                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            708941                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide           6908                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1866727                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1610322                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total               1866115                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1610600                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1612895                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1613173                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker          3979                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker          3678                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               64915                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1266850                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               64036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1266964                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker          4077                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker          3688                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               43536                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              887480                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               43298                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              887717                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide             8650                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2286852                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          64915                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          43536                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108450                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2016402                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2286086                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          64036                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          43298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107334                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2016750                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2016804                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2016402                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2017152                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2016750                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker         3979                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker         3678                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              64915                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1267252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              64036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1267366                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker         4077                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker         3688                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              43536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             887480                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              43298                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             887717                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide            8650                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4303656                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4303238                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
@@ -410,8 +410,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8921279                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8921279                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks      8921277                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8921277                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements         14295641                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.984599                       # Cycle average of tags in use
@@ -475,6 +475,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
+system.cpu0.icache.writebacks::writebacks     14295641                       # number of writebacks
+system.cpu0.icache.writebacks::total         14295641                       # number of writebacks
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -786,30 +788,30 @@ system.iocache.cache_copies                         0                       # nu
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1722562                       # number of replacements
-system.l2c.tags.tagsinuse                65341.862549                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   47048799                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1785858                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    26.345207                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1723178                       # number of replacements
+system.l2c.tags.tagsinuse                65341.862566                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   47049406                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1786474                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    26.336463                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37097.979539                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   156.460552                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   243.494258                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3630.477879                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9618.607320                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.652985                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   37238.861730                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   156.459058                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   243.477138                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3478.418369                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9618.970377                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.652979                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.itb.walker   201.240388                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2660.497968                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    11581.451661                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.566070                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu1.inst     2640.978192                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    11611.804335                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.568220                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002387                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.003715                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.055397                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.146768                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.053076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.146774                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002314                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.003071                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.040596                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.176719                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.040298                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.177182                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.997038                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023          276                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1024        63020                       # Occupied blocks per task id
@@ -821,48 +823,50 @@ system.l2c.tags.age_task_id_blocks_1024::3         4910                       #
 system.l2c.tags.age_task_id_blocks_1024::4        54672                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.004211                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1024     0.961609                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                426841717                       # Number of tag accesses
-system.l2c.tags.data_accesses               426841717                       # Number of data accesses
+system.l2c.tags.tag_accesses                426842331                       # Number of tag accesses
+system.l2c.tags.data_accesses               426842331                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker       279435                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker       145257                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.dtb.walker       276854                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.itb.walker       142757                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                 844303                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         8921279                       # number of Writeback hits
-system.l2c.Writeback_hits::total              8921279                       # number of Writeback hits
+system.l2c.WritebackDirty_hits::writebacks      8921277                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         8921277                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks     14294063                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total        14294063                       # number of WritebackClean hits
 system.l2c.UpgradeReq_hits::cpu0.data            5687                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data            5536                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total               11223                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           864866                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           827692                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1692558                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       7107362                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       7104867                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          14212229                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3754928                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data      3749182                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          7504110                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       345122                       # number of InvalidateReq hits
+system.l2c.ReadExReq_hits::cpu0.data           864865                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           827683                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total              1692548                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst       7108064                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst       7105057                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total          14213121                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data      3754840                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data      3749002                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          7503842                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       345118                       # number of InvalidateReq hits
 system.l2c.InvalidateReq_hits::cpu1.data       349199                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           694321                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           694317                       # number of InvalidateReq hits
 system.l2c.demand_hits::cpu0.dtb.walker        279435                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.itb.walker        145257                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             7107362                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4619794                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst             7108064                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             4619705                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.dtb.walker        276854                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.itb.walker        142757                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             7104867                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4576874                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                24253200                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst             7105057                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data             4576685                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                24253814                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.dtb.walker       279435                       # number of overall hits
 system.l2c.overall_hits::cpu0.itb.walker       145257                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            7107362                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4619794                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            7108064                       # number of overall hits
+system.l2c.overall_hits::cpu0.data            4619705                       # number of overall hits
 system.l2c.overall_hits::cpu1.dtb.walker       276854                       # number of overall hits
 system.l2c.overall_hits::cpu1.itb.walker       142757                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            7104867                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4576874                       # number of overall hits
-system.l2c.overall_hits::total               24253200                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst            7105057                       # number of overall hits
+system.l2c.overall_hits::cpu1.data            4576685                       # number of overall hits
+system.l2c.overall_hits::total               24253814                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker         3178                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker         2937                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker         3256                       # number of ReadReq misses
@@ -873,43 +877,45 @@ system.l2c.UpgradeReq_misses::cpu1.data         19925                       # nu
 system.l2c.UpgradeReq_misses::total             39919                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         415071                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         411488                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             826559                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        49148                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        34781                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           83929                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       177103                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       166985                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         344088                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       420021                       # number of InvalidateReq misses
+system.l2c.ReadExReq_misses::cpu0.data         415072                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         411497                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             826569                       # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst        48446                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst        34591                       # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total           83037                       # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       177191                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       167165                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         344356                       # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data       420025                       # number of InvalidateReq misses
 system.l2c.InvalidateReq_misses::cpu1.data       131007                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         551028                       # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total         551032                       # number of InvalidateReq misses
 system.l2c.demand_misses::cpu0.dtb.walker         3178                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker         2937                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             49148                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            592174                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             48446                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            592263                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker         3256                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.itb.walker         2945                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             34781                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            578473                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1266892                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             34591                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            578662                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1266278                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker         3178                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker         2937                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            49148                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           592174                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            48446                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           592263                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker         3256                       # number of overall misses
 system.l2c.overall_misses::cpu1.itb.walker         2945                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            34781                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           578473                       # number of overall misses
-system.l2c.overall_misses::total              1266892                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            34591                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           578662                       # number of overall misses
+system.l2c.overall_misses::total              1266278                       # number of overall misses
 system.l2c.ReadReq_accesses::cpu0.dtb.walker       282613                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.itb.walker       148194                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.dtb.walker       280110                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.itb.walker       145702                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total             856619                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      8921279                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          8921279                       # number of Writeback accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks      8921277                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      8921277                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks     14294063                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total     14294063                       # number of WritebackClean accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data        25681                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data        25461                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total           51142                       # number of UpgradeReq accesses(hits+misses)
@@ -955,36 +961,36 @@ system.l2c.UpgradeReq_miss_rate::cpu1.data     0.782569                       #
 system.l2c.UpgradeReq_miss_rate::total       0.780552                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.324290                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.332065                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.328115                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006868                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004872                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005871                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045041                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042640                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.043843                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.548944                       # miss rate for InvalidateReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.324291                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.332072                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.328119                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006770                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004845                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005808                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045063                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042686                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.043877                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.548950                       # miss rate for InvalidateReq accesses
 system.l2c.InvalidateReq_miss_rate::cpu1.data     0.272814                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.442469                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.442472                       # miss rate for InvalidateReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.011245                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.019819                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006868                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.113618                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006770                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.113635                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.dtb.walker     0.011624                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.itb.walker     0.020212                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004872                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.112208                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.049643                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004845                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.112245                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.049619                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.011245                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.019819                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006868                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.113618                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006770                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.113635                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.dtb.walker     0.011624                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.itb.walker     0.020212                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004872                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.112208                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.049643                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004845                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.112245                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.049619                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -993,51 +999,51 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1503691                       # number of writebacks
-system.l2c.writebacks::total                  1503691                       # number of writebacks
+system.l2c.writebacks::writebacks             1503969                       # number of writebacks
+system.l2c.writebacks::total                  1503969                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
-system.membus.trans_dist::ReadResp             525866                       # Transaction distribution
+system.membus.trans_dist::ReadResp             525242                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::Writeback           1610322                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           225569                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40486                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1610600                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           224679                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            40488                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40487                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1377023                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1377023                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        449187                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           40489                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1377035                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1377035                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        448563                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5529617                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5658809                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5527785                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5656977                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       344374                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       344374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6003183                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6001351                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    212740128                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    212909178                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    212718752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    212887802                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7391040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      7391040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               220300218                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               220278842                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3921668                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3920446                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3921668    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3920446    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3921668                       # Request fanout histogram
+system.membus.snoop_fanout::total             3920446                       # Request fanout histogram
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
 system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
@@ -1093,15 +1099,16 @@ system.realview.realview_io.osc_system_bus.clock        41667
 system.toL2Bus.snoop_filter.tot_requests     52477792                       # Total number of requests made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_requests     26568978                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_requests         1747                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2719                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2719                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2724                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2724                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.trans_dist::ReadReq            1320350                       # Transaction distribution
 system.toL2Bus.trans_dist::ReadResp          23464706                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33606                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33606                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          8921279                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict        16984756                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      8921277                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     14294063                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2690695                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeReq           51142                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeResp          51143                       # Transaction distribution
@@ -1116,22 +1123,22 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35
 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       832126                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1655216                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count::total              80533877                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    915126612                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1234659686                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1829946644                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1234659558                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3328504                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6620864                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2159735666                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1954363                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         55175249                       # Request fanout histogram
+system.toL2Bus.pkt_size::total             3074555570                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1954979                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         55175865                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::mean            0.011169                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::stdev           0.105093                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               54558983     98.88%     98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 616266      1.12%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               54559594     98.88%     98.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 616271      1.12%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           55175249                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::total           55175865                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index e8e31dd45..929ad0607 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,192 +1,192 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.397579                       # Number of seconds simulated
-sim_ticks                                51397578885000                       # Number of ticks simulated
-final_tick                               51397578885000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.278388                       # Number of seconds simulated
+sim_ticks                                51278388278000                       # Number of ticks simulated
+final_tick                               51278388278000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 213094                       # Simulator instruction rate (inst/s)
-host_op_rate                                   250423                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            11187167929                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 682236                       # Number of bytes of host memory used
-host_seconds                                  4594.33                       # Real time elapsed on the host
-sim_insts                                   979026656                       # Number of instructions simulated
-sim_ops                                    1150528336                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 258575                       # Simulator instruction rate (inst/s)
+host_op_rate                                   303855                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15635824114                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 733268                       # Number of bytes of host memory used
+host_seconds                                  3279.55                       # Real time elapsed on the host
+sim_insts                                   848009832                       # Number of instructions simulated
+sim_ops                                     996505618                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       187840                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       177856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2851188                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         60331016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        46336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        44800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           415360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          9688384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker        76288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker        60224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          1747072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data         13459648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker       113856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker       106880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst          1985280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data         25411584                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        412224                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            117115836                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2851188                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       415360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      1747072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst      1985280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6998900                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    101778880                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        80512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        85376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2480372                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         43948744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        23424                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        20864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           458368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5839488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker        24512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker        21952                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst          1437632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          8179392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker        64832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.itb.walker        58944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst          1702784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data         14408960                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        423680                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             79259836                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2480372                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       458368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst      1437632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst      1702784                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6079156                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     67469760                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         101799460                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2935                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2779                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             84957                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            942685                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          724                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          700                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6490                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            151381                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker         1192                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker          941                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             27298                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data            210307                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker         1779                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker         1670                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst             31020                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data            397056                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6441                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1870355                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1590295                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          67490340                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1258                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1334                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             79163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            686712                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          366                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          326                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              7162                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             91242                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker          383                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker          343                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst             22463                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data            127803                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker         1013                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.itb.walker          921                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst             26606                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data            225140                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6620                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1278855                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1054215                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1592868                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3655                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          3460                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               55473                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1173810                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           902                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker           872                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst                8081                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              188499                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker          1484                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker          1172                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               33991                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              261873                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          2215                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.itb.walker          2079                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst               38626                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data              494412                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8020                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2278626                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          55473                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst           8081                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          33991                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst          38626                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             136172                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1980227                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                400                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1980628                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1980227                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3655                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         3460                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              55473                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1174211                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          902                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker          872                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst               8081                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             188499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker         1484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker         1172                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              33991                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             261873                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         2215                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.itb.walker         2079                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst              38626                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data             494412                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8020                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4259253                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        833134                       # Number of read requests accepted
-system.physmem.writeReqs                       737289                       # Number of write requests accepted
-system.physmem.readBursts                      833134                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     737289                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 53302080                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18496                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  47184896                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  53320576                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               47186496                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      289                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          72650                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               50780                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               53589                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               52846                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               50887                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               54092                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               57010                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               51070                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               50979                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               47072                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               53421                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              50826                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              55035                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              52027                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              53888                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              49567                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              49756                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               44616                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               46679                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               46441                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               46533                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               48478                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               49819                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               45666                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               46728                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               42759                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               46487                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              43753                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              47850                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              45610                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              46767                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              44243                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              44835                       # Per bank write bursts
+system.physmem.num_writes::total              1056788                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1570                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1665                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               48371                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              857062                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           457                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           407                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst                8939                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              113878                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           478                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker           428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               28036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              159510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.itb.walker          1149                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst               33207                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data              280995                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1545677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          48371                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst           8939                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          28036                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst          33207                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             118552                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1315754                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1316156                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1315754                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1570                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1665                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              48371                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             857463                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          457                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          407                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst               8939                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             113878                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          478                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker          428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              28036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             159510                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.itb.walker         1149                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst              33207                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data             280995                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8262                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2861833                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        508133                       # Number of read requests accepted
+system.physmem.writeReqs                       442708                       # Number of write requests accepted
+system.physmem.readBursts                      508133                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     442708                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 32496192                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     24320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  28331264                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  32520512                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               28333312                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      380                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      16                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         172464                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               28425                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               32222                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               31678                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               29785                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               32093                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               37258                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               31249                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               31793                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               30380                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               34315                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              33552                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              33985                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              32112                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              32580                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28200                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28126                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               25043                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               27380                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               27369                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               27020                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               28395                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               31777                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               27205                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               28447                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               27006                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               30006                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              27888                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              28964                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              27392                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              28158                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              25051                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              25575                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51396578546000                       # Total gap between requests
+system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51277388057000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  833134                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  508133                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 737289                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    571213                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    169334                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     57100                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     32959                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       346                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       206                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       225                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       433                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       161                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      140                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       83                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       50                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       46                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       42                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       42                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       39                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 442708                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    359636                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     94580                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     31194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     18770                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       422                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       374                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       374                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       769                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       482                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       231                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      260                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       98                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       77                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       75                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       68                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       60                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       48                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -198,186 +198,193 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       667                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      662                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      657                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      651                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     9918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    10640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    28561                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    34227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    40879                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    43831                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    44813                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    44612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    46135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    46247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    46174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    49387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    47038                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    46944                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    49392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    44847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    45364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    43267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      707                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       393907                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      255.102976                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     152.689482                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     290.846029                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         173695     44.10%     44.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        94994     24.12%     68.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        37135      9.43%     77.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        19371      4.92%     82.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15343      3.90%     86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         9742      2.47%     88.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8567      2.17%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         6531      1.66%     92.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        28529      7.24%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         393907                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         42633                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        19.534281                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev        9.731161                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-31            39808     93.37%     93.37% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-63            2621      6.15%     99.52% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-95             170      0.40%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-127             21      0.05%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-159             5      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::224-255             4      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-287             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::352-383             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::544-575             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::608-639             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           42633                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         42633                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.293270                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.880471                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        5.837851                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                31      0.07%      0.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.02%      0.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               18      0.04%      0.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              54      0.13%      0.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           40522     95.05%     95.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             728      1.71%     97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             202      0.47%     97.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             312      0.73%     98.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              57      0.13%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             185      0.43%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              71      0.17%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              15      0.04%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              39      0.09%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              54      0.13%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              14      0.03%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              19      0.04%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             210      0.49%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              11      0.03%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               9      0.02%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              44      0.10%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            11      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           42633                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    19475290366                       # Total ticks spent queuing
-system.physmem.totMemAccLat               35091134116                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4164225000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       23384.05                       # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::0                       597                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       588                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       570                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       563                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      551                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      551                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     7362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     8022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    18082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    21480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    24501                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    25734                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    26594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    26643                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    27137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    27291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    27367                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    29561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    27445                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    27298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    29173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    25766                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    25736                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    24591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       46                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       256507                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      237.135361                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     143.751053                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     277.773032                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         118370     46.15%     46.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        63779     24.86%     71.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        23560      9.18%     80.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        11879      4.63%     84.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         8772      3.42%     88.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         5502      2.14%     90.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4497      1.75%     92.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3462      1.35%     93.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16686      6.51%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         256507                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         24650                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.597972                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       13.431676                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-31            22290     90.43%     90.43% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-63            2167      8.79%     99.22% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-95             156      0.63%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::96-127             17      0.07%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-159             6      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::160-191             3      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::192-223             1      0.00%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::224-255             2      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-287             2      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::320-351             1      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::416-447             1      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::448-479             1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::544-575             1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::640-671             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::672-703             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           24650                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         24650                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.958458                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.276383                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.669540                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                25      0.10%      0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                12      0.05%      0.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               19      0.08%      0.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              47      0.19%      0.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           22852     92.71%     93.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             503      2.04%     95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             178      0.72%     95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             262      1.06%     96.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              56      0.23%     97.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             180      0.73%     97.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              74      0.30%     98.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              10      0.04%     98.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              29      0.12%     98.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              72      0.29%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              15      0.06%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              17      0.07%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             194      0.79%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.02%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              14      0.06%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              52      0.21%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               7      0.03%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           24650                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10544434255                       # Total ticks spent queuing
+system.physmem.totMemAccLat               20064803005                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2538765000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20766.86                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  42134.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.04                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.92                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.04                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.92                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39516.86                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.63                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.55                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.63                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.55                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        13.53                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     652462                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    523738                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   78.34                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.04                       # Row buffer hit rate for writes
-system.physmem.avgGap                     32727856.47                       # Average gap between requests
-system.physmem.pageHitRate                      74.91                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1529501400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  832833375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3285765600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               2429740800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3315984618960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1212289072380                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29739570673500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34275922206015                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.648127                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   48905170971226                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1695288660000                       # Time in different power states
+system.physmem.avgWrQLen                        12.69                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     386701                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    307219                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.16                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  69.40                       # Row buffer hit rate for writes
+system.physmem.avgGap                     53928457.08                       # Average gap between requests
+system.physmem.pageHitRate                      73.01                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  977757480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  531832125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1985068800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               1442681280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3310425549600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1177046851320                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           30704731659000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             35197141399605                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              665.410484                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   48872276305390                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1692446600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    169075280274                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    119675759110                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1448412840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  788411250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3210347400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               2347729920                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3315984618960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1209778712865                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29729309949000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34262868182235                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.663987                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   48908958102968                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1695288660000                       # Time in different power states
+system.physmem_1.actEnergy                  961435440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  522856125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1975334400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               1425859200                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3310425549600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1177208679735                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29690763244500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34183282959000                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              667.568308                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   48872046794911                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1692446600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    165299992532                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    119910447839                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -437,47 +444,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   119866                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               119866                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples       119866                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         119866    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       119866                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 379345082112                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.652647                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -247578241138    -65.26%    -65.26% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1   626923323250    165.26%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 379345082112                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        88729     84.84%     84.84% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        15861     15.16%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       104590                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       119866                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    90321                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong                90321                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples        90321                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          90321    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        90321                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 389002628992                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.524259                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -203938078758    -52.43%    -52.43% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1   592940707750    152.43%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 389002628992                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        65935     84.97%     84.97% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        11661     15.03%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        77596                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90321                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       119866                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       104590                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90321                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        77596                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       104590                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       224456                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        77596                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       167917                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    75642766                       # DTB read hits
-system.cpu0.dtb.read_misses                     89640                       # DTB read misses
-system.cpu0.dtb.write_hits                   69609144                       # DTB write hits
-system.cpu0.dtb.write_misses                    30226                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1263                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    64849168                       # DTB read hits
+system.cpu0.dtb.read_misses                     68465                       # DTB read misses
+system.cpu0.dtb.write_hits                   59113138                       # DTB write hits
+system.cpu0.dtb.write_misses                    21856                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1195                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              20153                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    452                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   47006                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              16233                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    380                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   40748                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  3911                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  2820                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     8593                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                75732406                       # DTB read accesses
-system.cpu0.dtb.write_accesses               69639370                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     7506                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                64917633                       # DTB read accesses
+system.cpu0.dtb.write_accesses               59134994                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        145251910                       # DTB hits
-system.cpu0.dtb.misses                         119866                       # DTB misses
-system.cpu0.dtb.accesses                    145371776                       # DTB accesses
+system.cpu0.dtb.hits                        123962306                       # DTB hits
+system.cpu0.dtb.misses                          90321                       # DTB misses
+system.cpu0.dtb.accesses                    124052627                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -507,697 +514,699 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    57950                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                57950                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples        57950                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          57950    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        57950                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 379345082112                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.652788                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -247631753638    -65.28%    -65.28% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   626976835750    165.28%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 379345082112                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        50452     94.94%     94.94% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2688      5.06%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        53140                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    53302                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                53302                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        53302                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          53302    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        53302                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 389002628992                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.524352                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -203974223258    -52.44%    -52.44% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   592976852250    152.44%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 389002628992                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        46280     94.90%     94.90% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2485      5.10%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        48765                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57950                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57950                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53302                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53302                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        53140                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        53140                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       111090                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   405381622                       # ITB inst hits
-system.cpu0.itb.inst_misses                     57950                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        48765                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        48765                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       102067                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   346354960                       # ITB inst hits
+system.cpu0.itb.inst_misses                     53302                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1263                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1195                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              20153                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    452                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   33228                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              16233                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    380                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   28697                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               405439572                       # ITB inst accesses
-system.cpu0.itb.hits                        405381622                       # DTB hits
-system.cpu0.itb.misses                          57950                       # DTB misses
-system.cpu0.itb.accesses                    405439572                       # DTB accesses
-system.cpu0.numCycles                       487302102                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               346408262                       # ITB inst accesses
+system.cpu0.itb.hits                        346354960                       # DTB hits
+system.cpu0.itb.misses                          53302                       # DTB misses
+system.cpu0.itb.accesses                    346408262                       # DTB accesses
+system.cpu0.numCycles                       417857825                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   17144                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  405220560                       # Number of instructions committed
-system.cpu0.committedOps                    476699664                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            436776878                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                371179                       # Number of float alu accesses
-system.cpu0.num_func_calls                   23615839                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     62442452                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   436776878                       # number of integer instructions
-system.cpu0.num_fp_insts                       371179                       # number of float instructions
-system.cpu0.num_int_register_reads          647764481                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         347118708                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              591811                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             329388                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           109017876                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          108807189                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    145355316                       # number of memory refs
-system.cpu0.num_load_insts                   75721514                       # Number of load instructions
-system.cpu0.num_store_insts                  69633802                       # Number of store instructions
-system.cpu0.num_idle_cycles              473916691.596574                       # Number of idle cycles
-system.cpu0.num_busy_cycles              13385410.403426                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.027468                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.972532                       # Percentage of idle cycles
-system.cpu0.Branches                         90584626                       # Number of branches fetched
+system.cpu0.kern.inst.quiesce                   16514                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  346212347                       # Number of instructions committed
+system.cpu0.committedOps                    407289562                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            374196807                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                371114                       # Number of float alu accesses
+system.cpu0.num_func_calls                   20959157                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     52529410                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   374196807                       # number of integer instructions
+system.cpu0.num_fp_insts                       371114                       # number of float instructions
+system.cpu0.num_int_register_reads          546236459                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         297045333                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              596552                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             319604                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads            90150585                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           89913729                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    124035099                       # number of memory refs
+system.cpu0.num_load_insts                   64906131                       # Number of load instructions
+system.cpu0.num_store_insts                  59128968                       # Number of store instructions
+system.cpu0.num_idle_cycles              408498118.041102                       # Number of idle cycles
+system.cpu0.num_busy_cycles              9359706.958898                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.022399                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.977601                       # Percentage of idle cycles
+system.cpu0.Branches                         77291806                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                330567149     69.31%     69.31% # Class of executed instruction
-system.cpu0.op_class::IntMult                  941893      0.20%     69.51% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    42225      0.01%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             50408      0.01%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
-system.cpu0.op_class::MemRead                75721514     15.88%     85.40% # Class of executed instruction
-system.cpu0.op_class::MemWrite               69633802     14.60%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                282487625     69.32%     69.32% # Class of executed instruction
+system.cpu0.op_class::IntMult                  909497      0.22%     69.54% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    41524      0.01%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             50320      0.01%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.56% # Class of executed instruction
+system.cpu0.op_class::MemRead                64906131     15.93%     85.49% # Class of executed instruction
+system.cpu0.op_class::MemWrite               59128968     14.51%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 476956991                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements         11638567                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999719                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          335736078                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         11639079                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.845588                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 407524065                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          9647883                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999717                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          292725890                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9648395                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.339335                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.702275                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     7.106923                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.404077                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data     5.786443                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.964262                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.013881                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010555                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.011302                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.728369                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     5.127427                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     4.702216                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data     4.441704                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.972126                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.010015                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.009184                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data     0.008675                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1427343443                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1427343443                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     70546993                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     21833087                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data     29621653                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data     49726137                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      171727870                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     65848513                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     20323574                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data     26400594                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data     41881288                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     154453969                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       178125                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        52842                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        85285                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data       124641                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       440893                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       129363                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data        44707                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu2.data        62671                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu3.data        98791                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       335532                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1762005                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       548820                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       697386                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data      1176730                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      4184941                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1865727                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       590771                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data       751156                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1333509                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4541163                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    136395506                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     42156661                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data     56022247                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     91607425                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       326181839                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    136573631                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     42209503                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data     56107532                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     91732066                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      326622732                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2475648                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       760979                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data      1254924                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data      3959185                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      8450736                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1073288                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       320657                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       740390                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      4437299                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      6571634                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       641779                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       196644                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       265541                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data       463204                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1567168                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       696374                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       111936                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu2.data       158316                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu3.data       281973                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1248599                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       104417                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        42188                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        54084                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       202888                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       403577                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3548936                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      1081636                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1995314                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      8396484                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      15022370                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4190715                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1278280                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      2260855                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      8859688                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     16589538                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  13138449000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  22320104000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  72359917000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 107818470000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  15766909000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  37704242500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 250636765802                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 304107917302                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   4487202500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   6834071500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  13735050622                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  25056324622                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    652172000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    880917500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2926113500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4459203000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data        97500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        97500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  28905358000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  60024346500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 322996682802                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 411926387302                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  28905358000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  60024346500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 322996682802                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 411926387302                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     73022641                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     22594066                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data     30876577                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data     53685322                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::cpu0.data     66921801                       # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::cpu3.data     46318587                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    161025603                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       819904                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       249486                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       350826                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       587845                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      2008061                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       825737                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       156643                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       220987                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       380764                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1584131                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1866422                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       591008                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       751470                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1379618                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4588518                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1865729                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       590771                       # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1333511                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4541167                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    139944442                       # number of demand (read+write) accesses
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-system.cpu0.dcache.demand_accesses::cpu3.data    100003909                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    341204209                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    140764346                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     43487783                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data     58368387                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data    100591754                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    343212270                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033902                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033680                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.040643                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.073748                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.046902                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016038                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015533                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.027279                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.095800                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.040811                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.782749                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.788197                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.756902                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.787970                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.780438                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.843336                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.714593                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.716404                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.740545                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788192                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055945                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.071383                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.071971                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.147061                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.087954                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.tags.tag_accesses       1240366941                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1240366941                       # Number of data accesses
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+system.cpu0.dcache.SoftPFReq_hits::cpu3.data       112922                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       395957                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       126545                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data        46445                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu2.data        59725                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu3.data        96822                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       329537                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1458264                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       430071                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       571691                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       929686                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3389712                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1549495                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       467643                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data       621749                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1067526                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      3706413                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    116581423                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     36282031                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data     49173047                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu3.data     82824240                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       284860741                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    116740529                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     36328998                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data     49250009                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu3.data     82937162                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      285256698                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2044900                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       654690                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       963514                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu3.data      3438861                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      7101965                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       845622                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       251190                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       604459                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data      3442356                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      5143627                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       463462                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       145087                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data       209925                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu3.data       351338                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1169812                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       687578                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       110622                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu2.data       150083                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu3.data       277319                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1225602                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        91969                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        37784                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        50321                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       176189                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       356263                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu3.data            1                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2890522                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       905880                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1567973                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data      6881217                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      12245592                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3353984                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      1050967                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1777898                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data      7232555                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     13415404                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  10730358500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  16517281500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  60662755500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  87910395500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9179104000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22761343000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 115052000035                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 146992447035                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   3717932000                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   5375214500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  11073619157                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  20166765657                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    535758000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    751006000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2342018000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3628782000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data        84500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total        84500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  19909462500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  39278624500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data 175714755535                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 234902842535                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  19909462500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  39278624500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data 175714755535                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 234902842535                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     62723063                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     19575168                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data     26949763                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data     48382198                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    157630192                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     56748882                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     17612743                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data     23791257                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data     41323259                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    139476141                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       622568                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       192054                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       286887                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       464260                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1565769                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       814123                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       157067                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       209808                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       374141                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1555139                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1550233                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       467855                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       622012                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1105875                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      3745975                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1549496                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       467643                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       621749                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1067527                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      3706415                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    119471945                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     37187911                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data     50741020                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data     89705457                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    297106333                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    120094513                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     37379965                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data     51027907                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data     90169717                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    298672102                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032602                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033445                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.035752                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071077                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.045055                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014901                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014262                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.025407                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.083303                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.036878                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.744436                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.755449                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.731734                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.756770                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747117                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.844563                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.704298                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.715335                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.741215                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788098                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059326                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.080760                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.080900                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.159321                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095106                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025360                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025016                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.034392                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.083962                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.044028                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029771                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.029394                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.038734                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.088076                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.048336                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17265.192601                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17786.020508                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18276.467758                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12758.470978                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 49170.637161                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 50924.840287                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 56484.083178                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 46275.845140                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40087.215016                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 43167.282524                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 48710.517042                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20067.551409                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15458.708638                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16287.950226                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14422.309353                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11049.200029                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        48750                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        24375                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26723.738855                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30082.656915                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 38468.087690                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 27420.865503                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22612.696749                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26549.401222                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 36456.891349                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 24830.491802                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     26241707                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        45127                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          1118476                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            412                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.462021                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   109.531553                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024194                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024360                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.030901                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.076709                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.041216                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027928                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028116                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.034842                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.080210                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.044917                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16389.983809                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17142.751948                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17640.362754                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12378.320014                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36542.473825                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37655.726857                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33422.458350                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 28577.586795                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 33609.336298                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 35814.945730                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 39930.978970                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16454.579592                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14179.493966                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14924.305956                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13292.645965                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10185.683049                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        84500                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        42250                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21978.035170                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25050.574532                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25535.418449                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19182.644868                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18943.946385                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22092.732260                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24294.976745                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17509.934292                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     14425372                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        42395                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           882588                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            392                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.344401                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   108.150510                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8924778                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8924778                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3070                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       177170                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      2166772                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      2347012                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4945                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       329293                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      3711119                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      4045357                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           29                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2101                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         2130                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8861                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        11403                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       125299                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       145563                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         8015                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       506463                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      5877891                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      6392369                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         8015                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       506463                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      5877891                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      6392369                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       757909                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      1077754                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1792413                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3628076                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       315712                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       411097                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       726180                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1452989                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       196254                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       262805                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       454839                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       913898                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       111936                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       158287                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       279872                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       550095                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        33327                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        42681                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        77589                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       153597                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      1073621                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      1488851                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data      2518593                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      5081065                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1269875                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      1751656                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data      2973432                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5994963                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         7202                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6366                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         6575                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20143                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         6701                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         5973                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6301                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18975                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        13903                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        12339                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        12876                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39118                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  12177566500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  17778974500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  32248588000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  62205129000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  15233797500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  19851845000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  42775170792                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  77860813292                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3503817000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   5256863500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   8318157000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17078837500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   4375266500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   6674550500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  13332028122                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24381845122                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    465254000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    623794000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data   1175051500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2264099500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data        95500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        95500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  27411364000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  37630819500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  75023758792                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 140065942292                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  30915181000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  42887683000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  83341915792                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 157144779792                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1347374000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1179541000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1196510000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3723425000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1281429000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1132115000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1164905963                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3578449963                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2628803000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2311656000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2361415963                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7301874963                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033545                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.034905                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.033387                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.020136                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015293                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015147                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.015678                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009023                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.786633                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.749104                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.773740                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.455115                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.714593                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.716273                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.735027                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.347253                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056390                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.056797                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.056239                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.033474                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.writebacks::writebacks      7475106                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7475106                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3650                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       124312                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1904102                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      2032064                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4908                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       268057                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2861568                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3134533                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           28                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2036                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         2064                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8313                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10472                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       108224                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       127009                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         8558                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       392369                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      4765670                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      5166597                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         8558                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       392369                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      4765670                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      5166597                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       651040                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       839202                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1534759                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3025001                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       246282                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       336402                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       580788                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1163472                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       144706                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       207290                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       344141                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       696137                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       110622                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       150055                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       275283                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       535960                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        29471                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        39849                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        67965                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137285                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            1                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       897322                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      1175604                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data      2115547                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4188473                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1042028                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      1382894                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data      2459688                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4884610                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6832                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6962                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         7151                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20945                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         6305                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         6510                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6865                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19680                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        13137                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        13472                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        14016                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40625                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9843427000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  13182169000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26527501500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49553097500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   8718556000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  12098346000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  21094064660                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  41910966660                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3026616000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   4207308500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   6719819000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13953743500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   3607310000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   5223957500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  10676266657                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  19507534157                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    382668000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    527867500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    968982000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1879517500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data        83500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        83500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  18561983000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  25280515000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  47621566160                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  91464064160                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  21588599000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  29487823500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  54341385160                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 105417807660                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1349798500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1371763500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1366987000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4088549000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1281894000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1318427500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1339823955                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3940145455                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2631692500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2690191000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2706810955                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   8028694455                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033258                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031139                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031722                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019190                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013983                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014140                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014055                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008342                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.753465                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.722549                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.741268                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.444598                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.704298                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.715202                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.735773                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.344638                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062992                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.064065                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.061458                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036649                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024830                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.025662                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.025185                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.014892                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.029201                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.030010                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.029559                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.017467                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16067.320087                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16496.319661                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17991.717311                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17145.486754                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48252.196622                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48289.929141                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 58904.363645                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53586.650203                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17853.480693                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20002.905196                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 18288.134922                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18687.903355                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39087.215016                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 42167.395301                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 47636.162682                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 44322.971709                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13960.272452                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14615.262060                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15144.563018                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14740.519021                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        47750                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        47750                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25531.695077                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25275.074202                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 29787.964467                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27566.256738                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24345.058372                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 24484.078495                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28028.862201                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26212.802280                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187083.310192                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 185287.621740                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 181978.707224                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184849.575535                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191229.517982                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 189538.757743                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 184876.362958                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188587.613333                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189081.708984                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 187345.489910                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 183396.704178                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186662.788563                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024129                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023169                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023583                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.014098                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027877                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027101                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027278                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.016354                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.542578                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15707.980915                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17284.473654                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16381.183841                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35400.703259                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35963.953841                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36319.732260                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36022.325127                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20915.622020                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20296.726808                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19526.354023                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20044.536492                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 32609.336298                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 34813.618340                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 38782.876738                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36397.369500                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12984.561094                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13246.693769                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14257.073494                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13690.625341                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        83500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        83500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20685.977832                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21504.277801                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22510.285122                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21837.090548                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20717.868426                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21323.270981                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22092.795981                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21581.622209                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197570.038056                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197035.837403                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 191160.257307                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195204.058248                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203313.877875                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202523.425499                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 195167.364166                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200210.643039                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 200326.748877                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 199687.574228                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 193122.927725                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 197629.401969                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         16734603                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.971494                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          650477960                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16735115                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            38.869046                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      11779377500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   475.687206                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     5.486973                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    23.054415                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst     7.742900                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.929077                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.010717                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.045028                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.015123                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         15696881                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.971340                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          558297724                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         15697393                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.566270                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      11785355500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   478.712705                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     4.090332                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    22.639696                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst     6.528608                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.934986                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.007989                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.044218                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.012751                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999944                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        684306607                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       684306607                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    399406332                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    123839702                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     74645872                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst     52586054                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      650477960                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    399406332                       # number of demand (read+write) hits
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-system.cpu0.icache.demand_hits::total       650477960                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    399406332                       # number of overall hits
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-system.cpu0.icache.overall_hits::total      650477960                       # number of overall hits
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-system.cpu0.icache.ReadReq_misses::total     17093519                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6028430                       # number of demand (read+write) misses
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-system.cpu0.icache.demand_misses::total      17093519                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6028430                       # number of overall misses
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-system.cpu0.icache.overall_misses::total     17093519                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  24303980500                       # number of ReadReq miss cycles
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-system.cpu0.icache.ReadReq_miss_latency::total 150732944810                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  24303980500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  57538187500                       # number of demand (read+write) miss cycles
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-system.cpu0.icache.demand_miss_latency::total 150732944810                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  24303980500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  57538187500                       # number of overall miss cycles
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-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014869                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014395                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.052858                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.088261                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.025606                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014869                       # miss rate for demand accesses
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-system.cpu0.icache.demand_miss_rate::total     0.025606                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014869                       # miss rate for overall accesses
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-system.cpu0.icache.overall_miss_rate::total     0.025606                       # miss rate for overall accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13533.020928                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8818.134219                       # average ReadReq miss latency
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-system.cpu0.icache.overall_avg_miss_latency::total  8818.134219                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        66163                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        590046663                       # Number of tag accesses
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+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016154                       # miss rate for overall accesses
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+system.cpu0.icache.overall_miss_rate::total     0.027947                       # miss rate for overall accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13505.176060                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8854.142441                       # average ReadReq miss latency
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+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13505.176060                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8854.142441                       # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13730.909009                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13505.176060                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8854.142441                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        61485                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             3838                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             3700                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.238927                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.617568                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       358390                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       358390                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst       358390                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       358390                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst       358390                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       358390                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1808723                       # number of ReadReq MSHR misses
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-system.cpu0.icache.ReadReq_mshr_misses::total     10706699                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1808723                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst      4165797                       # number of demand (read+write) MSHR misses
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-system.cpu0.icache.demand_mshr_misses::total     10706699                       # number of demand (read+write) MSHR misses
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-system.cpu0.icache.overall_mshr_misses::cpu3.inst      4732179                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     10706699                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  22495257500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  53372390500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  60789325843                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 136656973843                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  22495257500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  53372390500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  60789325843                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 136656973843                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  22495257500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  53372390500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  60789325843                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 136656973843                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014395                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.052858                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.082047                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016038                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014395                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.052858                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.082047                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.016038                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014395                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.052858                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.082047                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.016038                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12437.093740                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12812.047851                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12845.948102                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12763.688775                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12437.093740                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12812.047851                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12845.948102                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12763.688775                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12437.093740                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12812.047851                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12845.948102                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12763.688775                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks     15696881                       # number of writebacks
+system.cpu0.icache.writebacks::total         15696881                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       354021                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       354021                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst       354021                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       354021                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst       354021                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       354021                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1686311                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3834374                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4581067                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     10101752                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      1686311                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst      3834374                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst      4581067                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     10101752                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      1686311                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst      3834374                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst      4581067                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     10101752                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21137106500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48815066500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  58829212841                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 128781385841                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21137106500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48815066500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  58829212841                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 128781385841                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21137106500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48815066500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  58829212841                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 128781385841                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017588                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017588                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017588                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12748.420852                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12748.420852                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12748.420852                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1228,69 +1237,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    42213                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong                42213                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         6241                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        31075                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        42204                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.853000                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev   141.748477                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047        42202    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::6144-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    31728                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                31728                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4579                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        23199                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        31723                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.882640                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev   157.206647                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-2047        31722    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        42204                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        37325                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 26882.732753                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 23412.636165                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 18338.779624                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        37004     99.14%     99.14% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071            2      0.01%     99.15% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          275      0.74%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143            7      0.02%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           19      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215            6      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            7      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::total        31723                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        27783                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 25230.482669                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21865.634493                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 16058.224156                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        27633     99.46%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.46% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          123      0.44%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143            5      0.02%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           12      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        37325                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   2908388356                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.649897                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.477002                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1018236500     35.01%     35.01% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     1890151856     64.99%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   2908388356                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        31075     83.28%     83.28% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         6241     16.72%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        37316                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        42213                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total        27783                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   2741941428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.632141                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.482223                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1008648500     36.79%     36.79% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     1733292928     63.21%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   2741941428                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        23199     83.52%     83.52% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         4579     16.48%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        27778                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31728                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        42213                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        37316                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31728                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27778                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        37316                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        79529                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27778                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        59506                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    23441762                       # DTB read hits
-system.cpu1.dtb.read_misses                     32033                       # DTB read misses
-system.cpu1.dtb.write_hits                   21401339                       # DTB write hits
-system.cpu1.dtb.write_misses                    10180                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1255                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    20241909                       # DTB read hits
+system.cpu1.dtb.read_misses                     24578                       # DTB read misses
+system.cpu1.dtb.write_hits                   18246308                       # DTB write hits
+system.cpu1.dtb.write_misses                     7150                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               6610                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    146                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   20769                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid               5242                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   17924                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1303                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   956                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     2968                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                23473795                       # DTB read accesses
-system.cpu1.dtb.write_accesses               21411519                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     2537                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                20266487                       # DTB read accesses
+system.cpu1.dtb.write_accesses               18253458                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         44843101                       # DTB hits
-system.cpu1.dtb.misses                          42213                       # DTB misses
-system.cpu1.dtb.accesses                     44885314                       # DTB accesses
+system.cpu1.dtb.hits                         38488217                       # DTB hits
+system.cpu1.dtb.misses                          31728                       # DTB misses
+system.cpu1.dtb.accesses                     38519945                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1320,131 +1327,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    21791                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                21791                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1072                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        19067                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        21791                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          21791    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        21791                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        20139                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 29400.094344                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25404.974001                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 23277.059653                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        19797     98.30%     98.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          293      1.45%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143            9      0.04%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           20      0.10%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.07%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        20139                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    20290                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                20290                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          971                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17908                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        20290                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          20290    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        20290                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        18879                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28298.930028                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25145.287562                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 17574.390852                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        18719     99.15%     99.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          141      0.75%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143            3      0.02%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679            8      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215            3      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        18879                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        19067     94.68%     94.68% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         1072      5.32%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        20139                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        17908     94.86%     94.86% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          971      5.14%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        18879                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        21791                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        21791                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20290                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20290                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        20139                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        20139                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        41930                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   125648425                       # ITB inst hits
-system.cpu1.itb.inst_misses                     21791                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18879                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18879                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        39169                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   107574480                       # ITB inst hits
+system.cpu1.itb.inst_misses                     20290                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1255                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               6610                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    146                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   15047                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid               5242                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   13368                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               125670216                       # ITB inst accesses
-system.cpu1.itb.hits                        125648425                       # DTB hits
-system.cpu1.itb.misses                          21791                       # DTB misses
-system.cpu1.itb.accesses                    125670216                       # DTB accesses
-system.cpu1.numCycles                      1254117353                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               107594770                       # ITB inst accesses
+system.cpu1.itb.hits                        107574480                       # DTB hits
+system.cpu1.itb.misses                          20290                       # DTB misses
+system.cpu1.itb.accesses                    107594770                       # DTB accesses
+system.cpu1.numCycles                      1186092617                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  125557631                       # Number of instructions committed
-system.cpu1.committedOps                    147479999                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            135255426                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                113335                       # Number of float alu accesses
-system.cpu1.num_func_calls                    7243553                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     19326205                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   135255426                       # number of integer instructions
-system.cpu1.num_fp_insts                       113335                       # number of float instructions
-system.cpu1.num_int_register_reads          197658337                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         107430286                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              186014                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              88856                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            33354822                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           33290251                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     44840861                       # number of memory refs
-system.cpu1.num_load_insts                   23441337                       # Number of load instructions
-system.cpu1.num_store_insts                  21399524                       # Number of store instructions
-system.cpu1.num_idle_cycles              1222996834.683689                       # Number of idle cycles
-system.cpu1.num_busy_cycles              31120518.316311                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.024815                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.975185                       # Percentage of idle cycles
-system.cpu1.Branches                         28029112                       # Number of branches fetched
+system.cpu1.committedInsts                  107495721                       # Number of instructions committed
+system.cpu1.committedOps                    126075283                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            115907756                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                113126                       # Number of float alu accesses
+system.cpu1.num_func_calls                    6382091                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     16276077                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   115907756                       # number of integer instructions
+system.cpu1.num_fp_insts                       113126                       # number of float instructions
+system.cpu1.num_int_register_reads          166908100                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          91871167                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              184275                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              91240                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            27698310                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27628060                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     38485648                       # number of memory refs
+system.cpu1.num_load_insts                   20241154                       # Number of load instructions
+system.cpu1.num_store_insts                  18244494                       # Number of store instructions
+system.cpu1.num_idle_cycles              1161627733.273481                       # Number of idle cycles
+system.cpu1.num_busy_cycles              24464883.726519                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.020626                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.979374                       # Percentage of idle cycles
+system.cpu1.Branches                         23916118                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                102409853     69.40%     69.40% # Class of executed instruction
-system.cpu1.op_class::IntMult                  296498      0.20%     69.60% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    11247      0.01%     69.61% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             12292      0.01%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.61% # Class of executed instruction
-system.cpu1.op_class::MemRead                23441337     15.88%     85.50% # Class of executed instruction
-system.cpu1.op_class::MemWrite               21399524     14.50%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 87373708     69.26%     69.26% # Class of executed instruction
+system.cpu1.op_class::IntMult                  271273      0.22%     69.47% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    11107      0.01%     69.48% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             12264      0.01%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
+system.cpu1.op_class::MemRead                20241154     16.04%     85.54% # Class of executed instruction
+system.cpu1.op_class::MemWrite               18244494     14.46%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 147570793                       # Class of executed instruction
-system.cpu2.branchPred.lookups               45471146                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         31973875                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          2129408                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            32992156                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               23695609                       # Number of BTB hits
+system.cpu1.op_class::total                 126154042                       # Class of executed instruction
+system.cpu2.branchPred.lookups               39396533                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         27362101                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect          1971184                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            28599658                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               20206635                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            71.821948                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                5443991                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            364384                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            70.653415                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                4844874                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            318265                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1474,61 +1481,59 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                   113177                       # Table walker walks requested
-system.cpu2.dtb.walker.walksLong               113177                       # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         8706                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        39954                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples       113177                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0         113177    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total       113177                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples        48660                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 26968.937526                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 23542.983422                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 19014.556180                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-65535        48252     99.16%     99.16% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-196607          346      0.71%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-262143            8      0.02%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-327679           19      0.04%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::327680-393215            9      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::393216-458751           17      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::458752-524287            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::524288-589823            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total        48660                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walksPending::samples   2000225500                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::0     2000225500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::total   2000225500                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K        39954     82.11%     82.11% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M         8706     17.89%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total        48660                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data       113177                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walks                    92743                       # Table walker walks requested
+system.cpu2.dtb.walker.walksLong                92743                       # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         6709                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        28755                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        92743                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          92743    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        92743                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples        35464                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 24952.261448                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 21836.970286                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 14872.403453                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-65535        35314     99.58%     99.58% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-196607          126      0.36%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-262143            2      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-327679           14      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::393216-458751            6      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total        35464                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples   2000224000                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0     2000224000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total   2000224000                       # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K        28755     81.08%     81.08% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M         6709     18.92%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total        35464                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        92743                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total       113177                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        48660                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        92743                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        35464                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        48660                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total       161837                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        35464                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total       128207                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    32304432                       # DTB read hits
-system.cpu2.dtb.read_misses                     94453                       # DTB read misses
-system.cpu2.dtb.write_hits                   28220489                       # DTB write hits
-system.cpu2.dtb.write_misses                    18724                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1254                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    28135338                       # DTB read hits
+system.cpu2.dtb.read_misses                     77405                       # DTB read misses
+system.cpu2.dtb.write_hits                   24723604                       # DTB write hits
+system.cpu2.dtb.write_misses                    15338                       # DTB write misses
+system.cpu2.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid               8683                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_mva_asid               6517                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                    195                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   25531                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      107                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  2547                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries                   22464                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                       74                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                  2032                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                     4198                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                32398885                       # DTB read accesses
-system.cpu2.dtb.write_accesses               28239213                       # DTB write accesses
+system.cpu2.dtb.perms_faults                     3778                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                28212743                       # DTB read accesses
+system.cpu2.dtb.write_accesses               24738942                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         60524921                       # DTB hits
-system.cpu2.dtb.misses                         113177                       # DTB misses
-system.cpu2.dtb.accesses                     60638098                       # DTB accesses
+system.cpu2.dtb.hits                         52858942                       # DTB hits
+system.cpu2.dtb.misses                          92743                       # DTB misses
+system.cpu2.dtb.accesses                     52951685                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1558,86 +1563,86 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                    29761                       # Table walker walks requested
-system.cpu2.itb.walker.walksLong                29761                       # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1942                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3        24191                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples        29761                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0          29761    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total        29761                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples        26133                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 29367.313359                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 25512.670377                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 21362.014142                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767        13922     53.27%     53.27% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535        11740     44.92%     98.20% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303            1      0.00%     98.20% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839          361      1.38%     99.58% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607           66      0.25%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375            4      0.02%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143            6      0.02%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911           20      0.08%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679            6      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::327680-360447            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::393216-425983            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total        26133                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks                    27058                       # Table walker walks requested
+system.cpu2.itb.walker.walksLong                27058                       # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1852                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22698                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples        27058                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0          27058    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total        27058                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples        24550                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 28387.494908                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 25558.389161                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 15951.956543                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767        12868     52.42%     52.42% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535        11496     46.83%     99.24% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839          141      0.57%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607           26      0.11%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375            3      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143            3      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911            4      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::294912-327679            5      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::393216-425983            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total        24550                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000197500                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000197500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000197500                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K        24191     92.57%     92.57% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M         1942      7.43%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total        26133                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K        22698     92.46%     92.46% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M         1852      7.54%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total        24550                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        29761                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total        29761                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27058                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27058                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        26133                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total        26133                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total        55894                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    78881959                       # ITB inst hits
-system.cpu2.itb.inst_misses                     29761                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24550                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24550                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total        51608                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    67882722                       # ITB inst hits
+system.cpu2.itb.inst_misses                     27058                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1254                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid               8683                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_mva_asid               6517                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                    195                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   18937                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                   16669                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                    67145                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                    53735                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                78911720                       # ITB inst accesses
-system.cpu2.itb.hits                         78881959                       # DTB hits
-system.cpu2.itb.misses                          29761                       # DTB misses
-system.cpu2.itb.accesses                     78911720                       # DTB accesses
-system.cpu2.numCycles                      7033284242                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                67909780                       # ITB inst accesses
+system.cpu2.itb.hits                         67882722                       # DTB hits
+system.cpu2.itb.misses                          27058                       # DTB misses
+system.cpu2.itb.accesses                     67909780                       # DTB accesses
+system.cpu2.numCycles                      6659969764                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                  166119965                       # Number of instructions committed
-system.cpu2.committedOps                    194630787                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                     16695727                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                     1592                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                 95760838731                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                             42.338585                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.023619                       # IPC: instructions per cycle
+system.cpu2.committedInsts                  144540812                       # Number of instructions committed
+system.cpu2.committedOps                    169698177                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                     13684727                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                     1569                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                 95895764240                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                             46.076742                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.021703                       # IPC: instructions per cycle
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                      311878847                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                     6721405395                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               81889340                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted         56169669                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect          3380866                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups            55493963                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits               40219158                       # Number of BTB hits
+system.cpu2.tickCycles                      269319044                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                     6390650720                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               73106797                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted         49433479                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect          3258695                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups            49334876                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits               35656978                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            72.474835                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS               10439836                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect            109057                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct            72.275398                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                9555620                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect            104634                       # Number of incorrect RAS predictions.
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1667,90 +1672,88 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.walks                   587832                       # Table walker walks requested
-system.cpu3.dtb.walker.walksLong               587832                       # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2        11030                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        61410                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore       367052                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples       220780                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean  2589.344596                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 16088.611072                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-65535       219110     99.24%     99.24% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-131071          781      0.35%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-196607          609      0.28%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-262143           97      0.04%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-327679          110      0.05%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-393215           29      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::393216-458751           21      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::458752-524287           18      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total       220780                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples       282413                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 23694.059764                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 19376.224176                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 20061.278653                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-65535       276792     98.01%     98.01% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3971      1.41%     99.42% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-196607         1088      0.39%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-262143          102      0.04%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-327679          289      0.10%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-393215           71      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-458751           75      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-524287           16      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total       282413                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -34655191100                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean    -0.302186                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -35339735100    101.98%    101.98% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7    378573500     -1.09%    100.88% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11    130659500     -0.38%    100.51% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15     81429500     -0.23%    100.27% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19     31558000     -0.09%    100.18% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23     16139000     -0.05%    100.13% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27     19404500     -0.06%    100.08% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31     22341500     -0.06%    100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35      4213500     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39       186000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43        24000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::44-47         5000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::48-51         6000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::52-55         2500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::56-59         1500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -34655191100                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K        61410     84.77%     84.77% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M        11030     15.23%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total        72440                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       587832                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walks                   494873                       # Table walker walks requested
+system.cpu3.dtb.walker.walksLong               494873                       # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8038                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        49628                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore       307549                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples       187324                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean  2356.267750                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 14281.156299                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-65535       186079     99.34%     99.34% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-131071          697      0.37%     99.71% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-196607          387      0.21%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-262143           69      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-327679           51      0.03%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-393215           11      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::393216-458751           12      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::458752-524287           14      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total       187324                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples       229131                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 22686.146789                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 18317.810397                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 18596.429018                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-65535       224486     97.97%     97.97% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3513      1.53%     99.51% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-196607          846      0.37%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-262143           43      0.02%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-327679          153      0.07%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-393215           48      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-458751           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-524287           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total       229131                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -24996742720                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean    -0.101724                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -25553833720    102.23%    102.23% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7    304691500     -1.22%    101.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11    107266500     -0.43%    100.58% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15     67844000     -0.27%    100.31% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19     24788500     -0.10%    100.21% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23     14749500     -0.06%    100.15% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27     13689000     -0.05%    100.10% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31     19439000     -0.08%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35      4284000     -0.02%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39       178500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43        52500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::44-47       105500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::48-51         2500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -24996742720                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K        49628     86.06%     86.06% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M         8038     13.94%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total        57666                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       494873                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       587832                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        72440                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       494873                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        57666                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        72440                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total       660272                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        57666                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total       552539                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                    65734744                       # DTB read hits
-system.cpu3.dtb.read_misses                    407673                       # DTB read misses
-system.cpu3.dtb.write_hits                   50830095                       # DTB write hits
-system.cpu3.dtb.write_misses                   180159                       # DTB write misses
-system.cpu3.dtb.flush_tlb                        1253                       # Number of times complete TLB was flushed
+system.cpu3.dtb.read_hits                    58275132                       # DTB read hits
+system.cpu3.dtb.read_misses                    338945                       # DTB read misses
+system.cpu3.dtb.write_hits                   45320334                       # DTB write hits
+system.cpu3.dtb.write_misses                   155928                       # DTB write misses
+system.cpu3.dtb.flush_tlb                        1185                       # Number of times complete TLB was flushed
 system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid              13974                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid                    340                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                   34753                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                       86                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                  6443                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_tlb_mva_asid              11379                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid                    309                       # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries                   30010                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                       82                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                  4724                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                    35079                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                66142417                       # DTB read accesses
-system.cpu3.dtb.write_accesses               51010254                       # DTB write accesses
+system.cpu3.dtb.perms_faults                    33145                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                58614077                       # DTB read accesses
+system.cpu3.dtb.write_accesses               45476262                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                        116564839                       # DTB hits
-system.cpu3.dtb.misses                         587832                       # DTB misses
-system.cpu3.dtb.accesses                    117152671                       # DTB accesses
+system.cpu3.dtb.hits                        103595466                       # DTB hits
+system.cpu3.dtb.misses                         494873                       # DTB misses
+system.cpu3.dtb.accesses                    104090339                       # DTB accesses
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1780,391 +1783,387 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.walks                    63234                       # Table walker walks requested
-system.cpu3.itb.walker.walksLong                63234                       # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2         2096                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3        42908                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore         8590                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples        54644                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  2021.164263                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 13009.185259                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-32767        53981     98.79%     98.79% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-65535          301      0.55%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-98303           60      0.11%     99.45% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::98304-131071           76      0.14%     99.59% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-163839          174      0.32%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::163840-196607           22      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-229375            8      0.01%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::262144-294911            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::294912-327679            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total        54644                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples        53594                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 30266.951524                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 25142.604210                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 25912.141235                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-65535        52174     97.35%     97.35% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-131071          327      0.61%     97.96% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::131072-196607          902      1.68%     99.64% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-262143           65      0.12%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-327679           86      0.16%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-393215           19      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::393216-458751           14      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::458752-524287            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::524288-589823            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total        53594                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -34657916600                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     0.961535                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev     0.183175                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0    -1283225616      3.70%      3.70% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1   -33417551984     96.42%    100.12% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2       37526500     -0.11%    100.02% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3        4293000     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         605000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5         220500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::6         216000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -34657916600                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K        42908     95.34%     95.34% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M         2096      4.66%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total        45004                       # Table walker page sizes translated
+system.cpu3.itb.walker.walks                    60079                       # Table walker walks requested
+system.cpu3.itb.walker.walksLong                60079                       # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1942                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3        41391                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore         8262                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples        51817                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1695.563232                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 10747.357060                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-65535        51612     99.60%     99.60% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-131071           80      0.15%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-196607          107      0.21%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-262143           10      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::262144-327679            7      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total        51817                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples        51595                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 29163.077818                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 24579.723425                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 21924.280551                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-32767        28123     54.51%     54.51% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-65535        22407     43.43%     97.94% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-98303          307      0.60%     98.53% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::98304-131071           32      0.06%     98.59% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::131072-163839          434      0.84%     99.43% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::163840-196607          175      0.34%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::196608-229375           23      0.04%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::229376-262143           26      0.05%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-294911           39      0.08%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::294912-327679           12      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-360447            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::393216-425983            9      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total        51595                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -33589148812                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     1.086684                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0     2957203824     -8.80%     -8.80% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1   -36586535136    108.92%    100.12% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2       35384500     -0.11%    100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3        4248500     -0.01%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4         527000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5          22500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -33589148812                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K        41391     95.52%     95.52% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M         1942      4.48%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total        43333                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        63234                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total        63234                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        60079                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total        60079                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        45004                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total        45004                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total       108238                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                    57820095                       # ITB inst hits
-system.cpu3.itb.inst_misses                     63234                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        43333                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total        43333                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total       103412                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                    52677682                       # ITB inst hits
+system.cpu3.itb.inst_misses                     60079                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
 system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.flush_tlb                        1253                       # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb                        1185                       # Number of times complete TLB was flushed
 system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid              13974                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid                    340                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                   26508                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_tlb_mva_asid              11379                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid                    309                       # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries                   23578                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                   125417                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                   114813                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                57883329                       # ITB inst accesses
-system.cpu3.itb.hits                         57820095                       # DTB hits
-system.cpu3.itb.misses                          63234                       # DTB misses
-system.cpu3.itb.accesses                     57883329                       # DTB accesses
-system.cpu3.numCycles                       434126905                       # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses                52737761                       # ITB inst accesses
+system.cpu3.itb.hits                         52677682                       # DTB hits
+system.cpu3.itb.misses                          60079                       # DTB misses
+system.cpu3.itb.accesses                     52737761                       # DTB accesses
+system.cpu3.numCycles                       367538464                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles         146156253                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                     363700570                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   81889340                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches          50658994                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                    264117346                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                7731870                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                   1657260                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles               10621                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles             2103                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles      3389024                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles       101744                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles         6028                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                 57676698                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes              2068277                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                  25207                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples         419306139                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.016419                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.270112                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles         137661230                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                     325116146                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   73106797                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches          45212598                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                    207107906                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                7385298                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                   1491112                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles                7917                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles             2707                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles      2935817                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        92613                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles         5851                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                 52545073                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes              2005603                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                  24026                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples         352997650                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.078283                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.326168                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0               329556532     78.60%     78.60% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                11088732      2.64%     81.24% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                11228658      2.68%     83.92% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 8092801      1.93%     85.85% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                18140495      4.33%     90.17% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                 5492721      1.31%     91.48% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 6039069      1.44%     92.92% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                 5230958      1.25%     94.17% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                24436173      5.83%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0               272813729     77.28%     77.28% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                10027908      2.84%     80.13% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                10164479      2.88%     83.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 7468497      2.12%     85.12% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                15406630      4.36%     89.49% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                 5031910      1.43%     90.91% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 5399943      1.53%     92.44% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                 4793152      1.36%     93.80% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                21891402      6.20%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total           419306139                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.188630                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.837775                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles               117967967                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles            225080995                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                 64189505                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles              9003410                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles               3062237                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved            11922856                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred               815112                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts             398264937                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts              2526332                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles               3062237                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles               122799246                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles               19956782                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles     172569750                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                 68252780                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles             32663221                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts             389247398                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                82681                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents               1469691                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents               1381042                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents              19259922                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents            2209                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands          374365889                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            605949673                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups       460740509                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups           465469                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps            317859037                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                56506847                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts          10256222                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts       9051847                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                 50890020                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads            62384560                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores           53396526                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          8272508                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         8814741                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                 368973435                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded           10287007                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                371458257                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued           527403                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined       47542551                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     30606523                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved        220793                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples    419306139                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.885888                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.625743                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total           352997650                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.198909                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.884577                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles               112522162                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles            171201406                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                 59221662                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles              7151544                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles               2899090                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved            10994019                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred               804734                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts             355281721                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts              2474096                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles               2899090                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles               116622448                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles               14081573                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles     135939902                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                 62181324                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles             21271328                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts             346993975                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                66296                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents               1234254                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                930282                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents              10943562                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents            2087                       # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands          331516858                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            531452942                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups       410096361                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups           485069                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps            278766720                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                52750133                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts           7968822                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts       6860328                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                 39681669                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads            56098818                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores           47638464                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          7335407                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         7944863                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                 329650835                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded            7964776                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                329496224                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued           469719                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined       44173010                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     28338373                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved        197137                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples    352997650                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.933423                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.659576                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0          272370865     64.96%     64.96% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1           63755387     15.20%     80.16% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2           26527410      6.33%     86.49% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3           18802792      4.48%     90.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4           14265193      3.40%     94.38% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5            9871415      2.35%     96.73% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6            6899561      1.65%     98.38% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7            4083667      0.97%     99.35% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8            2729849      0.65%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0          224922038     63.72%     63.72% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1           52868564     14.98%     78.69% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2           24171570      6.85%     85.54% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3           17197419      4.87%     90.41% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4           12806059      3.63%     94.04% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5            9032778      2.56%     96.60% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6            6064654      1.72%     98.32% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7            3560331      1.01%     99.33% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8            2374237      0.67%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total      419306139                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total      352997650                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                1874044     25.07%     25.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                 14207      0.19%     25.26% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                   1529      0.02%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.29% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead               3115796     41.69%     66.97% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite              2468334     33.03%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                1654999     25.37%     25.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                 15899      0.24%     25.61% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                   1445      0.02%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.63% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead               2663997     40.83%     66.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite              2188300     33.54%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass               19      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu            252023231     67.85%     67.85% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult              873366      0.24%     68.08% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                40952      0.01%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.09% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc         37311      0.01%     68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead            67010678     18.04%     86.14% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite           51472700     13.86%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu            223294743     67.77%     67.77% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult              773232      0.23%     68.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                39732      0.01%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.02% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc         41118      0.01%     68.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead            59435929     18.04%     86.07% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite           45911451     13.93%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total             371458257                       # Type of FU issued
-system.cpu3.iq.rate                          0.855644                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                    7473910                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.020120                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads        1169596628                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes        426913403                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses    357682131                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads             627338                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes            312499                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses       278370                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses             378596824                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                 335324                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads         2893628                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total             329496224                       # Type of FU issued
+system.cpu3.iq.rate                          0.896495                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                    6524640                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.019802                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads        1018336747                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes        381842202                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses    317599035                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads             647710                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes            321899                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses       289386                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses             335674602                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                 346243                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads         2638413                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      9605329                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses        12315                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation       430621                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores      5363996                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      8879523                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses        11866                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation       381459                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores      4873286                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads      2422339                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked      5589935                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads      2106312                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked      4209032                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles               3062237                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles               10687906                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles              7763233                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts          379342357                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts          1032736                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts             62384560                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts            53396526                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts           8880600                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                160790                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents              7539596                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents        430621                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect       1536012                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect      1351234                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts             2887246                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts            367483062                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts             65729081                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts          3395466                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles               2899090                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                8833562                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles              4011376                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts          337691030                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts           991613                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts             56098818                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts            47638464                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts           6709459                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                120203                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents              3844571                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents        381459                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect       1469292                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect      1295892                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts             2765184                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts            325759751                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts             58266124                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts          3247625                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        81915                       # number of nop insts executed
-system.cpu3.iew.exec_refs                   116559779                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                68181123                       # Number of branches executed
-system.cpu3.iew.exec_stores                  50830698                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.846488                       # Inst execution rate
-system.cpu3.iew.wb_sent                     358682036                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                    357960501                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                176824720                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                308531947                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        75419                       # number of nop insts executed
+system.cpu3.iew.exec_refs                   103584875                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                60432321                       # Number of branches executed
+system.cpu3.iew.exec_stores                  45318751                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.886328                       # Inst execution rate
+system.cpu3.iew.wb_sent                     318561323                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                    317888421                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                157110188                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                272714221                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      0.824553                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.573116                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      0.864912                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.576098                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts       47576745                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls       10066214                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts          2576993                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples    411229636                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.806649                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.806100                       # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts       44200110                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls        7767639                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts          2464984                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples    345475072                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.849389                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.847862                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0    288483917     70.15%     70.15% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1     61981955     15.07%     85.22% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2     20267968      4.93%     90.15% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      9217498      2.24%     92.39% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4      6652848      1.62%     94.01% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5      4003479      0.97%     94.99% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6      3757671      0.91%     95.90% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7      2541712      0.62%     96.52% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8     14322588      3.48%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0    238897207     69.15%     69.15% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1     51619563     14.94%     84.09% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2     18609130      5.39%     89.48% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      8398025      2.43%     91.91% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4      6043748      1.75%     93.66% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5      3655661      1.06%     94.72% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6      3455010      1.00%     95.72% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7      2146483      0.62%     96.34% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8     12650245      3.66%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total    411229636                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts           282128500                       # Number of instructions committed
-system.cpu3.commit.committedOps             331717886                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total    345475072                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts           249760952                       # Number of instructions committed
+system.cpu3.commit.committedOps             293442596                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                     100811760                       # Number of memory references committed
-system.cpu3.commit.loads                     52779230                       # Number of loads committed
-system.cpu3.commit.membars                    2341382                       # Number of memory barriers committed
-system.cpu3.commit.branches                  63187183                       # Number of branches committed
-system.cpu3.commit.fp_insts                    266447                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                304028105                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             8134067                       # Number of function calls committed.
+system.cpu3.commit.refs                      89984472                       # Number of memory references committed
+system.cpu3.commit.loads                     47219294                       # Number of loads committed
+system.cpu3.commit.membars                    1969895                       # Number of memory barriers committed
+system.cpu3.commit.branches                  55759591                       # Number of branches committed
+system.cpu3.commit.fp_insts                    278553                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                269644169                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             7403511                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu       230158153     69.38%     69.38% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult         685246      0.21%     69.59% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv           30654      0.01%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc        32073      0.01%     69.61% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.61% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.61% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.61% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead       52779230     15.91%     85.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite      48032530     14.48%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu       202786729     69.11%     69.11% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult         605783      0.21%     69.31% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv           30019      0.01%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.32% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc        35593      0.01%     69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.33% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead       47219294     16.09%     85.43% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite      42765178     14.57%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total        331717886                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events             14322588                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                   773873016                       # The number of ROB reads
-system.cpu3.rob.rob_writes                  766677768                       # The number of ROB writes
-system.cpu3.timesIdled                        2386400                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                       14820766                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                 98598665590                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                  282128500                       # Number of Instructions Simulated
-system.cpu3.committedOps                    331717886                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.538756                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.538756                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.649876                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.649876                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads               433777374                       # number of integer regfile reads
-system.cpu3.int_regfile_writes              254753352                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                   550692                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                  344140                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                 80727735                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                81413298                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads              763399482                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes              10252205                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40277                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40277                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136543                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136543                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47710                       # Packet count per connected master and slave (bytes)
+system.cpu3.commit.op_class_0::total        293442596                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events             12650245                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                   668392773                       # The number of ROB reads
+system.cpu3.rob.rob_writes                  682819370                       # The number of ROB writes
+system.cpu3.timesIdled                        2353613                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                       14540814                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                 98630935405                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                  249760952                       # Number of Instructions Simulated
+system.cpu3.committedOps                    293442596                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.471561                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.471561                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.679551                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.679551                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads               384013216                       # number of integer regfile reads
+system.cpu3.int_regfile_writes              227255326                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                   562445                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                  347476                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                 69354543                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                70004499                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads              654418825                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes               7814462                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40238                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40238                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136511                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136511                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47686                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2174,18 +2173,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29444                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122592                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230968                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230968                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122464                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353640                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47730                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353498                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47706                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2195,99 +2194,97 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155722                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334304                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334304                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155640                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492112                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             27944000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7491974                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             34324500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                 5500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                4000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy                5500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             9762000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            13360500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy               84000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              141000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            18725000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            21520500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               37000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               46500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           256543158                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           257733143                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               30500                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            57567000                       # Layer occupancy (ticks)
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 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
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 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
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 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
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 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
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 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
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 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8820                       # number of ReadReq misses
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 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
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-system.iocache.overall_misses::total             8860                       # number of overall misses
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-system.iocache.demand_miss_latency::total    731246845                       # number of demand (read+write) miss cycles
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 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8820                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8857                       # number of ReadReq accesses(hits+misses)
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 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8820                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8860                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8820                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8860                       # number of overall (read+write) accesses
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 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2301,503 +2298,506 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 82907.805556                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 82561.459298                       # average ReadReq miss latency
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-system.iocache.WriteLineReq_avg_miss_latency::total 58953.248641                       # average WriteLineReq miss latency
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-system.iocache.overall_avg_miss_latency::total 82533.503950                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         14483                       # number of cycles access was blocked
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+system.iocache.WriteLineReq_avg_miss_latency::total 58612.164451                       # average WriteLineReq miss latency
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+system.iocache.demand_avg_miss_latency::total 121846.519146                       # average overall miss latency
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+system.iocache.overall_avg_miss_latency::total 121846.519146                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         22659                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 1449                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 2381                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.995169                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.516590                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106630                       # number of writebacks
-system.iocache.writebacks::total               106630                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide         3943                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         3943                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        48464                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        48464                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         3943                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         3943                       # number of demand (read+write) MSHR misses
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-system.iocache.overall_mshr_misses::total         3943                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide    534096845                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    534096845                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3864989313                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3864989313                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide    534096845                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    534096845                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide    534096845                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    534096845                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.447052                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.445185                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.454361                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.454361                       # mshr miss rate for WriteLineReq accesses
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-system.iocache.demand_mshr_miss_rate::total     0.445034                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.447052                       # mshr miss rate for overall accesses
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-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135454.436977                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 135454.436977                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79749.696950                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79749.696950                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 135454.436977                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 135454.436977                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 135454.436977                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 135454.436977                       # average overall mshr miss latency
+system.iocache.writebacks::writebacks          106631                       # number of writebacks
+system.iocache.writebacks::total               106631                       # number of writebacks
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+system.iocache.ReadReq_mshr_miss_rate::total     0.646215                       # mshr miss rate for ReadReq accesses
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+system.iocache.WriteLineReq_mshr_miss_rate::total     0.450236                       # mshr miss rate for WriteLineReq accesses
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+system.iocache.demand_avg_mshr_miss_latency::realview.ide 138618.155971                       # average overall mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::total 138618.155971                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1727571                       # number of replacements
-system.l2c.tags.tagsinuse                65366.434127                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   52377191                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1790828                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    29.247472                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1137204                       # number of replacements
+system.l2c.tags.tagsinuse                65362.357170                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   47194222                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1199974                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    39.329370                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35675.383365                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   150.314968                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   221.842308                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3453.336849                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8628.573919                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    25.870351                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    46.456847                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      201.612441                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2287.318567                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    59.687727                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker    74.075629                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1384.134493                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3678.892327                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    90.341060                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.itb.walker   136.749974                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     2263.424269                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     6988.419034                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.544363                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002294                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003385                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.052694                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.131662                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000395                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000709                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.034902                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu2.itb.walker     0.001130                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.021120                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.056135                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001378                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.itb.walker     0.002087                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.034537                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.106635                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1023          271                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62986                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          271                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          557                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2824                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5088                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54403                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004135                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.961090                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                469232047                       # Number of tag accesses
-system.l2c.tags.data_accesses               469232047                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       235826                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       121184                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::total                1201753                       # number of ReadReq hits
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-system.l2c.Writeback_hits::total              8924778                       # number of Writeback hits
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-system.l2c.InvalidateReq_hits::cpu3.data       214200                       # number of InvalidateReq hits
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+system.l2c.ReadSharedReq_hits::total          6201904                       # number of ReadSharedReq hits
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-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.773056                       # miss rate for UpgradeReq accesses
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+system.l2c.ReadCleanReq_miss_latency::total   7558613999                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data   3626924000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data   5243614000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data  11147248500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  20017786500                       # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data   2479377500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu2.data   3669438500                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu3.data   7575573000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total  13724389000                       # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker     49999000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker     45195500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    942461000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   9543984500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker     52180000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.itb.walker     47605000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst   3002415000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data  13554354500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.dtb.walker    140767500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.itb.walker    128228000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst   3613737999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data  25498188500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     56619116499                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker     49999000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker     45195500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    942461000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   9543984500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker     52180000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.itb.walker     47605000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst   3002415000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data  13554354500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.dtb.walker    140767500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.itb.walker    128228000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst   3613737999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data  25498188500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    56619116499                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker       158170                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker       109277                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        57050                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker        42798                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker       148942                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker        57299                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.dtb.walker       286474                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.itb.walker       109434                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             969444                       # number of ReadReq accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks      7475106                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      7475106                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks     15694537                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total     15694537                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        17827                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5719                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data         7241                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data        12183                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           42970                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu3.data            1                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       827795                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       240563                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data       329220                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data       571155                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          1968733                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      5595707                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      1686311                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst      3834374                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst      4581002                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      15697394                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      2600331                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       825217                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data      1086282                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data      1944316                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      6456146                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       687578                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       110622                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu2.data       150055                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu3.data       275283                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1223538                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       158170                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       109277                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         5595707                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         3428126                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.inst         1686311                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         1065780                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker       148942                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker        57299                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst         3834374                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data         1415502                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker       286474                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker       109434                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst         4581002                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data         2515471                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            25091717                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       158170                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.inst        5595707                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.itb.walker        42798                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        1686311                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        1065780                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu2.itb.walker        57299                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst        3834374                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu3.itb.walker       109434                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total           25091717                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.006145                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784316                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783354                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.795470                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.778133                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.784315                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.500000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.750000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.347960                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.296542                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.293148                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.321628                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.325063                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006945                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.003588                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006553                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.006555                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.006375                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.047521                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.035283                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.040637                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.043775                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.043692                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.608985                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.224155                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu2.data     0.229741                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu3.data     0.234650                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.442216                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.012293                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.022418                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006945                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.121510                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.008810                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.015256                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.003588                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.097546                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.006174                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.014935                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.006553                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.097518                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.005114                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.itb.walker     0.014453                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.006555                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.109218                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.044845                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.012293                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.022418                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006945                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.121510                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.008810                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.015256                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.003588                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.097546                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.006174                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.014935                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.006553                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.097518                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.005114                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.itb.walker     0.014453                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.006555                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.109218                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.044845                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 134292.127072                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137647.142857                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 138700.922819                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 136037.194474                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 138444.444444                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 139405.421332                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 76138.255349                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 38006.094077                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 38558.065909                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 39033.488292                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 23104.518427                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131397.901159                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 132864.802280                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 154150.417161                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 78378.506853                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131453.775039                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133730.722737                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 136131.350741                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 81803.600555                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 133815.452615                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 135189.160099                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 140970.189942                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 76887.691711                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 131341.477024                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 140927.512718                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 157640.760141                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 34057.684109                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 134292.127072                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 137647.142857                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 131453.775039                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 132063.958913                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 138700.922819                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 136037.194474                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 133730.722737                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 133615.219152                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 138444.444444                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.itb.walker 139405.421332                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 136131.350741                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 150111.894143                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 78237.929960                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 134292.127072                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137647.142857                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 131453.775039                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 132063.958913                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 138700.922819                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 136037.194474                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 133730.722737                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 133615.219152                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 138444.444444                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.itb.walker 139405.421332                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 136131.350741                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 150111.894143                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 78237.929960                       # average overall miss latency
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data            1                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.220745                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.187913                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.190587                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.171036                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.197269                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006447                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004247                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.005859                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005808                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005880                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041967                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.033051                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.035730                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.040646                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.039380                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.575191                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.171783                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu2.data     0.176055                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu3.data     0.176822                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.400140                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006447                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.085137                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004247                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.068006                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.005859                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.071747                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.005808                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.070252                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.029527                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.006447                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.085137                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004247                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.068006                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.005859                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.071747                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.005808                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.070252                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.029527                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 77887.359409                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41235.825893                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 42800.781250                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 43269.989451                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 24967.909916                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130893.938724                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 132452.633676                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 146905.863566                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 73586.376394                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131591.873778                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133654.513889                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 135819.070132                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 81884.712040                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132981.007553                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 135099.425450                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141054.417422                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 78735.167675                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130472.951639                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 138899.178590                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 155632.611554                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total 28032.641865                       # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 131591.873778                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 131679.307110                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 133654.513889                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 133464.173182                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 135819.070132                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 144289.076824                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 76421.749493                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 131591.873778                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 131679.307110                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 133654.513889                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 133464.173182                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 135819.070132                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 144289.076824                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 76421.749493                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2806,338 +2806,338 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1483665                       # number of writebacks
-system.l2c.writebacks::total                  1483665                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker           12                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           27                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                39                       # number of ReadReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3.data            4                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.dtb.walker           12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.itb.walker           27                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.data              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 45                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.dtb.walker           12                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.itb.walker           27                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.data             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                45                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          724                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          700                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker         1192                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          941                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1779                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.itb.walker         1670                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            7006                       # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks          338                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total          338                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         5251                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data         6949                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data        11616                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        23816                       # number of UpgradeReq MSHR misses
+system.l2c.writebacks::writebacks              947584                       # number of writebacks
+system.l2c.writebacks::total                   947584                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            2                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                13                       # number of ReadReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            1                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data            4                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3.data            1                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.dtb.walker            2                       # number of demand (read+write) MSHR hits
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+system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.dtb.walker            2                       # number of overall MSHR hits
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+system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          366                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          326                       # number of ReadReq MSHR misses
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+system.l2c.ReadReq_mshr_misses::total            3352                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4480                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data         5760                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data         9480                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        19720                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        91622                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data       117894                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data       230007                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        439523                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         6490                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        27299                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        31020                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        64809                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data        34842                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data        56207                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data       101606                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       192655                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data        25091                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu2.data        36365                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu3.data        65672                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       127128                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker          724                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker          700                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         6490                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       126464                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker         1192                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker          941                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst        27299                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data       174101                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.dtb.walker         1779                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.itb.walker         1670                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst        31020                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data       331613                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           703993                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker          724                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker          700                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         6490                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       126464                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker         1192                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker          941                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst        27299                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data       174101                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.dtb.walker         1779                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.itb.walker         1670                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst        31020                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data       331613                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          703993                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         7202                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         6366                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3.data         6575                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        20143                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         6701                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         5973                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6301                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        18975                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        13903                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data        12339                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3.data        12876                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        39118                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     89987500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     89353000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker    153411500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker    118601000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker    228621000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker    216537500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    896511500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    370929500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    491743500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    821824000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   1684497000                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        26606                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total        56232                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data        27274                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data        38809                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data        79027                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total       145110                       # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data        19003                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu2.data        26418                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu3.data        48676                       # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total        94097                       # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker          366                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker          326                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         7162                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        72479                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker          383                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.itb.walker          343                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst        22464                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data       101554                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.dtb.walker         1013                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.itb.walker          921                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst        26606                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data       176715                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           410332                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker          366                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker          326                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         7162                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        72479                       # number of overall MSHR misses
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+system.l2c.overall_mshr_misses::cpu2.data       101554                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.dtb.walker         1013                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.itb.walker          921                       # number of overall MSHR misses
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+system.l2c.overall_mshr_misses::cpu3.data       176715                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          410332                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6832                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data         6962                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3.data         7151                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total        20945                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         6305                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         6510                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6865                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        19680                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        13137                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data        13472                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3.data        14016                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        40625                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     46339000                       # number of ReadReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker     44175000                       # number of ReadReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker    117603000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    428779000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    316657000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    407624000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    670775000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   1395056000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        72000                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total        72000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  11122718500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data  14485023000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  33155605000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  58763346500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    788235000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   3377725000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   3912594500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   8078554500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   4313978000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   7036589000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  13307454500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  24658021500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   3044579000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   4761179000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   9695864000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  17501622000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     89987500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     89353000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    788235000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  15436696500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker    153411500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker    118601000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst   3377725000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data  21521612000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker    228621000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.itb.walker    216537500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst   3912594500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data  46463059500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  92396434000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     89987500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     89353000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    788235000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  15436696500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker    153411500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker    118601000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst   3377725000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data  21521612000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker    228621000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.itb.walker    216537500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst   3912594500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data  46463059500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  92396434000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1257349000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1099961500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1114322500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3471633000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1204367500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1063346000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1092408000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   3360121500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2461716500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2163307500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2206730500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   6831754500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.008810                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.015256                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.006174                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.014935                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.005079                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.014223                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.005769                       # mshr miss rate for ReadReq accesses
-system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.778618                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.773056                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.788862                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.466413                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.296542                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.293148                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.321628                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.177302                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.003588                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006553                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.006555                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003873                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.035283                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.040636                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.043774                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.024345                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.224155                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.229741                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.234650                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.101991                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008810                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.015256                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.003588                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.097546                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.006174                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.014935                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006553                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.097517                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.005079                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.014223                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.006555                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.109216                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.024839                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008810                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.015256                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.003588                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.097546                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.006174                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.014935                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006553                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.097517                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.005079                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.014223                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.006555                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.109216                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.024839                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 127963.388524                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70639.782898                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70764.642395                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70749.311295                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70729.635539                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5465010500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   7683290500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  13374060000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  26522361000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    870841000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   2777775000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   3347666499                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   6996282499                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   3354184000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   4855123000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  10356862500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  18566169500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2289347500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   3405258500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   7088813000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  12783419000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     46339000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     41935500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    870841000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   8819194500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     48350000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     44175000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst   2777775000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data  12538413500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker    130376500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.itb.walker    117603000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst   3347666499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data  23730922500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  52513591999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     46339000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     41935500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    870841000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   8819194500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     48350000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     44175000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst   2777775000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data  12538413500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker    130376500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.itb.walker    117603000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst   3347666499                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data  23730922500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  52513591999                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1264338500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1284734500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1277563000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3826636000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1209386500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1243481500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1260805498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   3713673498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2473725000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2528216000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2538368498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   7540309498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.006415                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.007617                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002571                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.005986                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003536                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.008416                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.003458                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783354                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.795470                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.778133                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.458925                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.187913                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.190587                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.171036                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.104452                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.004247                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.005859                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005808                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003582                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.033051                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.035726                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.040645                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.022476                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.171783                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.176055                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.176822                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.076906                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.006415                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007617                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004247                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.068006                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002571                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.005986                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005859                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.071744                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003536                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008416                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005808                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.070251                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.016353                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.006415                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007617                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004247                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.068006                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002571                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.005986                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005859                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.071744                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003536                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008416                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005808                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.070251                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.016353                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 127917.362768                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70682.366071                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70768.055556                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70756.856540                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70743.204868                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        72000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121397.901159                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122864.802280                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 144150.417161                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 133698.001015                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121453.775039                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123730.722737                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126131.350741                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124651.738185                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123815.452615                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125190.616827                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 130971.148357                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127990.560847                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 121341.477024                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 130927.512718                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 147640.760141                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 137669.293940                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121453.775039                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122063.958913                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123730.722737                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123615.671363                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126131.350741                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 140112.298070                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 131246.239664                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121453.775039                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122063.958913                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123730.722737                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123615.671363                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126131.350741                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 140112.298070                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 131246.239664                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174583.310192                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 172786.914860                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169478.707224                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172349.352132                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179729.517982                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178025.447849                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 173370.576099                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177081.501976                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177063.691290                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 175322.757112                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 171383.232370                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 174644.779897                       # average overall mshr uncacheable latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120893.938724                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122452.633676                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 136905.863566                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 128975.972340                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124418.169352                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122981.007553                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125103.017341                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131054.734458                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127945.486183                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120472.951639                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 128899.178590                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 145632.611554                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 135853.629765                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121679.307110                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123465.481419                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134289.236907                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 127978.300496                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121679.307110                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123465.481419                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134289.236907                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 127978.300496                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185061.255855                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184535.262856                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 178655.153125                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 182699.259967                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191813.877875                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191010.983103                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 183657.028114                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 188702.921646                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 188302.123773                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 187664.489311                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 181105.058362                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 185607.618412                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               76751                       # Transaction distribution
-system.membus.trans_dist::ReadResp             550767                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33656                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33656                       # Transaction distribution
-system.membus.trans_dist::Writeback           1590295                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           250132                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            40589                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           40592                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1356297                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1356297                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        474016                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76702                       # Transaction distribution
+system.membus.trans_dist::ReadResp             438040                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33616                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33616                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1054215                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           195061                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34374                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           34376                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            877287                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           877287                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        361338                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122592                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122464                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           61                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6786                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5542839                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5672278                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342541                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342541                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6014819                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155722                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6736                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3755613                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3884874                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342734                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342734                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4227608                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155640                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13572                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    211708448                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    211877938                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7303680                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7303680                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               219181618                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1560                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3931023                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    139526112                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    139695420                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7304128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7304128                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               146999548                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1634                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2741682                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3931023    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2741682    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3931023                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            67063498                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2741682                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            69473500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy                2000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1693000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1838002                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          4875978841                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          2993221129                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4492458378                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2766254947                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          103510165                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          111131085                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -3148,11 +3148,11 @@ system.realview.ethernet.descDMAReads               0                       # Nu
 system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
 system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
 system.realview.ethernet.totPackets                 3                       # Total Packets
 system.realview.ethernet.totBytes                 966                       # Total Bytes
 system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
 system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
 system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
 system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
@@ -3191,60 +3191,61 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     57525316                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     29151092                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         3060                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2399                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2399                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     51354926                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     26009056                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         2855                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2048                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2048                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            1748199                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          26397420                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33656                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33656                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          9662082                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict        19582233                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           51062                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          51066                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2478951                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2478951                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      16735129                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7917622                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1294933                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1246469                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     50288517                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35153401                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       878892                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2158697                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              88479507                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1071219732                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1236530654                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3178896                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      7750232                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2318679514                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2264699                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         60538896                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.012147                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.109543                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            1478127                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          23632068                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33616                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33616                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      7917832                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     15694537                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2278182                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           42970                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          42972                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1968733                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1968733                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      15697459                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6461865                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1271562                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1223538                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47175640                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29164933                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       814493                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1705007                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              78860073                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2009256084                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1017810408                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2934600                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6010000                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3036011092                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1652274                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         37979201                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.016509                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.127422                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               59803521     98.79%     98.79% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 735375      1.21%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               37352210     98.35%     98.35% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 626991      1.65%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           60538896                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        23067770487                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           767706                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           37979201                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        30549015491                       # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy           656694                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       16065319902                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       15157992691                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        9498707196                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        7808308250                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         310622695                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         290510210                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         847575032                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         695723441                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index b9366b9f7..79264f671 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,161 +1,161 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.289289                       # Number of seconds simulated
-sim_ticks                                51289289109000                       # Number of ticks simulated
-final_tick                               51289289109000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.329060                       # Number of seconds simulated
+sim_ticks                                51329059921000                       # Number of ticks simulated
+final_tick                               51329059921000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 116964                       # Simulator instruction rate (inst/s)
-host_op_rate                                   137448                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6754182467                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 688124                       # Number of bytes of host memory used
-host_seconds                                  7593.71                       # Real time elapsed on the host
-sim_insts                                   888194021                       # Number of instructions simulated
-sim_ops                                    1043742869                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 121954                       # Simulator instruction rate (inst/s)
+host_op_rate                                   143308                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7039149523                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 740464                       # Number of bytes of host memory used
+host_seconds                                  7291.94                       # Real time elapsed on the host
+sim_insts                                   889279572                       # Number of instructions simulated
+sim_ops                                    1044993075                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       151872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       139200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          4024896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         41634016                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       137024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       129408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3236928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         42391336                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        430592                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             92275272                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4024896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3236928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7261824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78300352                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       138560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       132032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3631936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         41395808                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       145856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       130368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3527872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         42283560                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        424576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             91810568                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3631936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3527872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7159808                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     78035520                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78320932                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2373                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2175                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             62889                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            650540                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2141                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2022                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             50577                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            662369                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6728                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1441814                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1223443                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          78056100                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2165                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2063                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             56749                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            646818                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2279                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2037                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             55123                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            660685                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6634                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1434553                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1219305                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1226016                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2961                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               78474                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              811749                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2672                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               63111                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              826514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8395                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1799114                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          78474                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          63111                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             141586                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1526641                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1221878                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2699                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               70758                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              806479                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2540                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               68731                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              823774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8272                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1788666                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          70758                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          68731                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             139488                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1520299                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1527043                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1526641                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2961                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              78474                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             811749                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2672                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2523                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              63111                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             826916                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3326157                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1441814                       # Number of read requests accepted
-system.physmem.writeReqs                      1226016                       # Number of write requests accepted
-system.physmem.readBursts                     1441814                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1226016                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 92235136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     40960                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  78321024                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  92275272                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               78320932                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      640                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1520700                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1520299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2699                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2572                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              70758                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             806479                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2842                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2540                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              68731                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             824175                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8272                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3309366                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1434553                       # Number of read requests accepted
+system.physmem.writeReqs                      1221878                       # Number of write requests accepted
+system.physmem.readBursts                     1434553                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1221878                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 91768384                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     43008                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  78056128                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  91810568                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               78056100                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      672                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         143274                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               85394                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               90340                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               85251                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               84742                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               87352                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               95958                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               87724                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               87120                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               85128                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              115032                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              93810                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              94841                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              83101                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              88197                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              87648                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              89536                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               72684                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               76025                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               73393                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               74816                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               75820                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               81492                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               75165                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               76353                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               74241                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               82215                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              79031                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              79534                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              72343                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              77292                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              76022                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              77340                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         354445                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               86303                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               88556                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               87585                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               86132                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               85519                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               93403                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               87506                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               86099                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               84644                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              113970                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              93714                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              93674                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              83678                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              89960                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              85105                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              88033                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               73419                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               74799                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               75041                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               76138                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               74959                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               79592                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               75110                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               75651                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               74129                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               81022                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              78327                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              79368                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              72597                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              77989                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              74762                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              76724                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          16                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51289287954000                       # Total gap between requests
+system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51329058678000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1441799                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1434538                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1223443                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    661868                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    399209                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    215391                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    158760                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       856                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       607                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       570                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1170                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       794                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       390                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      404                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      203                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      141                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1219305                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    657679                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    396498                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -165,186 +165,185 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
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 system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::59392-61439            1      0.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::64-67             488      0.70%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              32      0.05%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              34      0.05%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             111      0.16%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               4      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            24      0.03%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           70105                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    42013541205                       # Total ticks spent queuing
-system.physmem.totMemAccLat               69035553705                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   7205870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       29152.30                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           69852                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    41803653811                       # Total ticks spent queuing
+system.physmem.totMemAccLat               68688922561                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   7169405000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29154.20                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47902.30                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.80                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.53                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47904.20                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.79                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.79                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1183295                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    918857                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.11                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.08                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19225096.03                       # Average gap between requests
-system.physmem.pageHitRate                      78.88                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2114615160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1153807875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                5490264000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3925247040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3349966598160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1237156507125                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29688344543250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34288151582610                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.524687                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49388977684769                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1712661860000                       # Time in different power states
+system.physmem.avgRdQLen                         1.29                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         8.57                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1177173                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    915297                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.05                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19322564.25                       # Average gap between requests
+system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2106662040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1149468375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5468603400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3918514320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3352564322640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1237967178795                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29711496726750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34314671476320                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.523347                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49427496871292                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1713989940000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    187649331731                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    187567949958                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2140047000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1167684375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5750846400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4004756640                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3349966598160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1240738244055                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29685202677000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34288970853630                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.540660                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49383704909692                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1712661860000                       # Time in different power states
+system.physmem_1.actEnergy                 2134770120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1164805125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5715621600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3984668640                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3352564322640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1240798843035                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29709012810750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34315375841910                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.537070                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49423322508450                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1713989940000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    192921720308                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    191746853550                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -374,15 +373,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              131510280                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         89076411                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5754624                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            89205696                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               64088886                       # Number of BTB hits
+system.cpu0.branchPred.lookups              128171553                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         86901839                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5585684                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            86828453                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               62767092                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            71.843939                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17216191                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            189076                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.288622                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               16853141                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            186956                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -413,92 +412,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   879879                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               879879                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16451                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88924                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       539694                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       340185                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2660.496495                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 15843.329302                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       337511     99.21%     99.21% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1400      0.41%     99.63% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          868      0.26%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          160      0.05%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679          148      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           35      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           25      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                   885239                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               885239                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16068                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88252                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       546727                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       338512                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2698.944203                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 16449.109677                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       335800     99.20%     99.20% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1393      0.41%     99.61% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          884      0.26%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          153      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679          156      0.05%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           36      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           43      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::458752-524287           32      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       340185                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       407005                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23314.236926                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18617.801732                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 20825.488249                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       397459     97.65%     97.65% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         7042      1.73%     99.38% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1712      0.42%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          113      0.03%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          415      0.10%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215          146      0.04%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823           10      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::589824-655359            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       338512                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       409508                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23024.226633                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18496.792158                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 19848.076678                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       400961     97.91%     97.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6256      1.53%     99.44% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1568      0.38%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          126      0.03%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          350      0.09%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215          156      0.04%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::393216-458751           68      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       407005                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 376382023716                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.109107                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.663618                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 375374134216     99.73%     99.73% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7    555470000      0.15%     99.88% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11    199772500      0.05%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15    117350500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19     45444000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23     24549500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27     26272500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31     32439000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35      6175500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39       322000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43        41000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47        35000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51        18000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 376382023716                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        88924     84.39%     84.39% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        16451     15.61%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       105375                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       879879                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total       409508                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 369272261460                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.199871                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.721140                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 368268104460     99.73%     99.73% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7    539578000      0.15%     99.87% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11    201182000      0.05%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15    121167500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19     48555500      0.01%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23     26406000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27     26984000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31     34302000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35      5588500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39       301000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43        52000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47        18000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51        22500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 369272261460                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        88253     84.60%     84.60% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        16068     15.40%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       104321                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       885239                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       879879                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       105375                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       885239                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       104321                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       105375                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       985254                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       104321                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       989560                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   104450342                       # DTB read hits
-system.cpu0.dtb.read_misses                    607388                       # DTB read misses
-system.cpu0.dtb.write_hits                   80999803                       # DTB write hits
-system.cpu0.dtb.write_misses                   272491                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1103                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                   102290715                       # DTB read hits
+system.cpu0.dtb.read_misses                    610545                       # DTB read misses
+system.cpu0.dtb.write_hits                   79331513                       # DTB write hits
+system.cpu0.dtb.write_misses                   274694                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1105                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21264                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    532                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   54933                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      199                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9612                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              21571                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    526                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   54684                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      193                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9578                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    55908                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               105057730                       # DTB read accesses
-system.cpu0.dtb.write_accesses               81272294                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    56017                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               102901260                       # DTB read accesses
+system.cpu0.dtb.write_accesses               79606207                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        185450145                       # DTB hits
-system.cpu0.dtb.misses                         879879                       # DTB misses
-system.cpu0.dtb.accesses                    186330024                       # DTB accesses
+system.cpu0.dtb.hits                        181622228                       # DTB hits
+system.cpu0.dtb.misses                         885239                       # DTB misses
+system.cpu0.dtb.accesses                    182507467                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -528,849 +524,848 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                   105425                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong               105425                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3033                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        71538                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        14522                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        90903                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1916.366897                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 12628.127488                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        89834     98.82%     98.82% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          539      0.59%     99.42% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303           99      0.11%     99.53% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          130      0.14%     99.67% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839          200      0.22%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           51      0.06%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375           18      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            4      0.00%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks                   102914                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong               102914                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2949                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69039                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        14347                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        88567                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1898.844942                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 12048.773919                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767        87489     98.78%     98.78% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535          597      0.67%     99.46% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303           92      0.10%     99.56% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071          110      0.12%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839          199      0.22%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607           35      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375           18      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        90903                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        89093                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 29737.628096                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24673.282560                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 24049.122605                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        86936     97.58%     97.58% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          600      0.67%     98.25% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         1294      1.45%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           93      0.10%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679          133      0.15%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           25      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        89093                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 303340156184                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.819271                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -248434536268    -81.90%    -81.90% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   551700406452    181.88%     99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       66884500      0.02%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        6271500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         916000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          53500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6         160500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 303340156184                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        71538     95.93%     95.93% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         3033      4.07%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        74571                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        88567                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        86335                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 29628.748480                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24429.301414                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 24451.958978                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        84088     97.40%     97.40% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          706      0.82%     98.22% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607         1293      1.50%     99.71% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           86      0.10%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679          119      0.14%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           18      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        86335                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 279075367244                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.887042                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -247471426488    -88.68%    -88.68% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   526476465732    188.65%     99.97% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       62141000      0.02%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        6800000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4        1085000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5         302000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 279075367244                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        69039     95.90%     95.90% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2949      4.10%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        71988                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       105425                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total       105425                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102914                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102914                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        74571                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        74571                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       179996                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    94464352                       # ITB inst hits
-system.cpu0.itb.inst_misses                    105425                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        71988                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        71988                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       174902                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    91881601                       # ITB inst hits
+system.cpu0.itb.inst_misses                    102914                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1103                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1105                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21264                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    532                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   41067                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21571                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    526                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   40429                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   204534                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   204535                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                94569777                       # ITB inst accesses
-system.cpu0.itb.hits                         94464352                       # DTB hits
-system.cpu0.itb.misses                         105425                       # DTB misses
-system.cpu0.itb.accesses                     94569777                       # DTB accesses
-system.cpu0.numCycles                       693727147                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                91984515                       # ITB inst accesses
+system.cpu0.itb.hits                         91881601                       # DTB hits
+system.cpu0.itb.misses                         102914                       # DTB misses
+system.cpu0.itb.accesses                     91984515                       # DTB accesses
+system.cpu0.numCycles                       691170563                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         245689923                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     583659918                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  131510280                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          81305077                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    403973689                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13146062                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2696063                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               24792                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             6132                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      5442737                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       182065                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         4382                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 94242396                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3550844                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  42244                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         664592540                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.028282                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.281038                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         239962884                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     570438077                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  128171553                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          79620233                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    407738854                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               12781952                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2594971                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               25425                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             5359                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      5458708                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       162648                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         3329                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 91660544                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3463851                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  41672                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         662342878                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.009072                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.262587                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               520383096     78.30%     78.30% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                18093254      2.72%     81.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18296207      2.75%     83.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13332643      2.01%     85.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                28010014      4.21%     90.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 9092439      1.37%     91.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9727305      1.46%     92.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8422108      1.27%     94.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                39235474      5.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               521294405     78.70%     78.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                17644727      2.66%     81.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                17609553      2.66%     84.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13023217      1.97%     85.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                28132742      4.25%     90.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 8705409      1.31%     91.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9465006      1.43%     92.98% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8172202      1.23%     94.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                38295617      5.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           664592540                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.189571                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.841339                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               199631749                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            341256701                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                105213142                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13320667                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5167977                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19724467                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1425325                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             637042209                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4387868                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5167977                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               207139071                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               31235122                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     259336821                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                110889608                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             50821415                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             622130396                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents               110301                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2210574                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1917918                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              31535075                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            3960                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          595274899                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            956990256                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       735490255                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           762145                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            501553477                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                93721422                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          14866567                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      12875390                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 74435077                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           100241817                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           85151630                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13697674                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14727627                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 590625310                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           14935431                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                591459977                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           828967                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       78563814                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     50313782                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        364460                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    664592540                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.889959                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.628761                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           662342878                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.185441                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.825322                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               194658503                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            347202119                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                101960102                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13505854                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5013938                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19069784                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1396202                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             622839427                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4306034                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5013938                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               202133183                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               32047845                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     264605257                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                107868981                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             50671063                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             608332366                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                94298                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2196276                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1835605                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              31002598                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            3774                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          582920651                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            941800609                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       719611293                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           780673                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            492512857                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                90407789                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15406324                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13476597                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 76098764                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            97666868                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           83390194                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13497619                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14417995                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 576927509                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15532510                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                579347297                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           823601                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       76188435                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     48806754                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        359672                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    662342878                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.874694                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.613558                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          433116455     65.17%     65.17% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           96939801     14.59%     79.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           43307418      6.52%     86.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           30869552      4.64%     90.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           22882943      3.44%     94.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           15965693      2.40%     96.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           10866497      1.64%     98.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6415983      0.97%     99.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4228198      0.64%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          433272632     65.42%     65.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           98115954     14.81%     80.23% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           42214584      6.37%     86.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           29957655      4.52%     91.13% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           22351656      3.37%     94.50% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           15512359      2.34%     96.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           10588779      1.60%     98.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6205955      0.94%     99.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4123304      0.62%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      664592540                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      662342878                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                3016734     25.85%     25.85% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 25376      0.22%     26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   2604      0.02%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               2      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     26.08% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4797053     41.10%     67.18% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3830581     32.82%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                2935970     25.32%     25.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 23101      0.20%     25.52% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   2125      0.02%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.54% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4825862     41.62%     67.16% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3807172     32.84%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass                4      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            401312314     67.85%     67.85% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1456904      0.25%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                65858      0.01%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                165      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            393154923     67.86%     67.86% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1386126      0.24%     68.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                65806      0.01%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                 67      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   2      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   1      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               4      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               1      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              9      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.11% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         60568      0.01%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         58960      0.01%     68.12% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.12% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.12% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           106521284     18.01%     86.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           82042825     13.87%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           104322059     18.01%     86.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           80359344     13.87%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             591459977                       # Type of FU issued
-system.cpu0.iq.rate                          0.852583                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11672350                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019735                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1858987169                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        684321714                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    570020326                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1026642                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            511393                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       456189                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             602584344                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 547979                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4688231                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             579347297                       # Type of FU issued
+system.cpu0.iq.rate                          0.838212                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11594230                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.020013                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        1832414752                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        668808824                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    557946251                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1040551                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            514226                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       463065                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             590385045                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 556471                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4593967                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     15870823                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        20812                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       719682                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      8709865                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     15457682                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        19886                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       685587                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      8559329                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      3916695                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      7873559                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      3807037                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      8317580                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5167977                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               16609605                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles             12703167                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          605694561                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1733726                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            100241817                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            85151630                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          12585145                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                227737                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents             12390007                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        719682                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2598504                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2279450                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             4877954                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            584896168                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            104440997                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          5696378                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5013938                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               16283569                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles             13949536                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          592593872                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1684559                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             97666868                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            83390194                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13181889                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                225552                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents             13639351                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        685587                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2515735                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2200394                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4716129                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            572987032                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            102282970                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          5487366                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       133820                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   185440040                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               108756194                       # Number of branches executed
-system.cpu0.iew.exec_stores                  80999043                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.843121                       # Inst execution rate
-system.cpu0.iew.wb_sent                     571697028                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    570476515                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                281622326                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                489116164                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       133853                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   181615455                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               106143494                       # Number of branches executed
+system.cpu0.iew.exec_stores                  79332485                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.829010                       # Inst execution rate
+system.cpu0.iew.wb_sent                     559590255                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    558409316                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                275573262                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                478603193                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.822336                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575778                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.807918                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.575787                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts       78604829                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       14570971                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4349296                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    651171717                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.809306                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.808418                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts       76231429                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15172838                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4208370                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    649315784                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.795101                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.790427                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    458185820     70.36%     70.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     94765025     14.55%     84.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     33137681      5.09%     90.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     15077927      2.32%     92.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10931676      1.68%     94.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6537456      1.00%     95.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6054601      0.93%     95.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3871079      0.59%     96.53% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     22610452      3.47%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    458104846     70.55%     70.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     95694647     14.74%     85.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     32190614      4.96%     90.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     14675845      2.26%     92.51% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10626542      1.64%     94.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6339406      0.98%     95.12% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      5863967      0.90%     96.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3778167      0.58%     96.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     22041750      3.39%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    651171717                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           448537783                       # Number of instructions committed
-system.cpu0.commit.committedOps             526996927                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    649315784                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           439229242                       # Number of instructions committed
+system.cpu0.commit.committedOps             516271579                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     160812759                       # Number of memory references committed
-system.cpu0.commit.loads                     84370994                       # Number of loads committed
-system.cpu0.commit.membars                    3712862                       # Number of memory barriers committed
-system.cpu0.commit.branches                 100457713                       # Number of branches committed
-system.cpu0.commit.fp_insts                    437537                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                483805259                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13348009                       # Number of function calls committed.
+system.cpu0.commit.refs                     157040050                       # Number of memory references committed
+system.cpu0.commit.loads                     82209185                       # Number of loads committed
+system.cpu0.commit.membars                    3679399                       # Number of memory barriers committed
+system.cpu0.commit.branches                  98142600                       # Number of branches committed
+system.cpu0.commit.fp_insts                    444854                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                473776942                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13048594                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       364956602     69.25%     69.25% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1127311      0.21%     69.47% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           49300      0.01%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        50913      0.01%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       84370994     16.01%     85.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      76441765     14.51%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       358050943     69.35%     69.35% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1081428      0.21%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           48877      0.01%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        50281      0.01%     69.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.58% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       82209185     15.92%     85.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      74830865     14.49%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        526996927                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             22610452                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1230217301                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1224645571                       # The number of ROB writes
-system.cpu0.timesIdled                        4130146                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       29134607                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 48521219733                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  448537783                       # Number of Instructions Simulated
-system.cpu0.committedOps                    526996927                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.546641                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.546641                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.646562                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.646562                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               689663562                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              407539482                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   822896                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  494260                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                125263725                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               126423537                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1208432146                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              14685746                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements         10442064                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.972968                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          299912904                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10442576                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.720203                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        516271579                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             22041750                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1215785177                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1198053925                       # The number of ROB writes
+system.cpu0.timesIdled                        4064231                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       28827685                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 52470002692                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  439229242                       # Number of Instructions Simulated
+system.cpu0.committedOps                    516271579                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.573599                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.573599                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.635486                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.635486                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               676011417                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              398349827                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   844800                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  475036                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                123341922                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               124453917                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1200774516                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15268687                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements         10441215                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.972989                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          300350847                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10441727                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.764480                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       2716190500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   306.410459                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   205.562509                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.598458                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.401489                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   278.618843                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   233.354146                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.544177                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.455770                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1323031608                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1323031608                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     80041652                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     78145564                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      158187216                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67282411                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     66174015                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     133456426                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       208357                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       193759                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       402116                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       179575                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       144785                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       324360                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1768308                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1713443                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3481751                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2038321                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1974130                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4012451                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    147324063                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    144319579                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       291643642                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    147532420                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    144513338                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      292045758                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6276474                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6183597                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12460071                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6322158                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6339058                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     12661216                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       639187                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       638043                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1277230                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       615392                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       622485                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1237877                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       328942                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       317586                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       646528                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            8                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            6                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           14                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     12598632                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     12522655                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      25121287                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     13237819                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     13160698                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     26398517                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112360682500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 108979382500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 221340065000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 275146028128                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 278942428574                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 554088456702                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  44475704107                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  47058017442                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  91533721549                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4608102000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4295538500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   8903640500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       178500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       151500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       330000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 387506710628                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 387921811074                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 775428521702                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 387506710628                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 387921811074                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 775428521702                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     86318126                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     84329161                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    170647287                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73604569                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     72513073                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    146117642                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       847544                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       831802                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1679346                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       794967                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       767270                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1562237                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2097250                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2031029                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4128279                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2038329                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1974136                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4012465                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    159922695                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    156842234                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    316764929                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    160770239                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    157674036                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    318444275                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.072713                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.073327                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.073017                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.085894                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.087420                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.086651                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.754164                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.767061                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760552                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.774110                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.811298                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792375                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.156844                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.156367                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156610                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.tags.tag_accesses       1324703631                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1324703631                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     77691173                       # number of ReadReq hits
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+system.cpu0.dcache.ReadReq_hits::total      158383515                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     65479208                       # number of WriteReq hits
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+system.cpu0.dcache.WriteReq_hits::total     133697054                       # number of WriteReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total       401571                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       173286                       # number of WriteLineReq hits
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+system.cpu0.dcache.WriteLineReq_hits::total       325114                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1754825                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1726209                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3481034                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2015188                       # number of StoreCondReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total      4013904                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    143170381                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    148910188                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       292080569                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    143375242                       # number of overall hits
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+system.cpu0.dcache.overall_hits::total      292482140                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6274582                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      6195801                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total     12470383                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      6551010                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      6079210                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total     12630220                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       672252                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       604348                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1276600                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       607594                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       629524                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1237118                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       316888                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       332062                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       648950                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     12825592                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data     12275011                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      25100603                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     13497844                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data     12879359                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     26377203                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110046320000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111087741500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 221134061500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 282950530887                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 268653294230                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 551603825117                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  43457890636                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  47921476510                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  91379367146                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4290157000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4634510500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   8924667500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       150500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       207500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       358000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 392996850887                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 379741035730                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 772737886617                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 392996850887                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 379741035730                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 772737886617                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     83965755                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     86888143                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    170853898                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     72030218                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     74297056                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    146327274                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       877113                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       801058                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1678171                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       780880                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       781352                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1562232                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2071713                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2058271                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4129984                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2015194                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1998721                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      4013915                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    155995973                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    161185199                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    317181172                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    156873086                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    161986257                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    318859343                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074728                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.071308                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.072989                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.090948                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.081823                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.086315                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766437                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.754437                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760709                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.778089                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.805686                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.791891                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.152959                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.161331                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.157131                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.078780                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.079842                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.079306                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.082340                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.083468                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.082898                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17901.879702                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17623.946467                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17763.948937                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43520.903484                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44003.766581                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43762.657292                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 72272.151908                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 75597.030357                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73944.116862                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14008.858705                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13525.591493                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13771.469294                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22312.500000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        25250                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23571.428571                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30757.840266                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30977.601082                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 30867.388351                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29272.700482                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29475.777886                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 29373.942548                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     88168676                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       110752                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3495525                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           1064                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.223300                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   104.090226                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.082217                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.076155                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.079136                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086043                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.079509                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.082724                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17538.430448                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17929.520574                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17732.740165                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.894210                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44192.139148                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43673.334678                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 71524.555272                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 76123.351151                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73864.713912                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13538.401580                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13956.762593                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13752.473226                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25083.333333                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        41500                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32545.454545                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30641.614897                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30936.105534                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 30785.630394                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29115.527701                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29484.467024                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 29295.671972                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     87920844                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       114851                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3496537                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           1061                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.145120                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   108.247879                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8003050                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8003050                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3450278                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3389516                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      6839794                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5251049                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5273458                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10524507                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3747                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3282                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         7029                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       203336                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       195633                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       398969                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      8701327                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      8662974                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     17364301                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      8701327                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      8662974                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     17364301                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2826196                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2794081                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5620277                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1071109                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1065600                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2136709                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       626536                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       626309                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1252845                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       611645                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       619203                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1230848                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       125606                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121953                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       247559                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            8                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            6                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           14                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3897305                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3859681                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7756986                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4523841                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4485990                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      9009831                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16464                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17213                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33677                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15292                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18404                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31756                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35617                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67373                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49680928000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  48547045000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98227973000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  49497765698                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  49329695702                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  98827461400                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  12314245500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12444174500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24758420000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  43627522607                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  46272791442                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  89900314049                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1845699500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1727387000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3573086500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       170500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       145500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       316000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99178693698                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  97876740702                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 197055434400                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111492939198                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110320915202                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 221813854400                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2819562500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3022126000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5841688500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2713847000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3108432498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5822279498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5533409500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6130558498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11663967998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032742                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033133                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032935                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014552                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014695                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014623                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.739237                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.752954                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746031                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.769397                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.807021                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787875                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059891                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060045                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059967                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.writebacks::writebacks      8016148                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8016148                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3459904                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3385993                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      6845897                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5454136                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5045051                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10499187                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3486                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3453                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         6939                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       195002                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       204372                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       399374                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      8914040                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      8431044                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     17345084                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      8914040                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      8431044                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     17345084                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2814678                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2809808                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5624486                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1096874                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1034159                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2131033                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       658655                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       593550                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1252205                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       604108                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       626071                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1230179                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       121886                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       127690                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       249576                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3911552                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3843967                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7755519                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4570207                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4437517                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      9007724                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15990                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17689                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33679                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        14658                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        19039                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30648                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        36728                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67376                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48435084000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49650597000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98085681000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  50577189739                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  47912432297                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  98489622036                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13555749500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11111774000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24667523500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  42652248636                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  47094090510                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  89746339146                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1696955500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1893897000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3590852500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       144500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       202500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       347000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99012273739                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  97563029297                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 196575303036                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112568023239                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 108674803297                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 221242826536                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2881077500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3350690000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6231767500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2752373000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3455424991                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6207797991                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5633450500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6806114991                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12439565491                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033522                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032338                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032920                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015228                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013919                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014563                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750935                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.740958                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746172                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.773625                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.801266                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787450                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058833                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062038                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060430                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024370                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024609                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024488                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028139                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028451                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028293                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17578.727024                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17374.959781                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17477.425579                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46211.698061                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46292.882603                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46252.185674                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19654.489926                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19869.065429                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19761.758238                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71328.176650                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 74729.598277                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73039.330648                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14694.357754                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14164.366600                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14433.272472                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21312.500000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        24250                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22571.428571                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25448.019516                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25358.764287                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25403.608360                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24645.636130                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24592.323033                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24619.091568                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171256.225705                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175572.300006                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173462.259109                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177468.414857                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168899.831450                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172788.446641                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174247.685477                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172124.505096                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173125.257863                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025075                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023848                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024451                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029133                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027394                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028250                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17208.037296                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17670.458978                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17439.047941                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46110.300489                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46329.850919                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46216.845087                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20580.955887                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18720.872715                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19699.269289                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 70603.681189                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 75221.645005                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 72953.886504                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13922.480843                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14831.991542                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14387.811729                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24083.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        40500                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 31545.454545                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25312.784731                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25380.818643                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25346.505248                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24630.836905                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24490.002697                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24561.457093                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180179.956223                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189422.239810                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185034.220137                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187772.752081                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181491.937129                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184224.055287                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183811.358001                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185311.342600                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184629.029491                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         15993913                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.921230                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          168728933                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         15994425                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.549234                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      23717372500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   279.340793                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   232.580437                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.545587                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.454259                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         16004570                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.921303                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          169009090                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         16005082                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.559714                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      23708267500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   282.699542                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   229.221761                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.552148                       # Average percentage of cache occupancy
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 system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
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-system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
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 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
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-system.cpu0.icache.ReadReq_hits::total      168728933                       # number of ReadReq hits
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-system.cpu0.icache.overall_hits::total      168728933                       # number of overall hits
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-system.cpu0.icache.ReadReq_misses::total     17223550                       # number of ReadReq misses
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-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13371.120304                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.746327                       # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 13416.746327                       # average overall miss latency
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-system.cpu0.icache.overall_avg_miss_latency::total 13416.746327                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs       127389                       # number of cycles access was blocked
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 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
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 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
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-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960778000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636240000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086272                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085749                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.086014                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086272                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085749                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.086014                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086272                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085749                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.086014                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12787.980784                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12705.482348                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12747.412823                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12787.980784                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12705.482348                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12747.412823                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12787.980784                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12705.482348                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12747.412823                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127687.687688                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127687.687688                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 101752782407                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103549068385                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 205301850792                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 101752782407                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103549068385                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 205301850792                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 101752782407                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103549068385                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 205301850792                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636383000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636383000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085934                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.085934                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.085934                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12827.195233                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12827.195233                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12827.195233                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              128002334                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         87000769                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5591841                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            87469952                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               62728816                       # Number of BTB hits
+system.cpu1.branchPred.lookups              131672686                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89355343                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5781214                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            89724326                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               64173033                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            71.714703                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               16690428                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            184044                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            71.522446                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17121716                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            186515                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1400,91 +1395,94 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   888625                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               888625                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16515                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        89516                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       551182                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       337443                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2618.907490                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 15834.815336                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       334927     99.25%     99.25% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1259      0.37%     99.63% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          844      0.25%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          153      0.05%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679          151      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           38      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           37      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287           30      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       337443                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       414261                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23202.362762                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18749.985984                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 19280.784036                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       405371     97.85%     97.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         6574      1.59%     99.44% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1705      0.41%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           91      0.02%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          347      0.08%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215          109      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           45      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       414261                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 346681338644                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.164180                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.727467                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 345667955144     99.71%     99.71% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7    547148000      0.16%     99.87% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11    197378500      0.06%     99.92% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15    124829500      0.04%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19     46718000      0.01%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23     26902000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27     29536000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31     34566500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35      5689000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39       518500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43        43000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47        27500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51        26500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::52-55          500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 346681338644                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        89517     84.42%     84.42% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        16515     15.58%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       106032                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       888625                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   890074                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               890074                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16464                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        90676                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       549449                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       340625                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2662.717064                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 16656.719504                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       337983     99.22%     99.22% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1343      0.39%     99.62% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          873      0.26%     99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          159      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679          157      0.05%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           32      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           28      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287           31      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::720896-786431            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::786432-851967            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::851968-917503            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::917504-983039            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::983040-1.04858e+06            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       340625                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       415755                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23534.974925                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18938.344998                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 20176.522890                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       406038     97.66%     97.66% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7288      1.75%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1678      0.40%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          118      0.03%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          407      0.10%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215          121      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           66      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       415755                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 351694007776                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.068501                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.668276                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 350661865276     99.71%     99.71% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7    565026500      0.16%     99.87% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11    204421500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15    121176000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19     47649500      0.01%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23     25922000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27     25482500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31     35190500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35      6889500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39       280500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43        36000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47        45500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51        22500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 351694007776                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        90676     84.63%     84.63% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        16464     15.37%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       107140                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       890074                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       888625                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       106032                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       890074                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       107140                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       106032                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       994657                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       107140                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       997214                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   102078491                       # DTB read hits
-system.cpu1.dtb.read_misses                    609526                       # DTB read misses
-system.cpu1.dtb.write_hits                   79752942                       # DTB write hits
-system.cpu1.dtb.write_misses                   279099                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1097                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                   104588302                       # DTB read hits
+system.cpu1.dtb.read_misses                    610979                       # DTB read misses
+system.cpu1.dtb.write_hits                   81672452                       # DTB write hits
+system.cpu1.dtb.write_misses                   279095                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1101                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              21138                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    525                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   54374                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      189                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  9195                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              20830                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    531                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   55425                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      192                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  9142                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    57003                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               102688017                       # DTB read accesses
-system.cpu1.dtb.write_accesses               80032041                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    57336                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               105199281                       # DTB read accesses
+system.cpu1.dtb.write_accesses               81951547                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        181831433                       # DTB hits
-system.cpu1.dtb.misses                         888625                       # DTB misses
-system.cpu1.dtb.accesses                    182720058                       # DTB accesses
+system.cpu1.dtb.hits                        186260754                       # DTB hits
+system.cpu1.dtb.misses                         890074                       # DTB misses
+system.cpu1.dtb.accesses                    187150828                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1514,381 +1512,388 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                   103286                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong               103286                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         2985                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        70650                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        14185                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        89101                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1880.887981                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 12259.575091                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-65535        88607     99.45%     99.45% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-131071          208      0.23%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-196607          245      0.27%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-262143           23      0.03%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-327679            9      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-393215            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        89101                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        87820                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 29448.206559                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24574.367788                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 23374.084602                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        85760     97.65%     97.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          575      0.65%     98.31% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607         1268      1.44%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           74      0.08%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679          108      0.12%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           15      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        87820                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 303729046684                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     1.808269                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0   -245416179168    -80.80%    -80.80% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   549075630852    180.78%     99.98% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       61607500      0.02%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        7072500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         899500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5          15500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 303729046684                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        70650     95.95%     95.95% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         2985      4.05%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        73635                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                   107237                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong               107237                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3106                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        74018                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        14783                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        92454                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1914.233024                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 12442.896364                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        91334     98.79%     98.79% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          604      0.65%     99.44% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303           90      0.10%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071          135      0.15%     99.69% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839          192      0.21%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           45      0.05%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375           20      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911           11      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-425983            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        92454                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        91907                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 29826.585570                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25014.091101                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 23207.372292                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        89740     97.64%     97.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          728      0.79%     98.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1203      1.31%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           89      0.10%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679          102      0.11%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           19      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           20      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        91907                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 308743335316                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     1.811344                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0   -250411422516    -81.11%    -81.11% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   559080989832    181.08%     99.98% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       64275500      0.02%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        7864000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4        1253500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5         141000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::6         234000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 308743335316                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        74018     95.97%     95.97% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         3106      4.03%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        77124                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       103286                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total       103286                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       107237                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total       107237                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        73635                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        73635                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       176921                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    91956391                       # ITB inst hits
-system.cpu1.itb.inst_misses                    103286                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        77124                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        77124                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       184361                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    94835234                       # ITB inst hits
+system.cpu1.itb.inst_misses                    107237                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1097                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1101                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              21138                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    525                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   40049                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              20830                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    531                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   41604                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   202974                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   202082                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                92059677                       # ITB inst accesses
-system.cpu1.itb.hits                         91956391                       # DTB hits
-system.cpu1.itb.misses                         103286                       # DTB misses
-system.cpu1.itb.accesses                     92059677                       # DTB accesses
-system.cpu1.numCycles                       683589124                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                94942471                       # ITB inst accesses
+system.cpu1.itb.hits                         94835234                       # DTB hits
+system.cpu1.itb.misses                         107237                       # DTB misses
+system.cpu1.itb.accesses                     94942471                       # DTB accesses
+system.cpu1.numCycles                       690312922                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         238009169                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     571176057                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  128002334                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          79419244                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    404719127                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               12774600                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2616585                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               24222                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             5589                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      5368087                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       160870                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         2610                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 91730802                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3443412                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  41301                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         657293286                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.017856                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.272002                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         244529898                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     585856252                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  131672686                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          81294749                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    402345645                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13192141                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2778573                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               21795                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             5943                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      5312997                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       174263                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         3566                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 94609332                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3554739                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  42315                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         661768476                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.036278                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.289766                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               516237120     78.54%     78.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                17632958      2.68%     81.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                17654036      2.69%     83.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13091323      1.99%     85.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                27900711      4.24%     90.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 8639588      1.31%     91.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9467175      1.44%     92.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8151646      1.24%     94.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                38518729      5.86%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               517207044     78.16%     78.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                18129888      2.74%     80.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                18375332      2.78%     83.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13432056      2.03%     85.70% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                27838578      4.21%     89.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 9027951      1.36%     91.27% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9770345      1.48%     92.75% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8415200      1.27%     94.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                39572082      5.98%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           657293286                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.187250                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.835555                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               193664291                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            342800105                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                102542010                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13254966                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5029491                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            18937376                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1377136                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             623890493                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4237673                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5029491                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               201058836                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               31048942                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     259190035                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                108261392                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             52701935                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             609359225                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents               108791                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               2049420                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1849812                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              33430397                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            3628                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          583294874                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            940667365                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       720819975                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           791427                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            492359028                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                90935841                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15032233                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13124059                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 74465076                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            97949385                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           83816258                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13144575                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14065563                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 578164482                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15125943                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                579632592                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           823862                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       76544478                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     48922532                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        353577                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    657293286                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.881848                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.622601                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           661768476                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.190743                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.848682                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               199426637                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            337927065                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                106132516                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             13075533                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5204264                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19655517                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1411698                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             639761275                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4339654                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5204264                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               206862514                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               30693400                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     255298873                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                111614723                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             52092053                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             624767105                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents               119693                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               2051470                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1928200                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              33207471                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            3875                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          596912920                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            957883599                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       738584518                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           769692                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            502441681                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                94471239                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          14502575                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      12526593                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 72768072                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           100816739                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           85870948                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13475308                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14310498                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 593385744                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           14541945                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                593302844                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           834025                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       79206193                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     50535241                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        362086                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    661768476                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.896541                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.637280                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          429426254     65.33%     65.33% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           96715112     14.71%     80.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           42097823      6.40%     86.45% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           29977053      4.56%     91.01% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           22357761      3.40%     94.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           15606240      2.37%     96.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           10657458      1.62%     98.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6260997      0.95%     99.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4194588      0.64%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          430990787     65.13%     65.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           95612119     14.45%     79.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           43322710      6.55%     86.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           31009109      4.69%     90.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           22951412      3.47%     94.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           16184580      2.45%     96.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           10912216      1.65%     98.37% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6468210      0.98%     99.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4317333      0.65%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      657293286                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      661768476                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                2920465     25.31%     25.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 23164      0.20%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   2858      0.02%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               1      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.54% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4710924     40.83%     66.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3880904     33.63%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                3013963     25.80%     25.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 25479      0.22%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   3319      0.03%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               1      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.04% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4708735     40.30%     66.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3932373     33.66%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            393199833     67.84%     67.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1396367      0.24%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                66291      0.01%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                 69      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               1      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         68890      0.01%     68.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           104108183     17.96%     86.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           80792947     13.94%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass                2      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            402293875     67.81%     67.81% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1465613      0.25%     68.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                66790      0.01%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                152      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         70080      0.01%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           106673645     17.98%     86.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           82732640     13.94%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             579632592                       # Type of FU issued
-system.cpu1.iq.rate                          0.847925                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11538316                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019906                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1827853747                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        669983955                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    558625373                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1066901                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            527037                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       476493                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             590600685                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 570212                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4591636                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             593302844                       # Type of FU issued
+system.cpu1.iq.rate                          0.859469                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11683870                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019693                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1859837992                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        687326005                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    572108496                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1054067                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            524138                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       469445                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             604424270                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 562442                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4728038                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     15509069                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        19434                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       687053                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      8553480                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     15991835                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        20369                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       727913                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      8786210                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3778771                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      7833875                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3909440                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      7480668                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5029491                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               16246993                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles             12738129                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          593422501                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1696916                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             97949385                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            83816258                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12835084                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                232041                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents             12419302                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        687053                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2537334                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2208748                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4746082                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            573207937                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            102068127                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          5548487                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5204264                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               16486033                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles             12035619                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          608060202                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1765454                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            100816739                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            85870948                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12241352                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                233009                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents             11715765                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        727913                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2628157                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2293591                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4921748                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            586639297                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            104576028                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          5786024                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       132076                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   181824390                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               105934255                       # Number of branches executed
-system.cpu1.iew.exec_stores                  79756263                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.838527                       # Inst execution rate
-system.cpu1.iew.wb_sent                     560287134                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    559101866                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                276158020                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                479351020                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       132513                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   186249978                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               108834662                       # Number of branches executed
+system.cpu1.iew.exec_stores                  81673950                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.849816                       # Inst execution rate
+system.cpu1.iew.wb_sent                     573803675                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    572577941                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                282811002                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                490863765                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.817892                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.576108                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.829447                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.576150                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       76588811                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14772366                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4233759                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    644213743                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.802134                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.802116                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       79254249                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14179859                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4389133                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    648242205                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.815623                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.819454                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    454416895     70.54%     70.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     94019038     14.59%     85.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     32034419      4.97%     90.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     14900535      2.31%     92.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10532700      1.63%     94.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6339894      0.98%     95.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      5911008      0.92%     95.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3813889      0.59%     96.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22245365      3.45%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    456295445     70.39%     70.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     93190134     14.38%     84.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     33049230      5.10%     89.86% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15421896      2.38%     92.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10834364      1.67%     93.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6534810      1.01%     94.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      6130401      0.95%     95.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3914098      0.60%     96.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22871827      3.53%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    644213743                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           439656238                       # Number of instructions committed
-system.cpu1.commit.committedOps             516745942                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    648242205                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           450050330                       # Number of instructions committed
+system.cpu1.commit.committedOps             528721496                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     157703093                       # Number of memory references committed
-system.cpu1.commit.loads                     82440315                       # Number of loads committed
-system.cpu1.commit.membars                    3590265                       # Number of memory barriers committed
-system.cpu1.commit.branches                  97880986                       # Number of branches committed
-system.cpu1.commit.fp_insts                    458119                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                474489741                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            12901444                       # Number of function calls committed.
+system.cpu1.commit.refs                     161909642                       # Number of memory references committed
+system.cpu1.commit.loads                     84824904                       # Number of loads committed
+system.cpu1.commit.membars                    3632926                       # Number of memory barriers committed
+system.cpu1.commit.branches                 100459992                       # Number of branches committed
+system.cpu1.commit.fp_insts                    451058                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                485698001                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13255700                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       357849627     69.25%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1084383      0.21%     69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           49292      0.01%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        59547      0.01%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.48% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       82440315     15.95%     85.44% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      75262778     14.56%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       365572080     69.14%     69.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1129275      0.21%     69.36% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           50278      0.01%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        60179      0.01%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       84824904     16.04%     85.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      77084738     14.58%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        516745942                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22245365                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1211389031                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1199768965                       # The number of ROB writes
-system.cpu1.timesIdled                        3993228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       26295838                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 52679663676                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  439656238                       # Number of Instructions Simulated
-system.cpu1.committedOps                    516745942                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.554826                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.554826                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.643159                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.643159                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               676354635                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              399072274                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   856252                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  508516                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                122966367                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               124089822                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1193194921                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              14876268                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
+system.cpu1.commit.op_class_0::total        528721496                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22871827                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1229476063                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1229500763                       # The number of ROB writes
+system.cpu1.timesIdled                        4141402                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       28544446                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 48806249668                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  450050330                       # Number of Instructions Simulated
+system.cpu1.committedOps                    528721496                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.533857                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.533857                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.651951                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.651951                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               691759463                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              409243112                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   834045                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  529652                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                125054676                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               126221670                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1204731271                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              14298109                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1907,11 +1912,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230948                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230948                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353732                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353738                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1928,104 +1933,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334224                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334224                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492144                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492168                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             47821000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25458500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy              172500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            40147500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy              127000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           566083715                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           565671459                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer28.occupancy               45000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147708000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147714000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115455                       # number of replacements
-system.iocache.tags.tagsinuse               10.418427                       # Cycle average of tags in use
+system.iocache.tags.replacements               115458                       # number of replacements
+system.iocache.tags.tagsinuse               10.422741                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13100950746000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     5.907029                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     4.511398                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.369189                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.281962                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651152                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13100980146000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     5.902457                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     4.520285                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.368904                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.282518                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651421                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039623                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039623                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039650                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8810                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8847                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8810                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8850                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8810                       # number of overall misses
-system.iocache.overall_misses::total             8850                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1682627953                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1687696953                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
+system.iocache.overall_misses::total             8853                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1698093507                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1703163007                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13827060762                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13827060762                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1682627953                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1688047953                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1682627953                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1688047953                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13865016452                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13865016452                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1698093507                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1703514007                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1698093507                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1703514007                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8810                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8847                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8810                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8850                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8810                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8850                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2039,55 +2044,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 190990.687060                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 190764.886741                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 192680.529559                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 192447.797401                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129631.935442                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129631.935442                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 190990.687060                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 190739.881695                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 190990.687060                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 190739.881695                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34328                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.778932                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129987.778932                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 192680.529559                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 192422.230543                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 192680.529559                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 192422.230543                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         37009                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3540                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3636                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.697175                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.178493                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8810                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8847                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8810                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8850                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8810                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8850                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1242127953                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1245346953                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1257443507                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1260663007                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8493860762                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8493860762                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1242127953                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1245547953                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1242127953                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1245547953                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8531816452                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8531816452                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1257443507                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1260864007                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1257443507                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1260864007                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2101,308 +2106,312 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140990.687060                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 140764.886741                       # average ReadReq mshr miss latency
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+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142680.529559                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 142447.797401                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79631.935442                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79631.935442                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 140990.687060                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140739.881695                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 140990.687060                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140739.881695                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79987.778932                       # average WriteLineReq mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 142680.529559                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 142422.230543                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1323890                       # number of replacements
-system.l2c.tags.tagsinuse                65259.173207                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   49503955                       # Total number of references to valid blocks.
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-system.l2c.tags.avg_refs                    35.693961                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              22417690500                       # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0.dtb.walker   177.543359                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   251.636127                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3743.427577                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    11664.257926                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   184.830913                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   267.828045                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3663.308299                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     9857.059987                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu0.data    10777.196597                       # Average occupied blocks per requestor
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-system.l2c.ReadReq_misses::cpu1.itb.walker         2046                       # number of ReadReq misses
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+system.l2c.WritebackDirty_hits::total         8016148                       # number of WritebackDirty hits
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 system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
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 system.l2c.SCUpgradeReq_miss_latency::cpu0.data        81000                       # number of SCUpgradeReq miss cycles
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783778                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.782806                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 138611.111111                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137894.761242                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 136672.043011                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 40951.642693                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 41077.702230                       # average UpgradeReq miss latency
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+system.l2c.InvalidateReq_miss_latency::cpu0.data  37193130000                       # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data  41637080500                       # number of InvalidateReq miss cycles
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+system.l2c.WritebackClean_accesses::total     16001128                       # number of WritebackClean accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu1.data        22595                       # number of UpgradeReq accesses(hits+misses)
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+system.l2c.ReadCleanReq_accesses::total      16004890                       # number of ReadCleanReq accesses(hits+misses)
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+system.l2c.InvalidateReq_accesses::cpu0.data       604108                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       626069                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1230177                       # number of InvalidateReq accesses(hits+misses)
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+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004200                       # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004312                       # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784554                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.784632                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.166667                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.400000                       # miss rate for SCUpgradeReq accesses
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+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005911                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005703                       # miss rate for ReadCleanReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.041979                       # miss rate for ReadSharedReq accesses
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+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.428367                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.412756                       # miss rate for InvalidateReq accesses
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+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41670.925707                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 41032.750118                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        81000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149628.885690                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 149637.238009                       # average ReadExReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135121.579277                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 135318.671261                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140392.660424                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140942.832224                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 140662.469133                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 155654.928974                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 155047.531143                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 155340.143907                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138611.111111                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138311.000453                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 146218.083551                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 145119.633734                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2411,298 +2420,298 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1116813                       # number of writebacks
-system.l2c.writebacks::total                  1116813                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           12                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           34                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker           16                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           24                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                86                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks             1112675                       # number of writebacks
+system.l2c.writebacks::total                  1112675                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           14                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           25                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            9                       # number of ReadReq MSHR hits
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+system.l2c.ReadReq_mshr_hits::total                82                       # number of ReadReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data            9                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.dtb.walker           12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.itb.walker           34                       # number of demand (read+write) MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
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+system.l2c.ReadSharedReq_mshr_hits::cpu1.data           10                       # number of ReadSharedReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data              9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR hits
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+system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  34797370000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  38955210500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  73752580500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    277338500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    264753500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   5469883500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  55631559000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    294182000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    261573000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst   6003848498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  53556170000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 121759307998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    277338500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    264753500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   5469883500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  55631559000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    294182000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    261573000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst   6003848498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data  53556170000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 121759307998                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2681108500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3129478000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8126836998                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2583747500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3234873998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5818621498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5264856000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6364351998                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  13945458496                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011102                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.010236                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.005957                       # mshr miss rate for ReadReq accesses
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781836                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783778                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.782806                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.125000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.142857                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.240584                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.241067                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.240825                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.006124                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005477                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005806                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.042694                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041500                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.042100                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.400526                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.425616                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.413148                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004528                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011223                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006124                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.087810                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004106                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.010679                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005477                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.087158                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.034071                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004528                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011223                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006124                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.087810                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004106                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.010679                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005477                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.087158                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.034071                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 128099.012743                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70750.643465                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70745.928248                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70748.286186                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.784708                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784554                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.784632                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.272727                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.239872                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.240940                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.240390                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005703                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041580                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041976                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.041776                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.396578                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.428367                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.412756                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011102                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.087412                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.010236                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.086550                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.033812                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011102                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.087412                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.010236                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.086550                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.033812                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 128493.328652                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70758.532423                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70750.324364                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70754.478589                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        71000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139645.561265                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139628.885690                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 139637.238009                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125491.363034                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125126.981732                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125322.326553                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130392.772127                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130944.173004                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130663.179511                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145654.928974                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145047.531143                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145340.143907                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125491.363034                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136172.442949                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125126.981732                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136439.783200                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 135102.313801                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125491.363034                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136172.442949                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125126.981732                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136439.783200                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 135102.313801                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158756.104227                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163072.300006                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 142422.758279                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165967.041590                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157314.632689                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161241.289767                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 162228.507998                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160097.200775                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 149626.989605                       # average overall mshr uncacheable latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70750                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139289.246572                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139817.768615                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 139546.348741                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125707.843481                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131146.367199                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130252.654380                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130701.468233                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145245.642301                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145253.910518                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145250.009355                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136311.100602                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136218.050946                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 135122.369891                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136311.100602                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136218.050946                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 135122.369891                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167674.077548                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176916.614845                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149596.631348                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176268.761086                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169907.768160                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172674.763273                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 171784.651527                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173283.380473                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 158431.511395                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54323                       # Transaction distribution
-system.membus.trans_dist::ReadResp             463989                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::Writeback           1223443                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           213592                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            36616                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           36618                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1014298                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1014298                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        409666                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54325                       # Transaction distribution
+system.membus.trans_dist::ReadResp             460220                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33697                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33697                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1219305                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           210974                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            36812                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           36815                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1010906                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1010906                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        405895                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6856                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4273089                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4402725                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342054                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4744779                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6862                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4252499                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4382141                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341858                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341858                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4723999                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13712                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    163341292                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    163512986                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7254912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7254912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               170767898                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2786                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3094626                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13724                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    162617772                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    162789478                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7248896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7248896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               170038374                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2884                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3081006                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3094626    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3081006    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3094626                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           113794499                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3081006                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           113865000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5590500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5486002                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8281023093                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8251811507                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7728395442                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7689965068                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228381503                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227507173                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2756,60 +2765,61 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     53734904                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     27297777                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         4493                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2110                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2110                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     53750764                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     27303829                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         4497                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2153                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2153                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            2021207                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25124422                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33696                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33696                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          9226509                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict        18644458                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           45658                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            14                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          45672                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2103809                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2103809                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      15994542                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7116774                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1337512                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1230848                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48020569                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31553133                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       908522                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2486966                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              82969190                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1024954048                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1101984346                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3065144                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8363688                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2138367226                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2094185                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         56528569                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.014634                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.120081                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            2028554                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25149235                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33697                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33697                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      9235460                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     16001128                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2638618                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           45748                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          45759                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2096838                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2096838                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      16005202                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      7123570                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1336841                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1230177                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48052512                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31550783                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       914007                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2494586                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              83011888                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2049706496                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1102812070                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3078592                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8396320                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3163993478                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2090247                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         30104268                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.027207                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.162685                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               55701347     98.54%     98.54% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 827222      1.46%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               29285228     97.28%     97.28% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 819040      2.72%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           56528569                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        35506762964                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           30104268                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        51537960463                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1418902                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1443392                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       24036893583                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       24054534227                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       14511308139                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       14512097283                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         525798129                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         529644514                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1444244841                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        1447978944                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   16329                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index 8b7b1b258..42f464c4a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -1,159 +1,159 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.811486                       # Number of seconds simulated
-sim_ticks                                51811486345500                       # Number of ticks simulated
-final_tick                               51811486345500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.771790                       # Number of seconds simulated
+sim_ticks                                51771790334500                       # Number of ticks simulated
+final_tick                               51771790334500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 353733                       # Simulator instruction rate (inst/s)
-host_op_rate                                   415699                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            22175355428                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 671232                       # Number of bytes of host memory used
-host_seconds                                  2336.44                       # Real time elapsed on the host
-sim_insts                                   826478524                       # Number of instructions simulated
-sim_ops                                     971257944                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 615158                       # Simulator instruction rate (inst/s)
+host_op_rate                                   722932                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            38549866178                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 721636                       # Number of bytes of host memory used
+host_seconds                                  1342.98                       # Real time elapsed on the host
+sim_insts                                   826146401                       # Number of instructions simulated
+sim_ops                                     970885096                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        67136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        69696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2388444                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         32434992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        59968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        68096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2361560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         31996376                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        390912                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             69837180                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2388444                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2361560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4750004                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     60588032                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         15876                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data          4704                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          60608612                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1049                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1089                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             57981                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            506800                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          937                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1064                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             56645                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            499953                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6108                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1131626                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          946688                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             1985                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data              588                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               949261                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1296                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               46099                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              626019                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1157                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1314                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               45580                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              617554                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7545                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1347909                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          46099                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          45580                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              91679                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1169394                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bytes_read::cpu0.dtb.walker        64192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        68416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2225432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         31926704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        62336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        66048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2388572                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         32205016                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        391616                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             69398332                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2225432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2388572                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         4614004                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     60462464                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         15860                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data          4720                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          60483044                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1003                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1069                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             55433                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            498858                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          974                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1032                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             57068                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            503213                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6119                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1124769                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          944726                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             1983                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data              590                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               947299                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1240                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1321                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               42985                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              616681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1204                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1276                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               46137                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              622057                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7564                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1340466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          42985                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          46137                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              89122                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1167865                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                306                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 91                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1169791                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1169394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              46099                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             626326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1157                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1314                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              45580                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             617645                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7545                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2517700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1131626                       # Number of read requests accepted
-system.physmem.writeReqs                       949261                       # Number of write requests accepted
-system.physmem.readBursts                     1131626                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     949261                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 72380992                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     43072                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  60608832                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  69837180                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               60608612                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      673                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         139894                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               75334                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               78749                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               69239                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               66964                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               64795                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               72549                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               64584                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               63831                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               65287                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              109012                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              67637                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              66460                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              64061                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              68282                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              66426                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              67743                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61340                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               64755                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               59195                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               59472                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               56881                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               61983                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               56876                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               57630                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               57576                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               59174                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              59811                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              59738                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              56644                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              59454                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              57794                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              58690                       # Per bank write bursts
+system.physmem.bw_write::total                1168263                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1167865                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1321                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              42985                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             616988                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1204                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1276                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              46137                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             622148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7564                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2508729                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1124769                       # Number of read requests accepted
+system.physmem.writeReqs                       947299                       # Number of write requests accepted
+system.physmem.readBursts                     1124769                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     947299                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 71946624                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     38592                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  60482240                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  69398332                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               60483044                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      603                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2260                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         292556                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               71523                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               69926                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               70289                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               64893                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               64804                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               73543                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               62283                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               61053                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               62184                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              109202                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              70171                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              67486                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              64856                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              71148                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              68907                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              71898                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               59424                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               59953                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60707                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               57771                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               56630                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               62461                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               55190                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               55103                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               55968                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               60498                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              60512                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              59733                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              57588                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              61842                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              59660                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              61995                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          24                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51811483663500                       # Total gap between requests
+system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51771787505500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1088510                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1081653                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 946688                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1104614                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     20819                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       387                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       461                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       554                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       482                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1115                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       273                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      323                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      163                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      117                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      115                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       71                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       47                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 944726                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1098127                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     20478                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       405                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       323                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       445                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       557                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       508                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       660                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      305                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      151                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      156                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      114                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      109                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       90                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       53                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -165,181 +165,180 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      1575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      1529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      1505                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      1483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      1461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      1452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      1432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      1416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      1399                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      1383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     1360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     1350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     1337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     1328                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     1319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    13766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    16565                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    52866                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    53787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    55478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    54927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    55914                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    55859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    57161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    56694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    56942                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    56246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    54836                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::34                      720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      524                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::39                      454                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::42                      355                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::53                      213                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::61                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       68                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       441668                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      301.107402                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     173.680008                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     331.161317                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         174892     39.60%     39.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       107627     24.37%     63.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        38708      8.76%     72.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        22457      5.08%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15602      3.53%     81.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11601      2.63%     83.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10181      2.31%     86.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8589      1.94%     88.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        52011     11.78%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         441668                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         52978                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.347484                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      294.800530                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          52971     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::0                      1566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      1516                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples       441395                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      300.022755                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     172.726713                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     331.159215                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         176110     39.90%     39.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       107371     24.33%     64.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        38199      8.65%     72.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        22075      5.00%     77.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15487      3.51%     81.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11537      2.61%     84.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10154      2.30%     86.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8595      1.95%     88.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        51867     11.75%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         441395                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         52856                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.268333                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      295.103325                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          52849     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            3      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12288-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           52978                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         52978                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.875590                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.137628                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.848761                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                99      0.19%      0.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                70      0.13%      0.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               74      0.14%      0.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15             116      0.22%      0.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           49442     93.33%     94.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             558      1.05%     95.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             385      0.73%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             568      1.07%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             120      0.23%     97.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             330      0.62%     97.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             204      0.39%     98.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              24      0.05%     98.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              95      0.18%     98.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             130      0.25%     98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              29      0.05%     98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              30      0.06%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             454      0.86%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              21      0.04%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              29      0.05%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             141      0.27%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               7      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            29      0.05%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             8      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           52856                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         52856                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.879427                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.143276                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.780491                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3               105      0.20%      0.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                78      0.15%      0.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               62      0.12%      0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              98      0.19%      0.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           49304     93.28%     93.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             574      1.09%     95.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             365      0.69%     95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             594      1.12%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             149      0.28%     97.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             324      0.61%     97.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             209      0.40%     98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              26      0.05%     98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              84      0.16%     98.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             140      0.26%     98.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              28      0.05%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              39      0.07%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             454      0.86%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              24      0.05%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              18      0.03%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             112      0.21%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              11      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            24      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             7      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           52978                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    13921987827                       # Total ticks spent queuing
-system.physmem.totMemAccLat               35127356577                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5654765000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12309.96                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           52856                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    13880638873                       # Total ticks spent queuing
+system.physmem.totMemAccLat               34958751373                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5620830000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12347.50                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31059.96                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.40                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31097.50                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.39                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.35                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.34                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.17                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         7.63                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     914287                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    722010                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.84                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.24                       # Row buffer hit rate for writes
-system.physmem.avgGap                     24898749.27                       # Average gap between requests
-system.physmem.pageHitRate                      78.75                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1737469440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  948024000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4337112000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3098295360                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3384074191680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1302776002665                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29944103839500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34641074934645                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.598406                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49814086335255                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1730099280000                       # Time in different power states
+system.physmem.avgWrQLen                         9.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     908414                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    719391                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.81                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  76.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                     24985563.94                       # Average gap between requests
+system.physmem.pageHitRate                      78.67                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1674025920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  913407000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4198810200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3027708720                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3381481552800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1295576085285                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29926602975000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34613474564925                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.577915                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49785017997770                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1728773800000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    267300073745                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    257997880230                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1601540640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  873856500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4484282400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3038348880                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3384074191680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1289689159770                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29955583526250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34639344906120                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.565015                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49833230042430                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1730099280000                       # Time in different power states
+system.physmem_1.actEnergy                 1662920280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  907347375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4569645600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3096118080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3381481552800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1293349218120                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29928556367250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34613623169505                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.580786                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49788229996275                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1728773800000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    248153702570                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    254784926225                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -393,70 +392,68 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   116564                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               116564                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17888                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        84633                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore           13                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       116551                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean     0.308878                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev    85.298018                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047       116549    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::6144-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       116551                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       102534                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 24964.241130                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21649.871180                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15929.030690                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       101954     99.43%     99.43% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071            9      0.01%     99.44% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          497      0.48%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           10      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           33      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           15      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   115431                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               115431                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17925                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        83577                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       115422                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean     0.155949                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev    52.981983                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047       115421    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       115422                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       101511                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 24872.984209                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21671.671712                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 15716.369374                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       100971     99.47%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          465      0.46%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           13      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           29      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215            9      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       102534                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  -4616128984                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.375220                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     1732065704    -37.52%    -37.52% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    -6348194688    137.52%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  -4616128984                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        84634     82.55%     82.55% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        17888     17.45%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       102522                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       116564                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       101511                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples    118356120                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean   -14.037796                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     1779815204   1503.78%   1503.78% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    -1661459084  -1403.78%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total    118356120                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        83577     82.34%     82.34% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        17925     17.66%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       101502                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       115431                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       116564                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       102522                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       115431                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       101502                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       102522                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       219086                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       101502                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       216933                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    77762076                       # DTB read hits
-system.cpu0.dtb.read_misses                     89597                       # DTB read misses
-system.cpu0.dtb.write_hits                   70744341                       # DTB write hits
-system.cpu0.dtb.write_misses                    26967                       # DTB write misses
-system.cpu0.dtb.flush_tlb                       51819                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    77847569                       # DTB read hits
+system.cpu0.dtb.read_misses                     88672                       # DTB read misses
+system.cpu0.dtb.write_hits                   70757652                       # DTB write hits
+system.cpu0.dtb.write_misses                    26759                       # DTB write misses
+system.cpu0.dtb.flush_tlb                       51778                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              18784                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    511                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   68559                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              18503                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   67979                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  3939                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  3908                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9342                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                77851673                       # DTB read accesses
-system.cpu0.dtb.write_accesses               70771308                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9235                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                77936241                       # DTB read accesses
+system.cpu0.dtb.write_accesses               70784411                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        148506417                       # DTB hits
-system.cpu0.dtb.misses                         116564                       # DTB misses
-system.cpu0.dtb.accesses                    148622981                       # DTB accesses
+system.cpu0.dtb.hits                        148605221                       # DTB hits
+system.cpu0.dtb.misses                         115431                       # DTB misses
+system.cpu0.dtb.accesses                    148720652                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -486,278 +483,277 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    74612                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                74612                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4209                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        65365                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        74612                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          74612    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        74612                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        69574                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 28527.819300                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 25311.121928                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 18888.333067                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        68887     99.01%     99.01% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071            3      0.00%     99.02% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          590      0.85%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           20      0.03%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           39      0.06%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           13      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    74042                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                74042                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4197                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        64819                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        74042                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          74042    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        74042                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        69016                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 28471.542831                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 25336.788819                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 18532.815053                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        68368     99.06%     99.06% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071            2      0.00%     99.06% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          559      0.81%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           14      0.02%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           33      0.05%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        69574                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        69016                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   1705681704                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     1705681704    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   1705681704                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        65365     93.95%     93.95% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         4209      6.05%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        69574                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        64819     93.92%     93.92% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         4197      6.08%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        69016                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        74612                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        74612                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        74042                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        74042                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        69574                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        69574                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       144186                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   414226266                       # ITB inst hits
-system.cpu0.itb.inst_misses                     74612                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        69016                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        69016                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       143058                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   414105554                       # ITB inst hits
+system.cpu0.itb.inst_misses                     74042                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                       51819                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                       51778                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              18784                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    511                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   50668                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              18503                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   50190                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               414300878                       # ITB inst accesses
-system.cpu0.itb.hits                        414226266                       # DTB hits
-system.cpu0.itb.misses                          74612                       # DTB misses
-system.cpu0.itb.accesses                    414300878                       # DTB accesses
-system.cpu0.numCycles                     51812404725                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               414179596                       # ITB inst accesses
+system.cpu0.itb.hits                        414105554                       # DTB hits
+system.cpu0.itb.misses                          74042                       # DTB misses
+system.cpu0.itb.accesses                    414179596                       # DTB accesses
+system.cpu0.numCycles                     51772404432                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   15960                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  413973920                       # Number of instructions committed
-system.cpu0.committedOps                    486522682                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            447282441                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                436837                       # Number of float alu accesses
-system.cpu0.num_func_calls                   24924968                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     62713258                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   447282441                       # number of integer instructions
-system.cpu0.num_fp_insts                       436837                       # number of float instructions
-system.cpu0.num_int_register_reads          647714944                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         354553253                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              705988                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             367364                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           107220558                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          106909360                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    148497129                       # number of memory refs
-system.cpu0.num_load_insts                   77758052                       # Number of load instructions
-system.cpu0.num_store_insts                  70739077                       # Number of store instructions
-system.cpu0.num_idle_cycles              50264604442.745827                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1547800282.254174                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.029873                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.970127                       # Percentage of idle cycles
-system.cpu0.Branches                         92346942                       # Number of branches fetched
+system.cpu0.kern.inst.quiesce                   15961                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  413854142                       # Number of instructions committed
+system.cpu0.committedOps                    486394511                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            447175967                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                436796                       # Number of float alu accesses
+system.cpu0.num_func_calls                   24852805                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     62753360                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   447175967                       # number of integer instructions
+system.cpu0.num_fp_insts                       436796                       # number of float instructions
+system.cpu0.num_int_register_reads          647088270                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         354432965                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              705701                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             368548                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           107266365                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          106966753                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    148595341                       # number of memory refs
+system.cpu0.num_load_insts                   77843031                       # Number of load instructions
+system.cpu0.num_store_insts                  70752310                       # Number of store instructions
+system.cpu0.num_idle_cycles              50229100240.489449                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1543304191.510550                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.029809                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.970191                       # Percentage of idle cycles
+system.cpu0.Branches                         92298416                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                337152189     69.26%     69.26% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1046864      0.22%     69.47% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    47543      0.01%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                 20      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             53325      0.01%     69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.50% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.50% # Class of executed instruction
-system.cpu0.op_class::MemRead                77758052     15.97%     85.47% # Class of executed instruction
-system.cpu0.op_class::MemWrite               70739077     14.53%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                336911536     69.23%     69.23% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1057551      0.22%     69.45% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    48617      0.01%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                 20      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             54899      0.01%     69.47% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
+system.cpu0.op_class::MemRead                77843031     16.00%     85.46% # Class of executed instruction
+system.cpu0.op_class::MemWrite               70752310     14.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 486797091                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          9220536                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.942797                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          287472122                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9221048                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            31.175645                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       5829979500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   266.571154                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   245.371643                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.520647                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.479241                       # Average percentage of cache occupancy
+system.cpu0.op_class::total                 486667985                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          9213148                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.942746                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          287360735                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9213660                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            31.188554                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle       5830459500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   293.957596                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   217.985149                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.574136                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.425752                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999888                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           61                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          402                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1196444585                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1196444585                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     72800073                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     72976033                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      145776106                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67163987                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     66958173                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     134122160                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       185807                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       184713                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       370520                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       162919                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       167025                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       329944                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1640826                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1634541                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3275367                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1783142                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1773309                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3556451                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    139964060                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    139934206                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       279898266                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    140149867                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    140118919                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      280268786                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2404547                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2404611                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      4809158                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       998419                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       959819                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1958238                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       571068                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       532615                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1103683                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       611544                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       610003                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1221547                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       143187                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       139519                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       282706                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses       1195960121                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1195960121                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     72895855                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     72819187                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      145715042                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     67181478                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     66888003                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     134069481                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186279                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       186038                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       372317                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       164783                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data       168129                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       332912                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1645519                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1628369                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3273888                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1788293                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1767339                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      3555632                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    140077333                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    139707190                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       279784523                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    140263612                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    139893228                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      280156840                       # number of overall hits
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+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       562095                       # number of SoftPFReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total      1102084                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       607610                       # number of WriteLineReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       139766                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       283362                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3402966                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      3364430                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6767396                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3974034                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      3897045                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      7871079                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41475189000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  40798417000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  82273606000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33407894500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  32524052000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  65931946500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  36223199500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  36925470000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  73148669500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2177820000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2134271000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4312091000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data      3388997                       # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::cpu0.data      3951092                       # number of overall misses
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+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40954472000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  41182021500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  82136493500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33182162500                       # number of WriteReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total  65690096500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  36148226000                       # number of WriteLineReq miss cycles
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+system.cpu0.dcache.WriteLineReq_miss_latency::total  73075691500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2158365000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2163537000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4321902000                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        82000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  74883083500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  73322469000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 148205552500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  74883083500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  73322469000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 148205552500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     75204620                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     75380644                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    150585264                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     68162406                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     67917992                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    136080398                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       756875                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       717328                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1474203                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       774463                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       777028                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1551491                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1784013                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1774060                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3558073                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1783142                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1773310                       # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.demand_accesses::cpu0.data    143367026                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    143298636                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    286665662                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    144123901                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    144015964                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    288139865                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031973                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031900                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.031936                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014648                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014132                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.014390                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.754508                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.742499                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.748664                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.789636                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.785046                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.787337                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu0.data  74136634500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  73689955500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 147826590000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  74136634500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  73689955500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 147826590000                       # number of overall miss cycles
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+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       772393                       # number of WriteLineReq accesses(hits+misses)
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+system.cpu0.dcache.LoadLockedReq_accesses::total      3557250                       # number of LoadLockedReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031844                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032001                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.031923                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014542                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014250                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.014396                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.751088                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.743759                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747479                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.786659                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.784202                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.785425                       # miss rate for WriteLineReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.080261                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.078644                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079455                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.079047                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079658                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023736                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023478                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.023607                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027574                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027060                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.027317                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17248.649746                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16966.743062                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17107.694528                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33460.796019                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33885.609683                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 33669.015973                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59232.368399                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 60533.259672                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59881.993489                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15209.620985                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15297.350182                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15252.916457                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023622                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023583                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.023603                       # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027219                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.027308                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17081.060070                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17106.793199                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17093.952595                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33471.928989                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33618.626171                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 33544.364387                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59492.480374                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 60440.322338                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59967.709653                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15030.815622                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15479.708942                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15252.228598                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22005.239988                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21793.429793                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 21899.937953                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18843.090799                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18814.888974                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18829.127811                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21875.686081                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21838.519182                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 21857.142984                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18763.580929                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18825.832333                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18794.561034                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -766,216 +762,216 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7220092                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7220092                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        12855                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         9702                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        22557                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        11438                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         9844                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21282                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        33704                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        33408                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        67112                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        24293                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data        19546                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        43839                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        24293                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data        19546                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        43839                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2391692                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2394909                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      4786601                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       986981                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       949975                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1936956                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       570124                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       531812                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1101936                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       611544                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       610003                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1221547                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       109483                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       106111                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       215594                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7212950                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7212950                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        11283                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        11037                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        22320                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        11488                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         9712                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21200                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        33167                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        33718                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        66885                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        22771                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data        20749                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        43520                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        22771                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data        20749                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        43520                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2386371                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2396312                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      4782683                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       979855                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       957250                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1937105                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       561145                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       539145                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1100290                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       607610                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       610974                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1218584                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       110429                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       106048                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       216477                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3378673                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3344884                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      6723557                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      3948797                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      3876696                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      7825493                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16577                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17124                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33701                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16927                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        16781                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33504                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        33905                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67409                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38337908500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  37823855000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  76161763500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31904413500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31123658000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  63028071500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10925929500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   9736959500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20662889000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  35611655500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  36315467000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  71927122500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1499957000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1452847000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2952804000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3366226                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3353562                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      6719788                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      3927371                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      3892707                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      7820078                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16580                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17120                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33700                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16850                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        16857                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33430                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        33977                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67407                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  37889939000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  38156301500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  76046240500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31683288500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31094174500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  62777463000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10445512500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10132014500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20577527000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  35540616000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  36316491500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  71857107500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1500809000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1468573500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2969382500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        81000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  70242322000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  68947513000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 139189835000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  81168251500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  78684472500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 159852724000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2837606500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2994256500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5831863000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2838720500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2985129500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5823850000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5676327000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5979386000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11655713000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031802                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031771                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031787                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014480                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013987                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014234                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.753260                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.741379                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.747479                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.789636                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.785046                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787337                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061369                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059813                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060593                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  69573227500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  69250476000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 138823703500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  80018740000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  79382490500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 159401230500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3026868000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3173397500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6200265500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3017135500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3200441000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6217576500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6044003500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6373838500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12417842000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031694                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031855                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031774                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014373                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014107                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014241                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.749819                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.742596                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746262                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.786659                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.784202                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.785425                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061723                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059977                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060855                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023567                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023342                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023454                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027399                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026919                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.027159                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16029.617735                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15793.441421                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15911.450213                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32325.256008                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32762.607437                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32539.753872                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19164.128330                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18309.025558                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18751.442008                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58232.368399                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59533.259672                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58881.993489                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13700.364440                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13691.766169                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13696.132545                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023464                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023438                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023451                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027233                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027069                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.027151                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15877.639730                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15922.927190                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15900.330526                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32334.670436                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32482.814834                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32407.878251                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18614.640601                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18792.744994                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18701.912223                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58492.480374                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59440.322338                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58967.709653                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13590.714396                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13848.196100                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13716.849827                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20789.914265                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20612.826334                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20701.815274                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20555.184655                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20296.786877                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20427.176154                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171177.324003                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174857.305536                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173047.179609                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167703.698234                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177887.462011                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172773.525573                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169422.367479                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176357.056481                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172910.338382                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20668.020359                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20649.827258                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20658.940952                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20374.632292                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20392.618941                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20383.585752                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182561.399276                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185362.003505                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.139466                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179058.486647                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189858.278460                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.503961                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180795.797188                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187592.739206                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184221.846396                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         13375087                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.782407                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          813613327                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         13375599                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            60.828179                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      61699422500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   237.356539                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   274.425868                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.463587                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.535988                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements         13381945                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.782255                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          813274304                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         13382457                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            60.771673                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      61705740500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   277.029971                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   234.752284                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.541074                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.458501                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999575                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          190                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        840364535                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       840364535                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    407513323                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    406100004                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      813613327                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    407513323                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    406100004                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       813613327                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    407513323                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    406100004                       # number of overall hits
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-system.cpu0.icache.ReadReq_misses::cpu0.inst      6712943                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      6662661                       # number of ReadReq misses
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-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  91656187500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  90957016000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 182613203500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  91656187500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  90957016000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 182613203500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  91656187500                       # number of overall miss cycles
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-system.cpu0.icache.overall_miss_latency::total 182613203500                       # number of overall miss cycles
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-system.cpu0.icache.overall_accesses::total    826988931                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016206                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016142                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.016174                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016206                       # miss rate for demand accesses
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-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016206                       # miss rate for overall accesses
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-system.cpu0.icache.overall_miss_rate::total     0.016174                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13653.651982                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13651.755057                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13652.707085                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13653.651982                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13651.755057                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13652.707085                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13653.651982                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13651.755057                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13652.707085                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        840039228                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       840039228                       # Number of data accesses
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+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016198                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016179                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.016189                       # miss rate for ReadReq accesses
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+system.cpu0.icache.overall_miss_rate::total     0.016189                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13625.782307                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.090947                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13650.375843                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13625.782307                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13675.090947                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13650.375843                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13625.782307                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13675.090947                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13650.375843                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -984,60 +980,62 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6712943                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6662661                       # number of ReadReq MSHR misses
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-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6712943                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      6662661                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     13375604                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6712943                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      6662661                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     13375604                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        22063                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        21062                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.writebacks::writebacks     13381945                       # number of writebacks
+system.cpu0.icache.writebacks::total         13381945                       # number of writebacks
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+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6674734                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     13382462                       # number of ReadReq MSHR misses
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+system.cpu0.icache.demand_mshr_misses::cpu1.inst      6674734                       # number of demand (read+write) MSHR misses
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+system.cpu0.icache.overall_mshr_misses::cpu1.inst      6674734                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     13382462                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        22062                       # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        21063                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        22063                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        21062                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        22062                       # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        21063                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  84943244500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  84294355000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 169237599500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  84943244500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  84294355000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 169237599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  84943244500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  84294355000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 169237599500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780495500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   2656027000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5436522500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2780495500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   2656027000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   5436522500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016206                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016142                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016174                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016206                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016142                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.016174                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016206                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016142                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.016174                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12653.651982                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12651.755057                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12652.707085                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12653.651982                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12651.755057                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12652.707085                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12653.651982                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12651.755057                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12652.707085                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126025.268549                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126105.165701                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126064.289855                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126025.268549                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126105.165701                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126064.289855                       # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  84690313500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  84602860500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 169293174000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  84690313500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  84602860500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 169293174000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  84690313500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  84602860500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 169293174000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780591500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   2656208000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5436799500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2780591500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   2656208000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total   5436799500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016198                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016179                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016189                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016198                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016179                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.016189                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016198                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016179                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.016189                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12625.782307                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12675.090947                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12650.375843                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12625.782307                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12675.090947                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12650.375843                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12625.782307                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12675.090947                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12650.375843                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1068,68 +1066,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   117457                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               117457                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17877                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        85465                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore           15                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       117442                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.102178                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    35.016241                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-1023       117441    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   118026                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               118026                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17902                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        85905                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       118017                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.101680                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    34.930834                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-1023       118016    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::11264-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       117442                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       103357                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 25041.496947                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21746.242782                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15395.142756                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       102794     99.46%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          506      0.49%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143            8      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           24      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       103357                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   3996353148                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.606452                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.488536                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1572755204     39.35%     39.35% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     2423597944     60.65%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   3996353148                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        85465     82.70%     82.70% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        17877     17.30%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       103342                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       117457                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total       118017                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       103816                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 25027.404254                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21748.751472                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15644.616464                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       103269     99.47%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071            2      0.00%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          471      0.45%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143            7      0.01%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           35      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           17      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       103816                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples   2951550812                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.475602                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.499404                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1547787704     52.44%     52.44% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     1403763108     47.56%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   2951550812                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        85906     82.75%     82.75% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        17902     17.25%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       103808                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       118026                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       117457                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       103342                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       118026                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       103808                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       103342                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       220799                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       103808                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       221834                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    77889145                       # DTB read hits
-system.cpu1.dtb.read_misses                     90593                       # DTB read misses
-system.cpu1.dtb.write_hits                   70493756                       # DTB write hits
-system.cpu1.dtb.write_misses                    26864                       # DTB write misses
-system.cpu1.dtb.flush_tlb                       51813                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    77737807                       # DTB read hits
+system.cpu1.dtb.read_misses                     91072                       # DTB read misses
+system.cpu1.dtb.write_hits                   70427017                       # DTB write hits
+system.cpu1.dtb.write_misses                    26954                       # DTB write misses
+system.cpu1.dtb.flush_tlb                       51774                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              18879                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    486                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   67533                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              19160                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    483                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   67493                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  3800                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  3798                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9179                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                77979738                       # DTB read accesses
-system.cpu1.dtb.write_accesses               70520620                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     9286                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                77828879                       # DTB read accesses
+system.cpu1.dtb.write_accesses               70453971                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        148382901                       # DTB hits
-system.cpu1.dtb.misses                         117457                       # DTB misses
-system.cpu1.dtb.accesses                    148500358                       # DTB accesses
+system.cpu1.dtb.hits                        148164824                       # DTB hits
+system.cpu1.dtb.misses                         118026                       # DTB misses
+system.cpu1.dtb.accesses                    148282850                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1159,126 +1158,125 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    75165                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                75165                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4147                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        65764                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        75165                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          75165    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        75165                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        69911                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28585.308464                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25361.717379                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18567.806598                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        69206     98.99%     98.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071            3      0.00%     99.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          615      0.88%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           20      0.03%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           34      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           10      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           19      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    75801                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                75801                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4159                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        66376                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        75801                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          75801    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        75801                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        70535                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28466.739916                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25302.677208                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18338.850484                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        69863     99.05%     99.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071            2      0.00%     99.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          592      0.84%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           11      0.02%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           25      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           22      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        69911                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1449365704                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1449365704    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1449365704                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        65764     94.07%     94.07% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         4147      5.93%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        69911                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total        70535                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples   1449734704                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1449734704    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1449734704                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        66376     94.10%     94.10% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         4159      5.90%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        70535                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        75165                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        75165                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        75801                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        75801                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        69911                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        69911                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       145076                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   412762665                       # ITB inst hits
-system.cpu1.itb.inst_misses                     75165                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        70535                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        70535                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       146336                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   412551212                       # ITB inst hits
+system.cpu1.itb.inst_misses                     75801                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                       51813                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                       51774                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              18879                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    486                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   50171                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              19160                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    483                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   50654                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               412837830                       # ITB inst accesses
-system.cpu1.itb.hits                        412762665                       # DTB hits
-system.cpu1.itb.misses                          75165                       # DTB misses
-system.cpu1.itb.accesses                    412837830                       # DTB accesses
-system.cpu1.numCycles                     51810567966                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               412627013                       # ITB inst accesses
+system.cpu1.itb.hits                        412551212                       # DTB hits
+system.cpu1.itb.misses                          75801                       # DTB misses
+system.cpu1.itb.accesses                    412627013                       # DTB accesses
+system.cpu1.numCycles                     51771176237                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  412504604                       # Number of instructions committed
-system.cpu1.committedOps                    484735262                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            445679810                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                461935                       # Number of float alu accesses
-system.cpu1.num_func_calls                   24743870                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     62553122                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   445679810                       # number of integer instructions
-system.cpu1.num_fp_insts                       461935                       # number of float instructions
-system.cpu1.num_int_register_reads          643867148                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         353090786                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              745900                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             389388                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           106633710                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          106335348                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    148371142                       # number of memory refs
-system.cpu1.num_load_insts                   77883866                       # Number of load instructions
-system.cpu1.num_store_insts                  70487276                       # Number of store instructions
-system.cpu1.num_idle_cycles              50277800640.138901                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1532767325.861101                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.029584                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.970416                       # Percentage of idle cycles
-system.cpu1.Branches                         92048959                       # Number of branches fetched
+system.cpu1.committedInsts                  412292259                       # Number of instructions committed
+system.cpu1.committedOps                    484490585                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            445445369                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                462328                       # Number of float alu accesses
+system.cpu1.num_func_calls                   24787523                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     62474042                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   445445369                       # number of integer instructions
+system.cpu1.num_fp_insts                       462328                       # number of float instructions
+system.cpu1.num_int_register_reads          644065931                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         352949314                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              746699                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             388588                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           106522074                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          106212078                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    148153513                       # number of memory refs
+system.cpu1.num_load_insts                   77732872                       # Number of load instructions
+system.cpu1.num_store_insts                  70420641                       # Number of store instructions
+system.cpu1.num_idle_cycles              50233711408.448738                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1537464828.551259                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.029697                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.970303                       # Percentage of idle cycles
+system.cpu1.Branches                         92021257                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                335465896     69.17%     69.17% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1068730      0.22%     69.39% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    49540      0.01%     69.40% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  1      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.40% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             59074      0.01%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
-system.cpu1.op_class::MemRead                77883866     16.06%     85.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite               70487276     14.53%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                335453186     69.20%     69.20% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1057928      0.22%     69.42% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    48471      0.01%     69.43% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  1      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.43% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             57500      0.01%     69.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.44% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.44% # Class of executed instruction
+system.cpu1.op_class::MemRead                77732872     16.03%     85.47% # Class of executed instruction
+system.cpu1.op_class::MemWrite               70420641     14.53%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 485014384                       # Class of executed instruction
-system.iobus.trans_dist::ReadReq                40322                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40322                       # Transaction distribution
+system.cpu1.op_class::total                 484770600                       # Class of executed instruction
+system.iobus.trans_dist::ReadReq                40328                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40328                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
@@ -1297,11 +1295,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231002                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231002                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231014                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231014                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353786                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353798                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1318,104 +1316,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334440                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334440                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334488                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334488                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492360                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492408                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42148500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
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 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565848755                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           565515993                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147762000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147774000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115483                       # number of replacements
-system.iocache.tags.tagsinuse               10.447157                       # Cycle average of tags in use
+system.iocache.tags.replacements               115489                       # number of replacements
+system.iocache.tags.tagsinuse               10.442885                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115499                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115505                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13183753622000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.511463                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.935694                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219466                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.433481                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.652947                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13183784929000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.514154                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.928730                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.219635                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433046                       # Average percentage of cache occupancy
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 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039866                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039866                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039920                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039920                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8837                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8874                       # number of ReadReq misses
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 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8837                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8877                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8837                       # number of overall misses
-system.iocache.overall_misses::total             8877                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1638182519                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1643251519                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8843                       # number of overall misses
+system.iocache.overall_misses::total             8883                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5070500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1656329126                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1661399626                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13826239236                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13826239236                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1638182519                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1643602519                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1638182519                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1643602519                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13864058367                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13864058367                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5421500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1656329126                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1661750626                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5421500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1656329126                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1661750626                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8837                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8874                       # number of ReadReq accesses(hits+misses)
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+system.iocache.ReadReq_accesses::total           8880                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8837                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8877                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8843                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8883                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8837                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8877                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8843                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8883                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1429,55 +1427,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 185377.675569                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 185175.965630                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 187303.983490                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 187094.552477                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129624.233443                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129624.233443                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 185377.675569                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 185152.925425                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 185377.675569                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 185152.925425                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32900                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.796661                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129978.796661                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 187303.983490                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 187070.879883                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 187303.983490                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 187070.879883                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         34559                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3381                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3493                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.730849                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.893788                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8837                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8874                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8843                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8880                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8837                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8877                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8843                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8883                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8837                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8877                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1196332519                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1199551519                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8843                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8883                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1214179126                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1217399626                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8493039236                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8493039236                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1196332519                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1199752519                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1196332519                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1199752519                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8530858367                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8530858367                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3421500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1214179126                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1217600626                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3421500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1214179126                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1217600626                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1491,299 +1489,303 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135377.675569                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 135175.965630                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137303.983490                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 137094.552477                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79624.233443                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79624.233443                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 135377.675569                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 135152.925425                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 135377.675569                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 135152.925425                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79978.796661                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.796661                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 137303.983490                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 137070.879883                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 137303.983490                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 137070.879883                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   991160                       # number of replacements
-system.l2c.tags.tagsinuse                65239.765860                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   41642303                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1053414                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    39.530805                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle              56092424500                       # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0.dtb.walker   111.130764                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   159.764623                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4448.845209                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    10178.786628                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    88.140538                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   147.411941                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4204.768278                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     8150.476748                       # Average occupied blocks per requestor
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 system.l2c.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
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-system.l2c.ReadSharedReq_miss_latency::cpu1.data  13704189500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  28804727000                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data  30754261500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data  31540882000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total  62295143500                       # number of InvalidateReq miss cycles
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-system.l2c.Writeback_accesses::writebacks      7220092                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          7220092                       # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data        20725                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           41573                       # number of UpgradeReq accesses(hits+misses)
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 system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.786055                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.785847                       # miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.786447                       # miss rate for UpgradeReq accesses
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 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
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-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.397414                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.391899                       # miss rate for InvalidateReq accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 135274.070543                       # average ReadReq miss latency
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-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 134607.257204                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137070.958647                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41414.768891                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 41635.445363                       # average UpgradeReq miss latency
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+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.396361                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.392476                       # miss rate for InvalidateReq accesses
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 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132530.554911                       # average ReadSharedReq miss latency
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-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130106.268356                       # average InvalidateReq miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1792,265 +1794,261 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
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-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    116757000                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.inst   4338503000                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::total  73528264000                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu0.inst   4383871500                       # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu1.data  31328312500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  73528264000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2504708000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2630394000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   2392752000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2780206500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  10308060500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2644060000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2792148000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5436208000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2504708000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5274454000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   2392752000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5572354500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  15744268500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005048                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.006891                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004452                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.006666                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.005625                       # mshr miss rate for ReadReq accesses
-system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.785639                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.786055                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.785847                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18508182000                       # number of ReadExReq MSHR miss cycles
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+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   4392680000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   8474653500                       # number of ReadCleanReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  13275834000                       # number of ReadSharedReq MSHR miss cycles
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+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  29105885500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  57473224500                       # number of InvalidateReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu0.data  31999322500                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2504816500                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2959001500                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3006580000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5829935500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2504816500                       # number of overall MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5965581500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  16505916000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004914                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004641                       # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.785735                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.786447                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.786093                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.162935                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.166467                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.164666                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005356                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005341                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005348                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.037023                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.034095                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.035568                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.386397                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.397414                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.391899                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.005048                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.006891                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005356                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.067153                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004452                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.006666                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005341                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.065141                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.027357                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.005048                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.006891                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005356                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.067153                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004452                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.006666                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005341                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.065141                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.027357                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 126613.795603                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70658.373527                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70659.720091                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70659.044995                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.162817                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.163815                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.163310                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.004981                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005394                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005187                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.035065                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.035573                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.035318                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.388570                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.396361                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.392476                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004914                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.006842                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.004981                       # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005394                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.065761                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.027072                       # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.006842                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.004981                       # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005394                       # mshr miss rate for overall accesses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 126667.729279                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70680.375448                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70685.072261                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70682.738625                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120635.414218                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120617.257853                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 120626.415385                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121926.616604                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121926.285024                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121926.451676                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122801.012242                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122530.554911                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122672.201444                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120149.774227                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120106.268356                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120127.742975                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121926.616604                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121543.651452                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121926.285024                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121383.813199                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 121555.417056                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121926.616604                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121543.651452                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121926.285024                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121383.813199                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 121555.417056                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113525.268549                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158677.324003                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113605.165701                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162357.305536                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 134174.114232                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156203.698234                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166387.462011                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161273.525573                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113525.268549                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157427.590735                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113605.165701                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164351.998230                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 142438.240722                       # average overall mshr uncacheable latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120643.039166                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120656.223109                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 120649.571835                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122185.509459                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122001.944174                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122090.292885                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122703.908531                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122702.842091                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122703.372915                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120150.186998                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120189.809882                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120170.249757                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122185.509459                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121481.969037                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122001.944174                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121502.712249                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 121596.923925                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122185.509459                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121481.969037                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122001.944174                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121502.712249                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 121596.923925                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170038.721351                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172838.872664                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138964.926782                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167558.189911                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178357.952186                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.192453                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168788.438528                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175577.052123                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 149331.560091                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               76826                       # Transaction distribution
-system.membus.trans_dist::ReadResp             378489                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33708                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33708                       # Transaction distribution
-system.membus.trans_dist::Writeback            946688                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           157044                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            33236                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76825                       # Transaction distribution
+system.membus.trans_dist::ReadResp             374618                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       944726                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           152734                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            33164                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           33237                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            790266                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           790266                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        301663                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           33165                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            787274                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           787274                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        297793                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6928                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3314453                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3444143                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340891                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       340891                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3785034                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6924                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3294284                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3423970                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340925                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       340925                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3764895                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13856                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    123230496                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    123400318                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7215296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7215296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               130615614                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3426                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2449027                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    122665376                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    122835190                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7216000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7216000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               130051190                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3421                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2435800                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2449027    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2435800    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2449027                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           107350000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2435800                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           106891000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5290500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5617000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          6222696821                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          6213973567                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6001448560                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5964440131                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228378003                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227489060                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
 system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
@@ -2104,60 +2102,61 @@ system.realview.realview_io.osc_peripheral.clock        41667
 system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
 system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
 system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     45764335                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     23167677                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1751                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2649                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2649                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     45763569                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     23167437                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1754                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2234                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2234                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            1182601                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          20663192                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33708                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33708                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          8166804                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict        15533735                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           41576                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            1181074                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          20663813                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33707                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33707                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      8157694                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     13380350                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2156668                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           41465                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          41577                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1895383                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1895383                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      13375604                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6113005                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1328211                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1221547                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     40210956                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27881321                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       758327                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1083325                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              69933929                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    856211156                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    974300010                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2541024                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3345992                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             1836398182                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1592965                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         47672379                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.011257                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.105498                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp          41466                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1895643                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1895643                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      13382462                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6108330                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1325248                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1218584                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     40231524                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27858913                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       757060                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1077336                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              69924833                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1712992468                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    973558114                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2529304                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3311872                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2692391758                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1591852                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         25069303                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.021336                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.144501                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               47135748     98.87%     98.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 536631      1.13%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               24534434     97.87%     97.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 534869      2.13%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           47672379                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        30462031500                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           25069303                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        43835486500                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1592884                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1550881                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       20106531000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       20116818000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       12681402468                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       12673228476                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         440699000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         440897000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         665076000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         663352000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index d26a43093..370583b3e 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,134 +1,134 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.144266                       # Number of seconds simulated
-sim_ticks                                5144265998000                       # Number of ticks simulated
-final_tick                               5144265998000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.152315                       # Number of seconds simulated
+sim_ticks                                5152314519000                       # Number of ticks simulated
+final_tick                               5152314519000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 171354                       # Simulator instruction rate (inst/s)
-host_op_rate                                   338701                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2161855241                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 817304                       # Number of bytes of host memory used
-host_seconds                                  2379.56                       # Real time elapsed on the host
-sim_insts                                   407746267                       # Number of instructions simulated
-sim_ops                                     805959101                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 171705                       # Simulator instruction rate (inst/s)
+host_op_rate                                   339400                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2173929918                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 815744                       # Number of bytes of host memory used
+host_seconds                                  2370.05                       # Real time elapsed on the host
+sim_insts                                   406948645                       # Number of instructions simulated
+sim_ops                                     804394656                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         3968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         4096                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1040896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10728128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1035840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10724032                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11801664                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1040896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1040896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9535488                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9535488                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           62                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11792640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1035840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1035840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9542144                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9542144                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           64                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16264                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             167627                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             167563                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                184401                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          148992                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               148992                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            771                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                184260                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149096                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149096                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            795                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               202341                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2085454                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5511                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2294140                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          202341                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             202341                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1853615                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1853615                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1853615                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           771                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               201044                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2081401                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2288804                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          201044                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             201044                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1852011                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1852011                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1852011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           795                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              202341                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2085454                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5511                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4147754                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        184401                       # Number of read requests accepted
-system.physmem.writeReqs                       148992                       # Number of write requests accepted
-system.physmem.readBursts                      184401                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     148992                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11790400                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11264                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9534208                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11801664                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9535488                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      176                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst              201044                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2081401                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5503                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4140816                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        184260                       # Number of read requests accepted
+system.physmem.writeReqs                       149096                       # Number of write requests accepted
+system.physmem.readBursts                      184260                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     149096                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11779776                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     12864                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9541120                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11792640                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9542144                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      201                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          48430                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11512                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10865                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12624                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11646                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11360                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11063                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11424                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11380                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11354                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10854                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10623                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11335                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12163                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12460                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11874                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11688                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9762                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9087                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9770                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9357                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9485                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8994                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9154                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8718                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8812                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9056                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8954                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9300                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9801                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9709                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9528                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9485                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          58140                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11261                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10600                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12322                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11592                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11482                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10950                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11082                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11124                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10622                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11032                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11540                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11373                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12384                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12480                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11990                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              12225                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9586                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9015                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9694                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9483                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9592                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9320                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                9057                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                9053                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8752                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9410                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9210                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8755                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9657                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9381                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9483                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9632                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5144265948500                       # Total gap between requests
+system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5152314469500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  184401                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  184260                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 148992                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    169976                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11589                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1867                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       474                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        53                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        39                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 149096                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    169844                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11463                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1944                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       460                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        40                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        34                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        37                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -156,112 +156,114 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     8228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     8294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     9520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8743                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9904                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    10060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    10062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    11631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7698                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       21                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        73109                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      291.681517                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.230147                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     313.360710                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          28156     38.51%     38.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17755     24.29%     62.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7676     10.50%     73.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4351      5.95%     79.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2926      4.00%     83.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2405      3.29%     86.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1356      1.85%     88.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1112      1.52%     89.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7372     10.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          73109                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7269                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.343238                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      563.383377                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7268     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2961                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     8310                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     8291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     9451                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9957                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     9931                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    11713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8611                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7912                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      194                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       38                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        73146                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      291.483225                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.242867                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     313.005738                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          28143     38.48%     38.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17778     24.30%     62.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7759     10.61%     73.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4281      5.85%     79.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2977      4.07%     83.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2397      3.28%     86.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1373      1.88%     88.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1102      1.51%     89.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7336     10.03%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          73146                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7286                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.261872                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      562.739811                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7285     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7269                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7269                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.494153                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.676401                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.977803                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6209     85.42%     85.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             177      2.43%     87.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.43%     88.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             190      2.61%     90.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              15      0.21%     91.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             151      2.08%     93.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             110      1.51%     94.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               9      0.12%     94.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              21      0.29%     95.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              27      0.37%     95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.07%     95.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               5      0.07%     95.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             236      3.25%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               8      0.11%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               6      0.08%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              36      0.50%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               3      0.04%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.07%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.03%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            15      0.21%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.03%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7269                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2113024695                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5567243445                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    921125000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11469.80                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7286                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7286                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.461158                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.651895                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.024155                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6243     85.68%     85.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             165      2.26%     87.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              39      0.54%     88.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             177      2.43%     90.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              22      0.30%     91.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             151      2.07%     93.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             106      1.45%     94.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              11      0.15%     94.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              24      0.33%     95.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              33      0.45%     95.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               7      0.10%     95.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.10%     95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             220      3.02%     98.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.05%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.12%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              29      0.40%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               2      0.03%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             6      0.08%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.03%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.01%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.04%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            18      0.25%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7286                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2105191048                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5556297298                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    920295000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11437.59                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30219.80                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30187.59                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
@@ -271,298 +273,298 @@ system.physmem.busUtil                           0.03                       # Da
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.39                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     150283                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    109804                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.58                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15430035.87                       # Average gap between requests
-system.physmem.pageHitRate                      78.05                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  271774440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  148289625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 716609400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                481638960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           335997963600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           133079069070                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2969819271000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3440514616095                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.806670                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4940481054222                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    171778100000                       # Time in different power states
+system.physmem.avgWrQLen                        22.81                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     150243                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    109749                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.63                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.61                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15455892.41                       # Average gap between requests
+system.physmem.pageHitRate                      78.04                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  269634960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  147122250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 705213600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                484704000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           336523814640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           132970948335                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2974744703250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3445846141035                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.796378                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4948677575724                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    172046940000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32006683778                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31589843276                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  280929600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  153285000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 720337800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                483699600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           335997963600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           133106515425                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2969795195250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3440537926275                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.811201                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4940433568236                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    171778100000                       # Time in different power states
+system.physmem_1.actEnergy                  283348800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  154605000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 730438800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                481334400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           336523814640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           133265512935                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2974486313250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3445925367825                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.811755                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4948236275986                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    172046940000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     32047173014                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     32026607764                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                86512376                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86512376                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            844809                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             79880541                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                77944216                       # Number of BTB hits
+system.cpu.branchPred.lookups                86360408                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86360408                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            844738                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             79711483                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                77808056                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.575974                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1537356                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             178131                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.612104                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1540361                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             177639                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        465431904                       # number of cpu cycles simulated
+system.cpu.numCycles                        465551291                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27316222                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      427457339                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86512376                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79481572                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     433294653                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1774328                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     174290                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                61780                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        197089                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           61                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          797                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8939505                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                424296                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5201                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          461932056                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.826209                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.017418                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27284501                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      426653476                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86360408                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79348417                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     433446162                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1774418                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     139394                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                62229                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        198576                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           56                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          774                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8943748                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                426371                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4516                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          462018901                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.822492                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.015475                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                297044979     64.30%     64.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2134462      0.46%     64.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72126640     15.61%     80.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1546779      0.33%     80.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2100235      0.45%     81.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2289900      0.50%     81.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1474676      0.32%     81.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1857009      0.40%     82.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81357376     17.61%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                297432046     64.38%     64.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2127313      0.46%     64.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72010980     15.59%     80.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1540927      0.33%     80.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2092821      0.45%     81.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2281981      0.49%     81.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1471602      0.32%     82.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1847080      0.40%     82.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81214151     17.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            461932056                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.185875                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.918410                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 23107773                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             281695317                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 147794197                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               8447605                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 887164                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              835787144                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 887164                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 26441875                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               229504552                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       14337084                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 152214834                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              38546547                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              832466923                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                458085                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12798467                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 221946                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               22321415                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           994552862                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1807469855                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1111168371                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               379                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             963838514                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 30714343                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             460142                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         463176                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  43334873                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17067493                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10022220                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1319734                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1116337                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  827242342                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1181786                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 822485271                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            216558                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        22465018                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33877646                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         141871                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     461932056                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.780533                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.400914                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            462018901                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.185501                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.916448                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 22519839                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             281050355                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 150243576                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               7317922                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 887209                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              834205750                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 887209                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 25305856                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               229987183                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       14520771                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 154096496                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              37221386                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              830901673                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                454414                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12058066                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 208457                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               22294259                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           992600987                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1804085973                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1109069164                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               286                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             961883524                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 30717461                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             460427                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         463529                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  38187587                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17040256                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10018392                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1266986                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1072258                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  825691253                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1151613                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 820808364                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            215045                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        22448205                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33824600                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         141893                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     462018901                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.776569                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.399860                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           278202681     60.23%     60.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13844974      3.00%     63.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9781174      2.12%     65.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7532969      1.63%     66.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            73227075     15.85%     82.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4827596      1.05%     83.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72754467     15.75%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1183000      0.26%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              578120      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           278841075     60.35%     60.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13664119      2.96%     63.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             9689206      2.10%     65.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6979280      1.51%     66.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            74151695     16.05%     82.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4284933      0.93%     83.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72644295     15.72%     99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1183606      0.26%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              580692      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       461932056                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       462018901                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2482095     76.42%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 605940     18.66%     95.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                160087      4.93%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1922566     72.06%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     72.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 586085     21.97%     94.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                159449      5.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            284904      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             794458238     96.59%     96.63% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               149904      0.02%     96.65% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                126188      0.02%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 113      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18188915      2.21%     98.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9277009      1.13%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            284230      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             792921370     96.60%     96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               149961      0.02%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                126332      0.02%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                  89      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18051625      2.20%     98.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9274757      1.13%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              822485271                       # Type of FU issued
-system.cpu.iq.rate                           1.767144                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3248122                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003949                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2110366769                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         850901074                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    818087590                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 508                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                586                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          178                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              825448239                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     250                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1862376                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              820808364                       # Type of FU issued
+system.cpu.iq.rate                           1.763089                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2668100                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003251                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2106518335                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         849303097                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    816525348                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 438                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                438                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          154                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              823192025                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     209                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1863548                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3081864                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14686                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14021                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1600056                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3085191                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14446                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13942                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1597044                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2207186                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         68323                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2095832                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         68625                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 887164                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               205274699                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              15795611                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           828424128                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            165882                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17067493                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10022220                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             692366                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 393655                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              14549719                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14021                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         476392                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       506422                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               982814                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             820971747                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17818623                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1389098                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 887209                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               206158213                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              15645218                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           826842866                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            165190                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17040277                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10018392                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             682629                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 383889                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              14436572                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13942                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         477389                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       506444                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               983833                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             819298071                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17680302                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1386078                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     26886211                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83147027                       # Number of branches executed
-system.cpu.iew.exec_stores                    9067588                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.763892                       # Inst execution rate
-system.cpu.iew.wb_sent                      820497311                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     818087768                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 639862073                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1048693225                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     26745461                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 82993620                       # Number of branches executed
+system.cpu.iew.exec_stores                    9065159                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.759845                       # Inst execution rate
+system.cpu.iew.wb_sent                      818824421                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     816525502                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 638690631                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1046712832                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.757696                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610152                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.753889                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610187                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        22343285                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1039914                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            855258                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    458562995                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.757576                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.649246                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        22323770                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1009720                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            855337                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    458653605                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.753817                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.647498                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    287777749     62.76%     62.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11132608      2.43%     65.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3641047      0.79%     65.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74579710     16.26%     82.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2448796      0.53%     82.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1627078      0.35%     83.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1001834      0.22%     83.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70969693     15.48%     98.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5384480      1.17%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    288196518     62.84%     62.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11088839      2.42%     65.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3639702      0.79%     66.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74471288     16.24%     82.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2429938      0.53%     82.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1624365      0.35%     83.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1000566      0.22%     83.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     70851536     15.45%     98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5350853      1.17%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    458562995                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407746267                       # Number of instructions committed
-system.cpu.commit.committedOps              805959101                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    458653605                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            406948645                       # Number of instructions committed
+system.cpu.commit.committedOps              804394656                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22407791                       # Number of memory references committed
-system.cpu.commit.loads                      13985627                       # Number of loads committed
-system.cpu.commit.membars                      468163                       # Number of memory barriers committed
-system.cpu.commit.branches                   82155343                       # Number of branches committed
+system.cpu.commit.refs                       22376433                       # Number of memory references committed
+system.cpu.commit.loads                      13955085                       # Number of loads committed
+system.cpu.commit.membars                      448031                       # Number of memory barriers committed
+system.cpu.commit.branches                   82000673                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 734813827                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155420                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       171757      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        783115943     97.17%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144574      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121605      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 733377152                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155590                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       171815      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        781582591     97.16%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          144575      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121813      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
@@ -589,230 +591,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13983042      1.73%     98.96% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8422164      1.04%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13952498      1.73%     98.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8421348      1.05%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         805959101                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5384480                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1281402583                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1659991505                       # The number of ROB writes
-system.cpu.timesIdled                          284256                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         3499848                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9823097505                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407746267                       # Number of Instructions Simulated
-system.cpu.committedOps                     805959101                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.141474                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.141474                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.876060                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.876060                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1090398458                       # number of integer regfile reads
-system.cpu.int_regfile_writes               654801015                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       178                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 415698435                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                321644299                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               264872577                       # number of misc regfile reads
+system.cpu.commit.op_class_0::total         804394656                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5350853                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1279942872                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1656820485                       # The number of ROB writes
+system.cpu.timesIdled                          287895                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         3532390                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9839075158                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   406948645                       # Number of Instructions Simulated
+system.cpu.committedOps                     804394656                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.144005                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.144005                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.874122                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.874122                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1088092002                       # number of integer regfile reads
+system.cpu.int_regfile_writes               653524498                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       154                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 414883395                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                320972082                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               264296844                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 400155                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1656886                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993571                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18963252                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1657398                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.441580                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           1656669                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.992170                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18961321                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1657181                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.441913                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          65644500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993571                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.992170                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999985                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999985                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          87668549                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         87668549                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10819943                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10819943                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8077328                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8077328                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        63083                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         63083                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      18897271                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18897271                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18960354                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18960354                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1800618                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1800618                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       335187                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       335187                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406619                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406619                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2135805                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2135805                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2542424                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2542424                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  29915350500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  29915350500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21131383234                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21131383234                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  51046733734                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  51046733734                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  51046733734                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  51046733734                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12620561                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12620561                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8412515                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8412515                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       469702                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       469702                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21033076                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21033076                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21502778                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21502778                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142673                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.142673                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039844                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039844                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865696                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.865696                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.101545                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.101545                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118237                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118237                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16613.935049                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16613.935049                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63043.564440                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63043.564440                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23900.465508                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23900.465508                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20077.978234                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20077.978234                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       549742                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          87667052                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         87667052                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10819019                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10819019                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8076374                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8076374                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        63037                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         63037                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      18895393                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18895393                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18958430                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18958430                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1802297                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1802297                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       335310                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       335310                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406421                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406421                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2137607                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2137607                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2544028                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2544028                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  30111588500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  30111588500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21132348722                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21132348722                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  51243937222                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  51243937222                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  51243937222                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  51243937222                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12621316                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12621316                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8411684                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8411684                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       469458                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       469458                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21033000                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21033000                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21502458                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21502458                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142798                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.142798                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039862                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039862                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865724                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.865724                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.101631                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.101631                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118313                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118313                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16707.339856                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16707.339856                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63023.317891                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63023.317891                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23972.571769                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23972.571769                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20142.835386                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20142.835386                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       552183                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             52309                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             52307                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.509511                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.556579                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1559463                       # number of writebacks
-system.cpu.dcache.writebacks::total           1559463                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       834370                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       834370                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44863                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44863                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       879233                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       879233                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       879233                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       879233                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       966248                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       966248                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290324                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290324                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403128                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       403128                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1256572                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1256572                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1659700                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1659700                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602897                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.ReadReq_mshr_uncacheable::total       602897                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13882                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        13882                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616779                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total       616779                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14275238000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  14275238000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19179377736                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19179377736                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6821935500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6821935500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33454615736                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  33454615736                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40276551236                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  40276551236                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97793888500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97793888500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2616393000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2616393000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100410281500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100410281500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076561                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076561                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034511                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034511                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858263                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858263                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.writebacks::writebacks      1558965                       # number of writebacks
+system.cpu.dcache.writebacks::total           1558965                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       836189                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       836189                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44847                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        44847                       # number of WriteReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total       881036                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       881036                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       881036                       # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total       966108                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290463                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       290463                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402928                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402928                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1256571                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1256571                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1659499                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1659499                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       573460                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total       573460                       # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13902                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        13902                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       587362                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total       587362                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14275784000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  14275784000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19192933722                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19192933722                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6799517500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6799517500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33468717722                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  33468717722                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40268235222                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  40268235222                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  98146130000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  98146130000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2778950500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2778950500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100925080500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100925080500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076546                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076546                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034531                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034531                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858283                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858283                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059743                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.059743                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077185                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077185                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14773.886207                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14773.886207                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66061.978121                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66061.978121                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16922.504763                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16922.504763                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26623.715741                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26623.715741                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24267.368341                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24267.368341                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.626505                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.626505                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188473.778994                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188473.778994                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.827909                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077177                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077177                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14776.592265                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14776.592265                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66077.034672                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66077.034672                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16875.266797                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16875.266797                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26634.959522                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26634.959522                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24265.296467                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24265.296467                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171147.298853                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171147.298853                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199895.734427                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199895.734427                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171827.732301                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171827.732301                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        86946                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    15.839570                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        92503                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        86961                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.063730                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.839570                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.989973                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.989973                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements        70093                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.821930                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       109512                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        70108                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.562047                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 199860126500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.821930                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988871                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988871                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       449092                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       449092                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92507                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        92507                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92507                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        92507                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92507                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        92507                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        88026                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        88026                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        88026                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        88026                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        88026                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        88026                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1095128000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1095128000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1095128000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total   1095128000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1095128000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total   1095128000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       180533                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       180533                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       180533                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       180533                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       180533                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       180533                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.487590                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.487590                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.487590                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.487590                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.487590                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.487590                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses       432670                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       432670                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       109535                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       109535                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       109535                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       109535                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       109535                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       109535                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71200                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        71200                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71200                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        71200                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71200                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        71200                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    922231500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    922231500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    922231500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    922231500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    922231500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    922231500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       180735                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       180735                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       180735                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       180735                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       180735                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       180735                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.393947                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.393947                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.393947                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.393947                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.393947                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.393947                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12952.689607                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12952.689607                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12952.689607                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12952.689607                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12952.689607                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12952.689607                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -821,180 +824,183 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        22750                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        22750                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        88026                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        88026                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        88026                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        88026                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        88026                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        88026                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1007102000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1007102000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1007102000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1007102000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1007102000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1007102000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.487590                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.487590                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.487590                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.487590                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.487590                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.487590                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        21274                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        21274                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71200                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71200                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71200                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        71200                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71200                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        71200                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    851031500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    851031500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    851031500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    851031500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    851031500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    851031500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.393947                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.393947                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.393947                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.393947                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.393947                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.393947                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11952.689607                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11952.689607                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11952.689607                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            979952                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.399185                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7892668                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            980464                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.049931                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      150322947500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.399185                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994920                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994920                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            977286                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.169987                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7899726                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            977798                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.079098                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      150383300500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.169987                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.994473                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.994473                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          274                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          128                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          126                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9920034                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9920034                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7892668                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7892668                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7892668                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7892668                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7892668                       # number of overall hits
-system.cpu.icache.overall_hits::total         7892668                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1046827                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1046827                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1046827                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1046827                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1046827                       # number of overall misses
-system.cpu.icache.overall_misses::total       1046827                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15679887484                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15679887484                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15679887484                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15679887484                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15679887484                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15679887484                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8939495                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8939495                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8939495                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8939495                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8939495                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8939495                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.117101                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.117101                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.117101                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.117101                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.117101                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.117101                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.489745                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14978.489745                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.489745                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14978.489745                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.489745                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14978.489745                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        13392                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          244                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               457                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    29.304158                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    81.333333                       # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses           9921613                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9921613                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7899726                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7899726                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7899726                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7899726                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7899726                       # number of overall hits
+system.cpu.icache.overall_hits::total         7899726                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1044015                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1044015                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1044015                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1044015                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1044015                       # number of overall misses
+system.cpu.icache.overall_misses::total       1044015                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15702934482                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15702934482                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15702934482                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15702934482                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15702934482                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15702934482                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8943741                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8943741                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8943741                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8943741                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8943741                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8943741                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116731                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.116731                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.116731                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.116731                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.116731                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.116731                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15040.908878                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15040.908878                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15040.908878                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15040.908878                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15040.908878                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15040.908878                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        15272                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          183                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               489                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    31.231084                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    91.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        66288                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        66288                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        66288                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        66288                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        66288                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        66288                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       980539                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       980539                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       980539                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       980539                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       980539                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       980539                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13806283989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13806283989                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13806283989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13806283989                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13806283989                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13806283989                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109686                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109686                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109686                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.109686                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109686                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.109686                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14080.300721                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14080.300721                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14080.300721                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14080.300721                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14080.300721                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14080.300721                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       977286                       # number of writebacks
+system.cpu.icache.writebacks::total            977286                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        66143                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        66143                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        66143                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        66143                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        66143                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        66143                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       977872                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       977872                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       977872                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       977872                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       977872                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       977872                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13831418488                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13831418488                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13831418488                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13831418488                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13831418488                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13831418488                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109336                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109336                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109336                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.109336                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109336                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.109336                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14144.405902                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14144.405902                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14144.405902                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14144.405902                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14144.405902                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14144.405902                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        19284                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.025119                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        17613                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        19298                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     0.912685                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5119738953000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.025119                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376570                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.376570                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.replacements        13564                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.033276                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        24089                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        13580                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.773859                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5119783334000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.033276                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.377080                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.377080                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        95741                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        95741                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        17618                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        17618                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        91534                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        91534                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        24087                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        24087                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        17620                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        17620                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        17620                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        17620                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        20167                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        20167                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        20167                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        20167                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        20167                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        20167                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    233184000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    233184000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    233184000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    233184000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    233184000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    233184000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        37785                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        37785                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        24089                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        24089                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        24089                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        24089                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14452                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        14452                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14452                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        14452                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14452                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        14452                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    176436500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    176436500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    176436500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    176436500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    176436500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    176436500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        38539                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        38539                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        37787                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        37787                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        37787                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        37787                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.533730                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.533730                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.533702                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.533702                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.533702                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.533702                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11562.651857                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11562.651857                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11562.651857                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11562.651857                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11562.651857                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11562.651857                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        38541                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        38541                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        38541                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        38541                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.374997                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.374997                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.374977                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.374977                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.374977                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.374977                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12208.448658                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12208.448658                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12208.448658                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12208.448658                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12208.448658                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12208.448658                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1003,183 +1009,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         3197                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         3197                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        20167                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        20167                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        20167                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        20167                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        20167                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        20167                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    213017000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    213017000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    213017000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    213017000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    213017000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    213017000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.533730                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.533730                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.533702                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.533702                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.533702                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.533702                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10562.651857                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.651857                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10562.651857                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10562.651857                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10562.651857                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10562.651857                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         2638                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         2638                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14452                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14452                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14452                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        14452                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14452                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        14452                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    161984500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    161984500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    161984500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    161984500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    161984500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    161984500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.374997                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.374997                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.374977                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.374977                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.374977                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.374977                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11208.448658                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11208.448658                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11208.448658                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11208.448658                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11208.448658                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11208.448658                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           111670                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64798.131266                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4919632                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           175949                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            27.960557                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           111860                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64806.586551                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4895189                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176141                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            27.791309                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50517.509380                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.940071                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139536                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3193.810391                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.731889                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.770836                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000167                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50665.329006                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    16.461622                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139358                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3133.882078                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 10990.774487                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.773092                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000251                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048734                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.169002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.988741                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64279                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          676                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3413                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5955                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54192                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.980820                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43682151                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43682151                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      1585410                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1585410                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          346                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          346                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       155314                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       155314                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       964131                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       964131                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        75809                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        15497                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1332951                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1424257                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        75809                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        15497                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       964131                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1488265                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2543702                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        75809                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        15497                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       964131                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1488265                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2543702                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1462                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1462                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       132872                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       132872                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16267                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16267                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           62                       # number of ReadSharedReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047819                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.167706                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.988870                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64281                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          693                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3360                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6102                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54081                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.980850                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43507450                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43507450                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      1582877                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      1582877                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       976140                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       976140                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          326                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          326                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       155489                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       155489                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       961542                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       961542                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        64982                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        12040                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1332604                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1409626                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        64982                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        12040                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       961542                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1488093                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2526657                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        64982                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        12040                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       961542                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1488093                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2526657                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1472                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1472                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       132824                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       132824                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16188                       # number of ReadCleanReq misses
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-system.cpu.l2cache.overall_miss_latency::total  24003381500                       # number of overall miss cycles
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134336.483815                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 144343.750000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker       133000                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134535.013731                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134552.356314                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 144343.750000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134336.483815                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129303.845469                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 129750.079830                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 144343.750000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134336.483815                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129303.845469                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 129750.079830                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1188,8 +1198,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       102325                       # number of writebacks
-system.cpu.l2cache.writebacks::total           102325                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       102429                       # number of writebacks
+system.cpu.l2cache.writebacks::total           102429                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            2                       # number of ReadSharedReq MSHR hits
@@ -1200,181 +1210,182 @@ system.cpu.l2cache.demand_mshr_hits::total            5                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          104                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          104                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1462                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1462                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132872                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       132872                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16264                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16264                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           62                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            9                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            9                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1472                       # number of UpgradeReq MSHR misses
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+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16185                       # number of ReadCleanReq MSHR misses
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+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           64                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35697                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35764                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           62                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35684                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35753                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           64                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16264                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       168569                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       184900                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           62                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16185                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       168508                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       184762                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           64                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16264                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       168569                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       184900                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602897                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602897                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13882                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13882                       # number of WriteReq MSHR uncacheable
-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616779                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616779                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    104470500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    104470500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15652106000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15652106000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2021465000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2021465000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      8519000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       629500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4471847000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4480995500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8519000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       629500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2021465000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20123953000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  22154566500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8519000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       629500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2021465000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20123953000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  22154566500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90257667000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90257667000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2456737500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2456737500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92714404500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92714404500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16185                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       168508                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       184762                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       573460                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total       573460                       # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13902                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13902                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       587362                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total       587362                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    105285000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    105285000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15659734500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15659734500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2012557000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2012557000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      8598000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       615000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4444414500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4453627500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8598000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       615000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2012557000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20104149000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  22125919000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8598000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       615000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2012557000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20104149000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  22125919000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90977838000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90977838000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2619015000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2619015000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  93596853000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  93596853000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808628                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808628                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461063                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461063                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016589                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016589                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000817                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000323                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026082                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024496                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000817                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000323                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016589                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101742                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.067764                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000817                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000323                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016589                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101742                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.067764                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       125900                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       125900                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       125900                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.818687                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818687                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.460694                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.460694                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016554                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016554                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000984                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000415                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026079                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024736                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000984                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000415                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016554                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101719                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.068142                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000984                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000415                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016554                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101719                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.068142                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71525.135870                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71525.135870                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117898.380564                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117898.380564                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124347.049737                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124347.049737                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124549.223742                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124566.539871                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124347.049737                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119306.792556                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119753.623581                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124347.049737                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119306.792556                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119753.623581                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158647.225613                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158647.225613                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188391.238671                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188391.238671                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159351.222926                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159351.222926                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5491514                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2726446                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        94920                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1211                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1211                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5440647                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2708460                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        66609                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1238                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1238                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         602897                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3061240                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13882                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13882                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1734407                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1095490                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       288196                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       288196                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       980539                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1478351                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq         1645                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         573460                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3006256                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13902                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13902                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1731980                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       976140                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       117314                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2288                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2288                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       288324                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       288324                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       977872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1455461                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq         1647                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError            4                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2939753                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6208049                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        41124                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       194511                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           9383437                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62745472                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207643157                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1196736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      6311744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          277897109                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      226924                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      6316816                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.030269                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.203509                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2931742                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6148479                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        31127                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       166003                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           9277351                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    125047680                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207509531                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       939712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5524480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          339021403                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      218907                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3519115                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.019900                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.161788                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            6163711     97.58%     97.58% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             115005      1.82%     99.40% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              38100      0.60%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3460821     98.34%     98.34% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              46556      1.32%     99.67% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              11738      0.33%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6316816                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4646513967                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3519115                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5581131973                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       659789                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       669284                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1472350908                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1468639319                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3097364534                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3067775714                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      30265969                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      21694467                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     132091893                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     106870358                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               222097                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              222097                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57711                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57711                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1645                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1645                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               212021                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              212021                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1647                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1647                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       420172                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       400004                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
@@ -1384,21 +1395,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       464358                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       444236                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3290                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3290                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  562906                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3294                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3294                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  542788                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       210086                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       200002                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
@@ -1408,67 +1419,67 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       238456                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       228398                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6580                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3272852                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3921096                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6588                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3262802                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3986644                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                43000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 6500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy             10458500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy               146500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy              1029000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                77000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                94000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                58500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy                32500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            210087000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            300003000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy             1174000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
+system.iobus.reqLayer11.occupancy              212500                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy            24569000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           241306768                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           241170809                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy             1085500                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           453367000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           433230000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            50170000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1645000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1647000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                47574                       # number of replacements
-system.iocache.tags.tagsinuse                0.116041                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.140720                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4999338704000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116041                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007253                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.007253                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4999394542000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.140720                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008795                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.008795                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1482,14 +1493,14 @@ system.iocache.demand_misses::pc.south_bridge.ide          909
 system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
 system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
 system.iocache.overall_misses::total              909                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144457672                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    144457672                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   6056832096                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   6056832096                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    144457672                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    144457672                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    144457672                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    144457672                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    150240673                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    150240673                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   6073165136                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   6073165136                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    150240673                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    150240673                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    150240673                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    150240673                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
@@ -1506,19 +1517,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 158919.331133                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 158919.331133                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 158919.331133                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           604                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165281.268427                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 165281.268427                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129990.692123                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129990.692123                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165281.268427                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 165281.268427                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165281.268427                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 165281.268427                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs          1090                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   52                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                  104                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    11.615385                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.480769                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1532,14 +1543,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide          909
 system.iocache.demand_mshr_misses::total          909                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::pc.south_bridge.ide          909                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          909                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     99007672                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     99007672                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3720832096                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3720832096                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     99007672                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     99007672                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     99007672                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     99007672                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104790673                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    104790673                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3737165136                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3737165136                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104790673                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    104790673                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104790673                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    104790673                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1548,77 +1559,77 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 108919.331133                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 108919.331133                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115281.268427                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79990.692123                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79990.692123                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115281.268427                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115281.268427                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq              602897                       # Transaction distribution
-system.membus.trans_dist::ReadResp             655826                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13882                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13882                       # Transaction distribution
-system.membus.trans_dist::Writeback            148992                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             9700                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2190                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1729                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            132608                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           132605                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         52937                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1645                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1645                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
+system.membus.trans_dist::ReadReq              573460                       # Transaction distribution
+system.membus.trans_dist::ReadResp             626303                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13902                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13902                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       149096                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             9693                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2236                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1746                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            132555                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           132550                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         52847                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1647                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1647                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            4                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3290                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3290                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464358                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769200                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       484156                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1717730                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141814                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141814                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1862834                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6580                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538397                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18322112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20098965                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3294                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3294                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       444236                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       730488                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       484035                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio            8                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1658767                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141815                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141815                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1803876                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6588                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       228398                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1460973                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18319744                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20009115                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23120585                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1616                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1012128                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.001625                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.040282                       # Request fanout histogram
+system.membus.pkt_size::total                23030743                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1647                       # Total snoops (count)
+system.membus.snoop_fanout::samples            982714                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.001676                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.040904                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 1010483     99.84%     99.84% # Request fanout histogram
-system.membus.snoop_fanout::2                    1645      0.16%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  981067     99.83%     99.83% # Request fanout histogram
+system.membus.snoop_fanout::2                    1647      0.17%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             1012128                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           355014500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              982714                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           338956500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           388301500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           369067500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3290000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3986356                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1012808227                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1013629759                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy               10000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                5500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1645000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            2339356                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2201176288                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2140696281                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           86060868                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           85836693                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
index 41cabb250..aa0c99096 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.225369                       # Number of seconds simulated
-sim_ticks                                5225368810000                       # Number of ticks simulated
-final_tick                               5225368810000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.221365                       # Number of seconds simulated
+sim_ticks                                5221365015000                       # Number of ticks simulated
+final_tick                               5221365015000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 187606                       # Simulator instruction rate (inst/s)
-host_op_rate                                   364338                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6433833901                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1111300                       # Number of bytes of host memory used
-host_seconds                                   812.17                       # Real time elapsed on the host
-sim_insts                                   152367765                       # Number of instructions simulated
-sim_ops                                     295904443                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 248453                       # Simulator instruction rate (inst/s)
+host_op_rate                                   482434                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8587928983                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 826144                       # Number of bytes of host memory used
+host_seconds                                   607.99                       # Real time elapsed on the host
+sim_insts                                   151056354                       # Number of instructions simulated
+sim_ops                                     293314765                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0     11604096                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total           11604096                       # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0      9356928                       # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total         9356928                       # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0       181314                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total              181314                       # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0       146202                       # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total             146202                       # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0      2220723                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total               2220723                       # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0      1790673                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total              1790673                       # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0      4011396                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total              4011396                       # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs                      181314                       # Number of read requests accepted
-system.mem_ctrls.writeReqs                     146202                       # Number of write requests accepted
-system.mem_ctrls.readBursts                    181314                       # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts                   146202                       # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM               11574784                       # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ                   29312                       # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten                 9353152                       # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys                11604096                       # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys              9356928                       # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ                    458                       # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts                    37                       # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0     11629312                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total           11629312                       # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0      9426176                       # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total         9426176                       # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0       181708                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total              181708                       # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0       147284                       # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total             147284                       # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0      2227255                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total               2227255                       # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0      1805309                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total              1805309                       # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0      4032564                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total              4032564                       # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs                      181708                       # Number of read requests accepted
+system.mem_ctrls.writeReqs                     147284                       # Number of write requests accepted
+system.mem_ctrls.readBursts                    181708                       # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts                   147284                       # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM               11602944                       # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ                   26368                       # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten                 9422144                       # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys                11629312                       # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys              9426176                       # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ                    412                       # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts                    33                       # Number of DRAM write bursts merged with an existing one
 system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0             11244                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1             11728                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2             11414                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3             11249                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4             11189                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5             11530                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6             10984                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7             10623                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8             11116                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9             11643                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10            12156                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11            12345                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12            11109                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13            10877                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14            11117                       # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15            10532                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0              9114                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1              9153                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2              9190                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3              9432                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4              9109                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5              9160                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6              8858                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7              8355                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8              8936                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9              9402                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10             9134                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11             9662                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12             9149                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13             9001                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14             9507                       # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15             8981                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0             11315                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1             10810                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2             10914                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3             11597                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4             11232                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5             10763                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6             11930                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7             10887                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8             12498                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9             12229                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10            11811                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11            12012                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12            11054                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13            10768                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14            10809                       # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15            10667                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0             10064                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1              9276                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2              8835                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3              9280                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4              9017                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5              9023                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6              9283                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7              8385                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8              9360                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9              9330                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10             9168                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11             9776                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12             9055                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13             9211                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14             9312                       # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15             8846                       # Per bank write bursts
 system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
 system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
-system.mem_ctrls.totGap                  5225368708000                       # Total gap between requests
+system.mem_ctrls.totGap                  5221364905500                       # Total gap between requests
 system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
 system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6                181314                       # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6                181708                       # Read request sizes (log2)
 system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
 system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6               146202                       # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0                  180784                       # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1                      72                       # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6               147284                       # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0                  181190                       # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1                     106                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
 system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
@@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11                      1                       # Wh
 system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15                   2042                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16                   2789                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17                   8700                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18                   9297                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19                   8795                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20                   9401                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21                   9400                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22                   8618                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23                   9266                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24                   9253                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25                   8672                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26                   8773                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27                   8544                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28                   8651                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29                   8275                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30                   8310                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31                   8383                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32                   8185                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33                    136                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34                    112                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35                     98                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36                     93                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37                     85                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38                     69                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39                     65                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40                     46                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41                     33                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::42                     30                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::43                     18                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::44                     10                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::45                      1                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15                   2024                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16                   2744                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17                   8771                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18                   9315                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19                   8851                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20                   9482                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21                   9472                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22                   8660                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23                   9268                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24                   9345                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25                   8736                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26                   8808                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27                   8668                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28                   8747                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29                   8343                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30                   8394                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31                   8477                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32                   8268                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33                    147                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::34                    120                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::35                    118                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::36                    107                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37                     92                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38                     78                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39                     67                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40                     52                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::41                     36                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::42                     21                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::43                     12                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::44                      9                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::45                      2                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::46                      1                       # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::47                      1                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
@@ -184,349 +184,355 @@ system.mem_ctrls.wrQLenPdf::60                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples        59375                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean    352.469423                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   208.459416                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   350.191620                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127        19259     32.44%     32.44% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255        13965     23.52%     55.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383         6118     10.30%     66.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511         3675      6.19%     72.45% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639         2603      4.38%     76.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767         1985      3.34%     80.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895         1578      2.66%     82.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023         1346      2.27%     85.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151         8846     14.90%    100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total        59375                       # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples         8143                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean      22.209014                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev    312.827272                       # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-1023         8137     99.93%     99.93% # Reads before turning the bus around for writes
+system.mem_ctrls.bytesPerActivate::samples        59927                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean    350.843927                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   206.536657                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   350.281857                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127        19886     33.18%     33.18% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255        13813     23.05%     56.23% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383         6078     10.14%     66.38% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511         3680      6.14%     72.52% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639         2560      4.27%     76.79% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767         2039      3.40%     80.19% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895         1649      2.75%     82.94% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023         1406      2.35%     85.29% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151         8816     14.71%    100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total        59927                       # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples         8212                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean      22.072577                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev    311.491456                       # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-1023         8206     99.93%     99.93% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::1024-2047            3      0.04%     99.96% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total          8143                       # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples         8143                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean      17.947071                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean     17.618146                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev      3.900856                       # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16             6047     74.26%     74.26% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17               20      0.25%     74.51% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18              162      1.99%     76.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19               25      0.31%     76.80% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20               47      0.58%     77.38% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21              486      5.97%     83.35% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22              180      2.21%     85.56% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23               58      0.71%     86.27% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24              619      7.60%     93.87% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25              107      1.31%     95.19% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26                5      0.06%     95.25% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27               26      0.32%     95.57% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28              281      3.45%     99.02% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29                7      0.09%     99.10% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30                5      0.06%     99.16% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31                4      0.05%     99.21% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32                7      0.09%     99.30% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33                4      0.05%     99.35% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::34                1      0.01%     99.36% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::35                2      0.02%     99.39% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::36                5      0.06%     99.45% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::37                7      0.09%     99.53% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::38                4      0.05%     99.58% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::39                8      0.10%     99.68% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::40                5      0.06%     99.74% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::41                1      0.01%     99.75% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::42                2      0.02%     99.78% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::43                3      0.04%     99.82% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::44                4      0.05%     99.86% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::45                4      0.05%     99.91% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::46                3      0.04%     99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::48                1      0.01%     99.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::51                3      0.04%    100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total          8143                       # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat                   1912369249                       # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat              5303419249                       # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat                  904280000                       # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat                     10573.99                       # Average queueing delay per DRAM burst
+system.mem_ctrls.rdPerTurnAround::total          8212                       # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples         8212                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean      17.927545                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean     17.596423                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev      3.937922                       # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16             6145     74.83%     74.83% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17               16      0.19%     75.02% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18              149      1.81%     76.84% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19               20      0.24%     77.08% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20               39      0.47%     77.56% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21              481      5.86%     83.41% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22              195      2.37%     85.79% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23               59      0.72%     86.51% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24              612      7.45%     93.96% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25              113      1.38%     95.34% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26                6      0.07%     95.41% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::27               13      0.16%     95.57% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28              284      3.46%     99.03% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::29                4      0.05%     99.07% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::30                6      0.07%     99.15% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::31                4      0.05%     99.20% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::32                7      0.09%     99.28% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::33                5      0.06%     99.34% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::34                1      0.01%     99.35% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::35                1      0.01%     99.37% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::36                6      0.07%     99.44% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::37                4      0.05%     99.49% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::38                2      0.02%     99.51% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::39                6      0.07%     99.59% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::40                1      0.01%     99.60% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::41                8      0.10%     99.70% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::42                3      0.04%     99.73% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::43                2      0.02%     99.76% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::44                6      0.07%     99.83% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::45                4      0.05%     99.88% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::46                1      0.01%     99.89% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::47                1      0.01%     99.90% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::48                3      0.04%     99.94% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::50                1      0.01%     99.95% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::51                4      0.05%    100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total          8212                       # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat                   1926712996                       # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat              5326012996                       # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat                  906480000                       # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat                     10627.44                       # Average queueing delay per DRAM burst
 system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat                29323.99                       # Average memory access latency per DRAM burst
+system.mem_ctrls.avgMemAccLat                29377.44                       # Average memory access latency per DRAM burst
 system.mem_ctrls.avgRdBW                         2.22                       # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW                         1.79                       # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys                      2.22                       # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys                      1.79                       # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW                         1.80                       # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys                      2.23                       # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys                      1.81                       # Average system write bandwidth in MiByte/s
 system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.mem_ctrls.busUtil                         0.03                       # Data bus utilization in percentage
 system.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      24.23                       # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits                   146726                       # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits                  120897                       # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate                 81.13                       # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate                82.71                       # Row buffer hit rate for writes
-system.mem_ctrls.avgGap                   15954544.84                       # Average gap between requests
-system.mem_ctrls.pageHitRate                    81.84                       # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy                218060640                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy                118981500                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy               701688000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy              468964080                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy         341295633120                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy         139733284410                       # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy         3012647859750                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy           3495184471500                       # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower            668.887692                       # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 5011696826000                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF  174486520000                       # Time in different power states
+system.mem_ctrls.avgWrQLen                      25.95                       # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits                   146991                       # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits                  121598                       # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate                 81.08                       # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate                82.58                       # Row buffer hit rate for writes
+system.mem_ctrls.avgGap                   15870795.96                       # Average gap between requests
+system.mem_ctrls.pageHitRate                    81.75                       # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy                221946480                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                121101750                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy               697686600                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy              474096240                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy         341033724720                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy         139619979810                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy         3010341298500                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy           3492509834100                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            668.889138                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 5007866146000                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF  174352620000                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT   39185363500                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT   39146148500                       # Time in different power states
 system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls_1.actEnergy                230814360                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy                125940375                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy               708981000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy              478042560                       # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy         341295633120                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy         140499040365                       # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy         3011976144000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy           3495314595780                       # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower            668.912595                       # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5010570381500                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF  174486520000                       # Time in different power states
+system.mem_ctrls_1.actEnergy                231101640                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                126097125                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy               716414400                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy              479895840                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy         341033724720                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy         139466264490                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy         3010476136500                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy           3492529634715                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            668.892930                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 5008078591499                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF  174352620000                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT   40311306000                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT   38927077251                       # Time in different power states
 system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                     10450737620                       # number of cpu cycles simulated
+system.cpu0.numCycles                     10442730030                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  133878612                       # Number of instructions committed
-system.cpu0.committedOps                    261396254                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            242945035                       # Number of integer alu accesses
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  100536790                       # Number of instructions committed
+system.cpu0.committedOps                    194797787                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            182088702                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                    48                       # Number of float alu accesses
-system.cpu0.num_func_calls                    2097767                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     24690965                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   242945035                       # number of integer instructions
+system.cpu0.num_func_calls                    1786032                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     17861740                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   182088702                       # number of integer instructions
 system.cpu0.num_fp_insts                           48                       # number of float instructions
-system.cpu0.num_int_register_reads          449858957                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         208812254                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          340614933                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         155369927                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                  48                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           139838702                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          101442019                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     19926036                       # number of memory refs
-system.cpu0.num_load_insts                   12901049                       # Number of load instructions
-system.cpu0.num_store_insts                   7024987                       # Number of store instructions
-system.cpu0.num_idle_cycles              9874541194.502110                       # Number of idle cycles
-system.cpu0.num_busy_cycles              576196425.497890                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.055135                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.944865                       # Percentage of idle cycles
-system.cpu0.Branches                         27504240                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass               196451      0.08%      0.08% # Class of executed instruction
-system.cpu0.op_class::IntAlu                241068901     92.22%     92.30% # Class of executed instruction
-system.cpu0.op_class::IntMult                  118906      0.05%     92.34% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    91754      0.04%     92.38% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                     16      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     92.38% # Class of executed instruction
-system.cpu0.op_class::MemRead                12896145      4.93%     97.31% # Class of executed instruction
-system.cpu0.op_class::MemWrite                7024987      2.69%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads           104545094                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           75102328                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     18441277                       # number of memory refs
+system.cpu0.num_load_insts                   11598406                       # Number of load instructions
+system.cpu0.num_store_insts                   6842871                       # Number of store instructions
+system.cpu0.num_idle_cycles              9945203438.030096                       # Number of idle cycles
+system.cpu0.num_busy_cycles              497526591.969905                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.047643                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.952357                       # Percentage of idle cycles
+system.cpu0.Branches                         20259437                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass               186593      0.10%      0.10% # Class of executed instruction
+system.cpu0.op_class::IntAlu                175972173     90.34%     90.43% # Class of executed instruction
+system.cpu0.op_class::IntMult                  117562      0.06%     90.49% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    85263      0.04%     90.54% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                     16      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.54% # Class of executed instruction
+system.cpu0.op_class::MemRead                11594262      5.95%     96.49% # Class of executed instruction
+system.cpu0.op_class::MemWrite                6842871      3.51%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 261397160                       # Class of executed instruction
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu0.op_class::total                 194798740                       # Class of executed instruction
 system.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu1.numCycles                     10450371427                       # number of cpu cycles simulated
+system.cpu1.numCycles                     10442397548                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   18489153                       # Number of instructions committed
-system.cpu1.committedOps                     34508189                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             33584697                       # Number of integer alu accesses
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu1.committedInsts                   50519564                       # Number of instructions committed
+system.cpu1.committedOps                     98516978                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             91922994                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                    48                       # Number of float alu accesses
-system.cpu1.num_func_calls                     723193                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2490900                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    33584697                       # number of integer instructions
+system.cpu1.num_func_calls                     994306                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      9151225                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    91922994                       # number of integer instructions
 system.cpu1.num_fp_insts                           48                       # number of float instructions
-system.cpu1.num_int_register_reads           67969193                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          27166606                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          171998955                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          78483891                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                  48                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            18719213                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           11481778                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      7779481                       # number of memory refs
-system.cpu1.num_load_insts                    4611241                       # Number of load instructions
-system.cpu1.num_store_insts                   3168240                       # Number of store instructions
-system.cpu1.num_idle_cycles              10364265637.965616                       # Number of idle cycles
-system.cpu1.num_busy_cycles              86105789.034384                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.008239                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.991761                       # Percentage of idle cycles
-system.cpu1.Branches                          3500131                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               130271      0.38%      0.38% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 26481859     76.74%     77.12% # Class of executed instruction
-system.cpu1.op_class::IntMult                   73611      0.21%     77.33% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    48640      0.14%     77.47% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                     16      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     77.47% # Class of executed instruction
-system.cpu1.op_class::MemRead                 4606243     13.35%     90.82% # Class of executed instruction
-system.cpu1.op_class::MemWrite                3168240      9.18%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            52229827                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           37031962                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      8648347                       # number of memory refs
+system.cpu1.num_load_insts                    5505950                       # Number of load instructions
+system.cpu1.num_store_insts                   3142397                       # Number of store instructions
+system.cpu1.num_idle_cycles              10281439289.330288                       # Number of idle cycles
+system.cpu1.num_busy_cycles              160958258.669712                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.015414                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.984586                       # Percentage of idle cycles
+system.cpu1.Branches                         10509152                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               118845      0.12%      0.12% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 89646727     91.00%     91.12% # Class of executed instruction
+system.cpu1.op_class::IntMult                   68401      0.07%     91.19% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    39477      0.04%     91.23% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                     16      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     91.23% # Class of executed instruction
+system.cpu1.op_class::MemRead                 5501755      5.58%     96.81% # Class of executed instruction
+system.cpu1.op_class::MemWrite                3142397      3.19%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  34508880                       # Class of executed instruction
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq               907238                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              907238                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               37562                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              37562                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1829                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1829                       # Transaction distribution
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1740                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1686                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3426                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           52                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6428                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          960                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           46                       # Packet count per connected master and slave (bytes)
+system.cpu1.op_class::total                  98517618                       # Class of executed instruction
+system.iobus.trans_dist::ReadReq               883857                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              883857                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               36766                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              36766                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1833                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1833                       # Transaction distribution
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1736                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1682                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3418                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6154                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          712                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           74                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       943400                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1424                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio          178                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       917434                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1422                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           90                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        21370                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       831224                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          164                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14468                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       811270                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          178                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1807714                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4706                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          404                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            8                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        32826                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          674                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        32826                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         5996                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port           68                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         4602                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        82118                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 1893258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3372                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6852                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           26                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4059                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           23                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1754122                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4888                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          652                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        31650                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          676                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        31738                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12896                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port           70                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         4614                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        87372                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 1844912                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3472                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3364                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6836                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3500                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          356                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           37                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       471700                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         2848                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           89                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       458717                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         2844                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           45                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        10685                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1662442                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          328                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7234                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1622534                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          356                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      2157234                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         2653                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          202                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        16413                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1348                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        16413                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         2998                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          136                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         9201                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        49372                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2213458                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy                43500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      2100077                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          326                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15825                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1352                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        15869                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6448                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          140                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         9225                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        52465                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2159378                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy                43000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 6500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                 7500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy              9139000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy              9039000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               158000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               159000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy               936500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy               945000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                82500                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                85000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                52500                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                51500                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy             21911000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy             21127500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy            471701000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy            458718000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy              1769984                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy              1770984                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy            33004000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy            31828500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.occupancy                2500                       # Layer occupancy (ticks)
 system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            20528000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            20526000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
@@ -534,24 +540,24 @@ system.iobus.reqLayer16.occupancy                9500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           420342217                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           410368779                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy             7349150                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             7668139                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy             1592000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             2491416                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             2481464                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy          2005792963                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy          1948163500                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy            55581972                       # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy            60411500                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2987008                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs          813                       # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
 system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
@@ -561,48 +567,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs            1
 system.ruby.clk_domain.clock                      500                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
-system.ruby.delayHist::samples               11126779                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.431812                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.814704                       # delay histogram for all message
-system.ruby.delayHist                    |    10527775     94.62%     94.62% |        6617      0.06%     94.68% |      590092      5.30%     99.98% |         473      0.00%     99.98% |        1712      0.02%    100.00% |          18      0.00%    100.00% |          91      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                 11126779                       # delay histogram for all message
+system.ruby.delayHist::samples               11180744                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.431770                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.809571                       # delay histogram for all message
+system.ruby.delayHist                    |    10577839     94.61%     94.61% |        2056      0.02%     94.63% |      600268      5.37%     99.99% |         190      0.00%    100.00% |         314      0.00%    100.00% |          12      0.00%    100.00% |          62      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                 11180744                       # delay histogram for all message
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples    200336264                      
-system.ruby.outstanding_req_hist::mean       1.000143                      
-system.ruby.outstanding_req_hist::gmean      1.000099                      
-system.ruby.outstanding_req_hist::stdev      0.011958                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   200307614     99.99%     99.99% |       28650      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total     200336264                      
+system.ruby.outstanding_req_hist::samples    197955014                      
+system.ruby.outstanding_req_hist::mean       1.000129                      
+system.ruby.outstanding_req_hist::gmean      1.000089                      
+system.ruby.outstanding_req_hist::stdev      0.011356                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   197929484     99.99%     99.99% |       25530      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total     197955014                      
 system.ruby.latency_hist::bucket_size             128                      
 system.ruby.latency_hist::max_bucket             1279                      
-system.ruby.latency_hist::samples           200336263                      
-system.ruby.latency_hist::mean               1.335134                      
-system.ruby.latency_hist::gmean              1.041246                      
-system.ruby.latency_hist::stdev              5.048100                      
-system.ruby.latency_hist                 |   200300902     99.98%     99.98% |       26494      0.01%    100.00% |        2841      0.00%    100.00% |        3411      0.00%    100.00% |        1684      0.00%    100.00% |         871      0.00%    100.00% |          17      0.00%    100.00% |          21      0.00%    100.00% |          19      0.00%    100.00% |           3      0.00%    100.00%
-system.ruby.latency_hist::total             200336263                      
+system.ruby.latency_hist::samples           197955013                      
+system.ruby.latency_hist::mean               1.340863                      
+system.ruby.latency_hist::gmean              1.042158                      
+system.ruby.latency_hist::stdev              5.086284                      
+system.ruby.latency_hist                 |   197919444     99.98%     99.98% |       26717      0.01%    100.00% |        2924      0.00%    100.00% |        3327      0.00%    100.00% |        1642      0.00%    100.00% |         886      0.00%    100.00% |           9      0.00%    100.00% |          33      0.00%    100.00% |          23      0.00%    100.00% |           8      0.00%    100.00%
+system.ruby.latency_hist::total             197955013                      
 system.ruby.hit_latency_hist::bucket_size            1                      
 system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples       197654640                      
+system.ruby.hit_latency_hist::samples       195243076                      
 system.ruby.hit_latency_hist::mean                  1                      
 system.ruby.hit_latency_hist::gmean                 1                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |   197654640    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total         197654640                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |   195243076    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total         195243076                      
 system.ruby.miss_latency_hist::bucket_size          128                      
 system.ruby.miss_latency_hist::max_bucket         1279                      
-system.ruby.miss_latency_hist::samples        2681623                      
-system.ruby.miss_latency_hist::mean         26.036867                      
-system.ruby.miss_latency_hist::gmean        20.481431                      
-system.ruby.miss_latency_hist::stdev        35.851511                      
-system.ruby.miss_latency_hist            |     2646262     98.68%     98.68% |       26494      0.99%     99.67% |        2841      0.11%     99.78% |        3411      0.13%     99.90% |        1684      0.06%     99.97% |         871      0.03%    100.00% |          17      0.00%    100.00% |          21      0.00%    100.00% |          19      0.00%    100.00% |           3      0.00%    100.00%
-system.ruby.miss_latency_hist::total          2681623                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits     17463573                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses      1589391                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses     19052964                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits    149306597                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses       484179                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses    149790776                       # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples        2711937                      
+system.ruby.miss_latency_hist::mean         25.880928                      
+system.ruby.miss_latency_hist::gmean        20.371838                      
+system.ruby.miss_latency_hist::stdev        35.746268                      
+system.ruby.miss_latency_hist            |     2676368     98.69%     98.69% |       26717      0.99%     99.67% |        2924      0.11%     99.78% |        3327      0.12%     99.90% |        1642      0.06%     99.96% |         886      0.03%    100.00% |           9      0.00%    100.00% |          33      0.00%    100.00% |          23      0.00%    100.00% |           8      0.00%    100.00%
+system.ruby.miss_latency_hist::total          2711937                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits     16386658                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses      1208703                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses     17595361                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits    114457594                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses       551051                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses    115008645                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -612,13 +618,13 @@ system.ruby.l1_cntrl0.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.fully_busy_cycles            10                       # cycles for which number of transistions == max transitions
-system.ruby.l1_cntrl1.L1Dcache.demand_hits      7462230                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses       305828                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses      7768058                       # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits     23422240                       # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses       302225                       # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses     23724465                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.fully_busy_cycles            14                       # cycles for which number of transistions == max transitions
+system.ruby.l1_cntrl1.L1Dcache.demand_hits      7947911                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses       682965                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses      8630876                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits     56450913                       # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses       269218                       # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses     56720131                       # Number of cache demand accesses
 system.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -628,605 +634,606 @@ system.ruby.l1_cntrl1.prefetcher.hits               0                       # nu
 system.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
 system.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
 system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.fully_busy_cycles            12                       # cycles for which number of transistions == max transitions
-system.ruby.l2_cntrl0.L2cache.demand_hits      2423981                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses       257642                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses      2681623                       # Number of cache demand accesses
+system.ruby.l1_cntrl1.fully_busy_cycles            14                       # cycles for which number of transistions == max transitions
+system.ruby.l2_cntrl0.L2cache.demand_hits      2479106                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses       232831                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses      2711937                       # Number of cache demand accesses
 system.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     0.069248                      
-system.ruby.network.routers0.msg_count.Control::0      2073570                      
-system.ruby.network.routers0.msg_count.Request_Control::2        69104                      
-system.ruby.network.routers0.msg_count.Response_Data::1      2116140                      
-system.ruby.network.routers0.msg_count.Response_Control::1      1556339                      
-system.ruby.network.routers0.msg_count.Response_Control::2      1546945                      
-system.ruby.network.routers0.msg_count.Writeback_Data::0       396332                      
-system.ruby.network.routers0.msg_count.Writeback_Data::1          202                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0      1087870                      
-system.ruby.network.routers0.msg_bytes.Control::0     16588560                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2       552832                      
-system.ruby.network.routers0.msg_bytes.Response_Data::1    152362080                      
-system.ruby.network.routers0.msg_bytes.Response_Control::1     12450712                      
-system.ruby.network.routers0.msg_bytes.Response_Control::2     12375560                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0     28535904                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1        14544                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0      8702960                      
-system.ruby.network.routers1.percent_links_utilized     0.020197                      
-system.ruby.network.routers1.msg_count.Control::0       608053                      
-system.ruby.network.routers1.msg_count.Request_Control::2        63486                      
-system.ruby.network.routers1.msg_count.Response_Data::1       646525                      
-system.ruby.network.routers1.msg_count.Response_Control::1       287577                      
-system.ruby.network.routers1.msg_count.Response_Control::2       279257                      
-system.ruby.network.routers1.msg_count.Writeback_Data::0       145650                      
-system.ruby.network.routers1.msg_count.Writeback_Data::1          434                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0        71246                      
-system.ruby.network.routers1.msg_bytes.Control::0      4864424                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2       507888                      
-system.ruby.network.routers1.msg_bytes.Response_Data::1     46549800                      
-system.ruby.network.routers1.msg_bytes.Response_Control::1      2300616                      
-system.ruby.network.routers1.msg_bytes.Response_Control::2      2234056                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0     10486800                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1        31248                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0       569968                      
-system.ruby.network.routers2.percent_links_utilized     0.092758                      
-system.ruby.network.routers2.msg_count.Control::0      2862482                      
-system.ruby.network.routers2.msg_count.Request_Control::2       130329                      
-system.ruby.network.routers2.msg_count.Response_Data::1      2891866                      
-system.ruby.network.routers2.msg_count.Response_Control::1      1887153                      
-system.ruby.network.routers2.msg_count.Response_Control::2      1826202                      
-system.ruby.network.routers2.msg_count.Writeback_Data::0       541982                      
-system.ruby.network.routers2.msg_count.Writeback_Data::1          636                      
-system.ruby.network.routers2.msg_count.Writeback_Control::0      1159116                      
-system.ruby.network.routers2.msg_bytes.Control::0     22899856                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2      1042632                      
-system.ruby.network.routers2.msg_bytes.Response_Data::1    208214352                      
-system.ruby.network.routers2.msg_bytes.Response_Control::1     15097224                      
-system.ruby.network.routers2.msg_bytes.Response_Control::2     14609616                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::0     39022704                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::1        45792                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::0      9272928                      
-system.ruby.network.routers3.percent_links_utilized     0.007084                      
-system.ruby.network.routers3.msg_count.Control::0       180859                      
-system.ruby.network.routers3.msg_count.Response_Data::1       283581                      
-system.ruby.network.routers3.msg_count.Response_Control::1       133793                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0        47550                      
+system.ruby.network.routers0.percent_links_utilized     0.059056                      
+system.ruby.network.routers0.msg_count.Control::0      1759754                      
+system.ruby.network.routers0.msg_count.Request_Control::2        45501                      
+system.ruby.network.routers0.msg_count.Response_Data::1      1788735                      
+system.ruby.network.routers0.msg_count.Response_Control::1      1174106                      
+system.ruby.network.routers0.msg_count.Response_Control::2      1170476                      
+system.ruby.network.routers0.msg_count.Writeback_Data::0       411011                      
+system.ruby.network.routers0.msg_count.Writeback_Data::1          193                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0       718896                      
+system.ruby.network.routers0.msg_bytes.Control::0     14078032                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2       364008                      
+system.ruby.network.routers0.msg_bytes.Response_Data::1    128788920                      
+system.ruby.network.routers0.msg_bytes.Response_Control::1      9392848                      
+system.ruby.network.routers0.msg_bytes.Response_Control::2      9363808                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0     29592792                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1        13896                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0      5751168                      
+system.ruby.network.routers1.percent_links_utilized     0.031129                      
+system.ruby.network.routers1.msg_count.Control::0       952183                      
+system.ruby.network.routers1.msg_count.Request_Control::2        41487                      
+system.ruby.network.routers1.msg_count.Response_Data::1       977973                      
+system.ruby.network.routers1.msg_count.Response_Control::1       652847                      
+system.ruby.network.routers1.msg_count.Response_Control::2       651858                      
+system.ruby.network.routers1.msg_count.Writeback_Data::0       161021                      
+system.ruby.network.routers1.msg_count.Writeback_Data::1          301                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0       450874                      
+system.ruby.network.routers1.msg_bytes.Control::0      7617464                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2       331896                      
+system.ruby.network.routers1.msg_bytes.Response_Data::1     70414056                      
+system.ruby.network.routers1.msg_bytes.Response_Control::1      5222776                      
+system.ruby.network.routers1.msg_bytes.Response_Control::2      5214864                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0     11593512                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1        21672                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0      3606992                      
+system.ruby.network.routers2.percent_links_utilized     0.094716                      
+system.ruby.network.routers2.msg_count.Control::0      2893171                      
+system.ruby.network.routers2.msg_count.Request_Control::2        85123                      
+system.ruby.network.routers2.msg_count.Response_Data::1      2948036                      
+system.ruby.network.routers2.msg_count.Response_Control::1      1908362                      
+system.ruby.network.routers2.msg_count.Response_Control::2      1822334                      
+system.ruby.network.routers2.msg_count.Writeback_Data::0       572032                      
+system.ruby.network.routers2.msg_count.Writeback_Data::1          494                      
+system.ruby.network.routers2.msg_count.Writeback_Control::0      1169770                      
+system.ruby.network.routers2.msg_bytes.Control::0     23145368                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2       680984                      
+system.ruby.network.routers2.msg_bytes.Response_Data::1    212258592                      
+system.ruby.network.routers2.msg_bytes.Response_Control::1     15266896                      
+system.ruby.network.routers2.msg_bytes.Response_Control::2     14578672                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::0     41186304                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::1        35568                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::0      9358160                      
+system.ruby.network.routers3.percent_links_utilized     0.007127                      
+system.ruby.network.routers3.msg_count.Control::0       181234                      
+system.ruby.network.routers3.msg_count.Response_Data::1       285341                      
+system.ruby.network.routers3.msg_count.Response_Control::1       133293                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0        47555                      
 system.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers3.msg_bytes.Control::0      1446872                      
-system.ruby.network.routers3.msg_bytes.Response_Data::1     20417832                      
-system.ruby.network.routers3.msg_bytes.Response_Control::1      1070344                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0       380400                      
+system.ruby.network.routers3.msg_bytes.Control::0      1449872                      
+system.ruby.network.routers3.msg_bytes.Response_Data::1     20544552                      
+system.ruby.network.routers3.msg_bytes.Response_Control::1      1066344                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0       380440                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
 system.ruby.network.routers4.percent_links_utilized     0.000243                      
-system.ruby.network.routers4.msg_count.Response_Data::1          814                      
-system.ruby.network.routers4.msg_count.Writeback_Control::0        47550                      
+system.ruby.network.routers4.msg_count.Response_Data::1          819                      
+system.ruby.network.routers4.msg_count.Writeback_Control::0        47555                      
 system.ruby.network.routers4.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers4.msg_bytes.Response_Data::1        58608                      
-system.ruby.network.routers4.msg_bytes.Writeback_Control::0       380400                      
+system.ruby.network.routers4.msg_bytes.Response_Data::1        58968                      
+system.ruby.network.routers4.msg_bytes.Writeback_Control::0       380440                      
 system.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
 system.ruby.network.routers5.percent_links_utilized            0                      
-system.ruby.network.routers6.percent_links_utilized     0.031589                      
-system.ruby.network.routers6.msg_count.Control::0      2862482                      
-system.ruby.network.routers6.msg_count.Request_Control::2       132590                      
-system.ruby.network.routers6.msg_count.Response_Data::1      2969463                      
-system.ruby.network.routers6.msg_count.Response_Control::1      1932431                      
-system.ruby.network.routers6.msg_count.Response_Control::2      1826202                      
-system.ruby.network.routers6.msg_count.Writeback_Data::0       541982                      
-system.ruby.network.routers6.msg_count.Writeback_Data::1          636                      
-system.ruby.network.routers6.msg_count.Writeback_Control::0      1206666                      
+system.ruby.network.routers6.percent_links_utilized     0.032046                      
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+system.ruby.network.routers6.msg_count.Request_Control::2        86988                      
+system.ruby.network.routers6.msg_count.Response_Data::1      3000452                      
+system.ruby.network.routers6.msg_count.Response_Control::1      1934304                      
+system.ruby.network.routers6.msg_count.Response_Control::2      1822334                      
+system.ruby.network.routers6.msg_count.Writeback_Data::0       572032                      
+system.ruby.network.routers6.msg_count.Writeback_Data::1          494                      
+system.ruby.network.routers6.msg_count.Writeback_Control::0      1217325                      
 system.ruby.network.routers6.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers6.msg_bytes.Control::0     22899856                      
-system.ruby.network.routers6.msg_bytes.Request_Control::2      1060720                      
-system.ruby.network.routers6.msg_bytes.Response_Data::1    213801336                      
-system.ruby.network.routers6.msg_bytes.Response_Control::1     15459448                      
-system.ruby.network.routers6.msg_bytes.Response_Control::2     14609616                      
-system.ruby.network.routers6.msg_bytes.Writeback_Data::0     39022704                      
-system.ruby.network.routers6.msg_bytes.Writeback_Data::1        45792                      
-system.ruby.network.routers6.msg_bytes.Writeback_Control::0      9653328                      
+system.ruby.network.routers6.msg_bytes.Control::0     23145368                      
+system.ruby.network.routers6.msg_bytes.Request_Control::2       695904                      
+system.ruby.network.routers6.msg_bytes.Response_Data::1    216032544                      
+system.ruby.network.routers6.msg_bytes.Response_Control::1     15474432                      
+system.ruby.network.routers6.msg_bytes.Response_Control::2     14578672                      
+system.ruby.network.routers6.msg_bytes.Writeback_Data::0     41186304                      
+system.ruby.network.routers6.msg_bytes.Writeback_Data::1        35568                      
+system.ruby.network.routers6.msg_bytes.Writeback_Control::0      9738600                      
 system.ruby.network.routers6.msg_bytes.Writeback_Control::1       373888                      
-system.ruby.network.msg_count.Control         8587446                      
-system.ruby.network.msg_count.Request_Control       395509                      
-system.ruby.network.msg_count.Response_Data      8908389                      
-system.ruby.network.msg_count.Response_Control     11275899                      
-system.ruby.network.msg_count.Writeback_Data      1627854                      
-system.ruby.network.msg_count.Writeback_Control      3760206                      
-system.ruby.network.msg_byte.Control         68699568                      
-system.ruby.network.msg_byte.Request_Control      3164072                      
-system.ruby.network.msg_byte.Response_Data    641404008                      
-system.ruby.network.msg_byte.Response_Control     90207192                      
-system.ruby.network.msg_byte.Writeback_Data    117205488                      
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+system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47555                      
+system.ruby.network.routers6.throttle3.msg_bytes.Control::0      1449872                      
+system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7436736                      
+system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       107680                      
+system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380440                      
 system.ruby.network.routers6.throttle4.link_utilization     0.000259                      
-system.ruby.network.routers6.throttle4.msg_count.Response_Data::1          814                      
+system.ruby.network.routers6.throttle4.msg_count.Response_Data::1          819                      
 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1        46736                      
-system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58608                      
+system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58968                      
 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       373888                      
 system.ruby.network.routers6.throttle5.link_utilization            0                      
 system.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples       6208923                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean         0.706330                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev        2.282369                       # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0           |     5663471     91.22%     91.22% |        1771      0.03%     91.24% |      541397      8.72%     99.96% |         469      0.01%     99.97% |        1705      0.03%    100.00% |          18      0.00%    100.00% |          91      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total         6208923                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples       6276073                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean         0.731694                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev        2.309515                       # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0           |     5702895     90.87%     90.87% |         563      0.01%     90.88% |      572045      9.11%     99.99% |         184      0.00%     99.99% |         309      0.00%    100.00% |          12      0.00%    100.00% |          62      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total         6276073                       # delay histogram for vnet_0
 system.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples       4785266                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean         0.087581                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev        0.822703                       # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1           |     4729884     98.84%     98.84% |        1830      0.04%     98.88% |        2212      0.05%     98.93% |        2634      0.06%     98.98% |       48164      1.01%     99.99% |         531      0.01%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           6      0.00%    100.00% |           1      0.00%    100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total         4785266                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples       4817683                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean         0.048845                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev        0.619508                       # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1           |     4787335     99.37%     99.37% |         621      0.01%     99.38% |         650      0.01%     99.40% |         843      0.02%     99.41% |       27983      0.58%     99.99% |         240      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total         4817683                       # delay histogram for vnet_1
 system.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
 system.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples        132590                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean         0.000272                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev        0.023301                       # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2           |      132572     99.99%     99.99% |           0      0.00%     99.99% |          18      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total          132590                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples         86988                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean         0.000184                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev        0.019179                       # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2           |       86980     99.99%     99.99% |           0      0.00%     99.99% |           8      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total           86988                       # delay histogram for vnet_2
 system.ruby.LD.latency_hist::bucket_size          128                      
 system.ruby.LD.latency_hist::max_bucket          1279                      
-system.ruby.LD.latency_hist::samples         15790582                      
-system.ruby.LD.latency_hist::mean            2.812687                      
-system.ruby.LD.latency_hist::gmean           1.304256                      
-system.ruby.LD.latency_hist::stdev           8.986997                      
-system.ruby.LD.latency_hist              |    15775646     99.91%     99.91% |       12869      0.08%     99.99% |         830      0.01%     99.99% |         776      0.00%    100.00% |         352      0.00%    100.00% |          97      0.00%    100.00% |           3      0.00%    100.00% |           7      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.latency_hist::total           15790582                      
+system.ruby.LD.latency_hist::samples         15432046                      
+system.ruby.LD.latency_hist::mean            2.853578                      
+system.ruby.LD.latency_hist::gmean           1.313269                      
+system.ruby.LD.latency_hist::stdev           9.014347                      
+system.ruby.LD.latency_hist              |    15417213     99.90%     99.90% |       12849      0.08%     99.99% |         809      0.01%     99.99% |         750      0.00%    100.00% |         322      0.00%    100.00% |          89      0.00%    100.00% |           3      0.00%    100.00% |           6      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00%
+system.ruby.LD.latency_hist::total           15432046                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
 system.ruby.LD.hit_latency_hist::max_bucket            9                      
-system.ruby.LD.hit_latency_hist::samples     14360870                      
+system.ruby.LD.hit_latency_hist::samples     13998284                      
 system.ruby.LD.hit_latency_hist::mean               1                      
 system.ruby.LD.hit_latency_hist::gmean              1                      
-system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |    14360870    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.hit_latency_hist::total       14360870                      
+system.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |    13998284    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.LD.hit_latency_hist::total       13998284                      
 system.ruby.LD.miss_latency_hist::bucket_size          128                      
 system.ruby.LD.miss_latency_hist::max_bucket         1279                      
-system.ruby.LD.miss_latency_hist::samples      1429712                      
-system.ruby.LD.miss_latency_hist::mean      21.020380                      
-system.ruby.LD.miss_latency_hist::gmean     18.799074                      
-system.ruby.LD.miss_latency_hist::stdev     22.967453                      
-system.ruby.LD.miss_latency_hist         |     1414776     98.96%     98.96% |       12869      0.90%     99.86% |         830      0.06%     99.91% |         776      0.05%     99.97% |         352      0.02%     99.99% |          97      0.01%    100.00% |           3      0.00%    100.00% |           7      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.LD.miss_latency_hist::total       1429712                      
+system.ruby.LD.miss_latency_hist::samples      1433762                      
+system.ruby.LD.miss_latency_hist::mean      20.950658                      
+system.ruby.LD.miss_latency_hist::gmean     18.787895                      
+system.ruby.LD.miss_latency_hist::stdev     22.661921                      
+system.ruby.LD.miss_latency_hist         |     1418929     98.97%     98.97% |       12849      0.90%     99.86% |         809      0.06%     99.92% |         750      0.05%     99.97% |         322      0.02%     99.99% |          89      0.01%    100.00% |           3      0.00%    100.00% |           6      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00%
+system.ruby.LD.miss_latency_hist::total       1433762                      
 system.ruby.ST.latency_hist::bucket_size          128                      
 system.ruby.ST.latency_hist::max_bucket          1279                      
-system.ruby.ST.latency_hist::samples          9817325                      
-system.ruby.ST.latency_hist::mean            3.175435                      
-system.ruby.ST.latency_hist::gmean           1.140318                      
-system.ruby.ST.latency_hist::stdev          17.634571                      
-system.ruby.ST.latency_hist              |     9803433     99.86%     99.86% |        8125      0.08%     99.94% |        1485      0.02%     99.96% |        2325      0.02%     99.98% |        1191      0.01%     99.99% |         723      0.01%    100.00% |          13      0.00%    100.00% |          12      0.00%    100.00% |          15      0.00%    100.00% |           3      0.00%    100.00%
-system.ruby.ST.latency_hist::total            9817325                      
+system.ruby.ST.latency_hist::samples          9612989                      
+system.ruby.ST.latency_hist::mean            3.237181                      
+system.ruby.ST.latency_hist::gmean           1.143928                      
+system.ruby.ST.latency_hist::stdev          17.959095                      
+system.ruby.ST.latency_hist              |     9598428     99.85%     99.85% |        8674      0.09%     99.94% |        1607      0.02%     99.96% |        2294      0.02%     99.98% |        1185      0.01%     99.99% |         751      0.01%    100.00% |           6      0.00%    100.00% |          22      0.00%    100.00% |          16      0.00%    100.00% |           6      0.00%    100.00%
+system.ruby.ST.latency_hist::total            9612989                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
 system.ruby.ST.hit_latency_hist::max_bucket            9                      
-system.ruby.ST.hit_latency_hist::samples      9465664                      
+system.ruby.ST.hit_latency_hist::samples      9259406                      
 system.ruby.ST.hit_latency_hist::mean               1                      
 system.ruby.ST.hit_latency_hist::gmean              1                      
-system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |     9465664    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.ST.hit_latency_hist::total        9465664                      
+system.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |     9259406    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.ST.hit_latency_hist::total        9259406                      
 system.ruby.ST.miss_latency_hist::bucket_size          128                      
 system.ruby.ST.miss_latency_hist::max_bucket         1279                      
-system.ruby.ST.miss_latency_hist::samples       351661                      
-system.ruby.ST.miss_latency_hist::mean      61.731653                      
-system.ruby.ST.miss_latency_hist::gmean     39.083293                      
-system.ruby.ST.miss_latency_hist::stdev     71.591745                      
-system.ruby.ST.miss_latency_hist         |      337769     96.05%     96.05% |        8125      2.31%     98.36% |        1485      0.42%     98.78% |        2325      0.66%     99.44% |        1191      0.34%     99.78% |         723      0.21%     99.99% |          13      0.00%     99.99% |          12      0.00%     99.99% |          15      0.00%    100.00% |           3      0.00%    100.00%
-system.ruby.ST.miss_latency_hist::total        351661                      
+system.ruby.ST.miss_latency_hist::samples       353583                      
+system.ruby.ST.miss_latency_hist::mean      61.823054                      
+system.ruby.ST.miss_latency_hist::gmean     38.699181                      
+system.ruby.ST.miss_latency_hist::stdev     72.148162                      
+system.ruby.ST.miss_latency_hist         |      339022     95.88%     95.88% |        8674      2.45%     98.34% |        1607      0.45%     98.79% |        2294      0.65%     99.44% |        1185      0.34%     99.77% |         751      0.21%     99.99% |           6      0.00%     99.99% |          22      0.01%     99.99% |          16      0.00%    100.00% |           6      0.00%    100.00%
+system.ruby.ST.miss_latency_hist::total        353583                      
 system.ruby.IFETCH.latency_hist::bucket_size          128                      
 system.ruby.IFETCH.latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.latency_hist::samples    173515241                      
-system.ruby.IFETCH.latency_hist::mean        1.084205                      
-system.ruby.IFETCH.latency_hist::gmean       1.013120                      
-system.ruby.IFETCH.latency_hist::stdev       1.878946                      
-system.ruby.IFETCH.latency_hist          |   173509156    100.00%    100.00% |        5109      0.00%    100.00% |         498      0.00%    100.00% |         299      0.00%    100.00% |         130      0.00%    100.00% |          45      0.00%    100.00% |           1      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.latency_hist::total      173515241                      
+system.ruby.IFETCH.latency_hist::samples    171728776                      
+system.ruby.IFETCH.latency_hist::mean        1.087723                      
+system.ruby.IFETCH.latency_hist::gmean       1.013813                      
+system.ruby.IFETCH.latency_hist::stdev       1.876064                      
+system.ruby.IFETCH.latency_hist          |   171723049    100.00%    100.00% |        4816      0.00%    100.00% |         477      0.00%    100.00% |         266      0.00%    100.00% |         120      0.00%    100.00% |          39      0.00%    100.00% |           0      0.00%    100.00% |           5      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::total      171728776                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
-system.ruby.IFETCH.hit_latency_hist::samples    172728837                      
+system.ruby.IFETCH.hit_latency_hist::samples    170908507                      
 system.ruby.IFETCH.hit_latency_hist::mean            1                      
 system.ruby.IFETCH.hit_latency_hist::gmean            1                      
-system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |   172728837    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.hit_latency_hist::total    172728837                      
+system.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |   170908507    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.hit_latency_hist::total    170908507                      
 system.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
-system.ruby.IFETCH.miss_latency_hist::samples       786404                      
-system.ruby.IFETCH.miss_latency_hist::mean    19.579326                      
-system.ruby.IFETCH.miss_latency_hist::gmean    17.745067                      
-system.ruby.IFETCH.miss_latency_hist::stdev    20.864873                      
-system.ruby.IFETCH.miss_latency_hist     |      780319     99.23%     99.23% |        5109      0.65%     99.88% |         498      0.06%     99.94% |         299      0.04%     99.98% |         130      0.02%     99.99% |          45      0.01%    100.00% |           1      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.IFETCH.miss_latency_hist::total       786404                      
+system.ruby.IFETCH.miss_latency_hist::samples       820269                      
+system.ruby.IFETCH.miss_latency_hist::mean    19.365461                      
+system.ruby.IFETCH.miss_latency_hist::gmean    17.675024                      
+system.ruby.IFETCH.miss_latency_hist::stdev    20.029392                      
+system.ruby.IFETCH.miss_latency_hist     |      814542     99.30%     99.30% |        4816      0.59%     99.89% |         477      0.06%     99.95% |         266      0.03%     99.98% |         120      0.01%     99.99% |          39      0.00%    100.00% |           0      0.00%    100.00% |           5      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::total       820269                      
 system.ruby.RMW_Read.latency_hist::bucket_size          128                      
 system.ruby.RMW_Read.latency_hist::max_bucket         1279                      
-system.ruby.RMW_Read.latency_hist::samples       523939                      
-system.ruby.RMW_Read.latency_hist::mean      4.129191                      
-system.ruby.RMW_Read.latency_hist::gmean     1.527796                      
-system.ruby.RMW_Read.latency_hist::stdev    10.162632                      
-system.ruby.RMW_Read.latency_hist        |      523754     99.96%     99.96% |         145      0.03%     99.99% |          18      0.00%    100.00% |           9      0.00%    100.00% |           8      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.latency_hist::total       523939                      
+system.ruby.RMW_Read.latency_hist::samples       500824                      
+system.ruby.RMW_Read.latency_hist::mean      4.015684                      
+system.ruby.RMW_Read.latency_hist::gmean     1.504004                      
+system.ruby.RMW_Read.latency_hist::stdev    10.245462                      
+system.ruby.RMW_Read.latency_hist        |      500634     99.96%     99.96% |         144      0.03%     99.99% |          19      0.00%     99.99% |          11      0.00%    100.00% |           9      0.00%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.latency_hist::total       500824                      
 system.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
 system.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
-system.ruby.RMW_Read.hit_latency_hist::samples       452465                      
+system.ruby.RMW_Read.hit_latency_hist::samples       434823                      
 system.ruby.RMW_Read.hit_latency_hist::mean            1                      
 system.ruby.RMW_Read.hit_latency_hist::gmean            1                      
-system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |      452465    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.hit_latency_hist::total       452465                      
+system.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |      434823    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.hit_latency_hist::total       434823                      
 system.ruby.RMW_Read.miss_latency_hist::bucket_size          128                      
 system.ruby.RMW_Read.miss_latency_hist::max_bucket         1279                      
-system.ruby.RMW_Read.miss_latency_hist::samples        71474                      
-system.ruby.RMW_Read.miss_latency_hist::mean    23.938481                      
-system.ruby.RMW_Read.miss_latency_hist::gmean    22.350533                      
-system.ruby.RMW_Read.miss_latency_hist::stdev    17.398088                      
-system.ruby.RMW_Read.miss_latency_hist   |       71289     99.74%     99.74% |         145      0.20%     99.94% |          18      0.03%     99.97% |           9      0.01%     99.98% |           8      0.01%     99.99% |           4      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.RMW_Read.miss_latency_hist::total        71474                      
-system.ruby.Locked_RMW_Read.latency_hist::bucket_size          128                      
-system.ruby.Locked_RMW_Read.latency_hist::max_bucket         1279                      
-system.ruby.Locked_RMW_Read.latency_hist::samples       344588                      
-system.ruby.Locked_RMW_Read.latency_hist::mean     3.637196                      
-system.ruby.Locked_RMW_Read.latency_hist::gmean     1.457387                      
-system.ruby.Locked_RMW_Read.latency_hist::stdev     8.622051                      
-system.ruby.Locked_RMW_Read.latency_hist |      344325     99.92%     99.92% |         246      0.07%    100.00% |          10      0.00%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.latency_hist::total       344588                      
+system.ruby.RMW_Read.miss_latency_hist::samples        66001                      
+system.ruby.RMW_Read.miss_latency_hist::mean    23.883396                      
+system.ruby.RMW_Read.miss_latency_hist::gmean    22.130353                      
+system.ruby.RMW_Read.miss_latency_hist::stdev    18.490127                      
+system.ruby.RMW_Read.miss_latency_hist   |       65811     99.71%     99.71% |         144      0.22%     99.93% |          19      0.03%     99.96% |          11      0.02%     99.98% |           9      0.01%     99.99% |           7      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.RMW_Read.miss_latency_hist::total        66001                      
+system.ruby.Locked_RMW_Read.latency_hist::bucket_size           64                      
+system.ruby.Locked_RMW_Read.latency_hist::max_bucket          639                      
+system.ruby.Locked_RMW_Read.latency_hist::samples       340189                      
+system.ruby.Locked_RMW_Read.latency_hist::mean     3.322441                      
+system.ruby.Locked_RMW_Read.latency_hist::gmean     1.405056                      
+system.ruby.Locked_RMW_Read.latency_hist::stdev     8.375867                      
+system.ruby.Locked_RMW_Read.latency_hist |      339841     99.90%     99.90% |          90      0.03%     99.92% |         233      0.07%     99.99% |           1      0.00%     99.99% |           4      0.00%     99.99% |           8      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           1      0.00%    100.00% |           5      0.00%    100.00%
+system.ruby.Locked_RMW_Read.latency_hist::total       340189                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Read.hit_latency_hist::samples       302216                      
+system.ruby.Locked_RMW_Read.hit_latency_hist::samples       301867                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::mean            1                      
 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean            1                      
-system.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |      302216    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.hit_latency_hist::total       302216                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size          128                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket         1279                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::samples        42372                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::mean    22.446852                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::gmean    21.392577                      
-system.ruby.Locked_RMW_Read.miss_latency_hist::stdev    14.183059                      
-system.ruby.Locked_RMW_Read.miss_latency_hist |       42109     99.38%     99.38% |         246      0.58%     99.96% |          10      0.02%     99.98% |           2      0.00%     99.99% |           3      0.01%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Read.miss_latency_hist::total        42372                      
+system.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |      301867    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Read.hit_latency_hist::total       301867                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size           64                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket          639                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::samples        38322                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::mean    21.616591                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::gmean    20.468877                      
+system.ruby.Locked_RMW_Read.miss_latency_hist::stdev    15.672180                      
+system.ruby.Locked_RMW_Read.miss_latency_hist |       37974     99.09%     99.09% |          90      0.23%     99.33% |         233      0.61%     99.93% |           1      0.00%     99.94% |           4      0.01%     99.95% |           8      0.02%     99.97% |           5      0.01%     99.98% |           1      0.00%     99.98% |           1      0.00%     99.99% |           5      0.01%    100.00%
+system.ruby.Locked_RMW_Read.miss_latency_hist::total        38322                      
 system.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Write.latency_hist::samples       344588                      
+system.ruby.Locked_RMW_Write.latency_hist::samples       340189                      
 system.ruby.Locked_RMW_Write.latency_hist::mean            1                      
 system.ruby.Locked_RMW_Write.latency_hist::gmean            1                      
-system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |      344588    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Write.latency_hist::total       344588                      
+system.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |      340189    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Write.latency_hist::total       340189                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
-system.ruby.Locked_RMW_Write.hit_latency_hist::samples       344588                      
+system.ruby.Locked_RMW_Write.hit_latency_hist::samples       340189                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::mean            1                      
 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean            1                      
-system.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |      344588    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.Locked_RMW_Write.hit_latency_hist::total       344588                      
-system.ruby.Directory_Controller.Fetch         180859      0.00%      0.00%
-system.ruby.Directory_Controller.Data          101908      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data       181314      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack       146202      0.00%      0.00%
-system.ruby.Directory_Controller.DMA_READ          814      0.00%      0.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |      340189    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Locked_RMW_Write.hit_latency_hist::total       340189                      
+system.ruby.Directory_Controller.Fetch         181234      0.00%      0.00%
+system.ruby.Directory_Controller.Data          103288      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data       181708      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack       147284      0.00%      0.00%
+system.ruby.Directory_Controller.DMA_READ          819      0.00%      0.00%
 system.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement        14542      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch       180859      0.00%      0.00%
-system.ruby.Directory_Controller.I.DMA_READ          455      0.00%      0.00%
-system.ruby.Directory_Controller.I.DMA_WRITE        44294      0.00%      0.00%
-system.ruby.Directory_Controller.ID.Memory_Data          455      0.00%      0.00%
-system.ruby.Directory_Controller.ID_W.Memory_Ack        44294      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data         99107      0.00%      0.00%
-system.ruby.Directory_Controller.M.DMA_READ          359      0.00%      0.00%
-system.ruby.Directory_Controller.M.DMA_WRITE         2442      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement        14542      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data       180859      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack        99107      0.00%      0.00%
-system.ruby.Directory_Controller.M_DRD.Data          359      0.00%      0.00%
-system.ruby.Directory_Controller.M_DRDI.Memory_Ack          359      0.00%      0.00%
-system.ruby.Directory_Controller.M_DWR.Data         2442      0.00%      0.00%
-system.ruby.Directory_Controller.M_DWRI.Memory_Ack         2442      0.00%      0.00%
-system.ruby.DMA_Controller.ReadRequest   |         814    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.DMA_Controller.ReadRequest::total          814                      
+system.ruby.Directory_Controller.CleanReplacement        13460      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch       181234      0.00%      0.00%
+system.ruby.Directory_Controller.I.DMA_READ          474      0.00%      0.00%
+system.ruby.Directory_Controller.I.DMA_WRITE        43996      0.00%      0.00%
+system.ruby.Directory_Controller.ID.Memory_Data          474      0.00%      0.00%
+system.ruby.Directory_Controller.ID_W.Memory_Ack        43996      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data        100203      0.00%      0.00%
+system.ruby.Directory_Controller.M.DMA_READ          345      0.00%      0.00%
+system.ruby.Directory_Controller.M.DMA_WRITE         2740      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement        13460      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data       181234      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack       100203      0.00%      0.00%
+system.ruby.Directory_Controller.M_DRD.Data          345      0.00%      0.00%
+system.ruby.Directory_Controller.M_DRDI.Memory_Ack          345      0.00%      0.00%
+system.ruby.Directory_Controller.M_DWR.Data         2740      0.00%      0.00%
+system.ruby.Directory_Controller.M_DWRI.Memory_Ack         2740      0.00%      0.00%
+system.ruby.DMA_Controller.ReadRequest   |         819    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.DMA_Controller.ReadRequest::total          819                      
 system.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.WriteRequest::total        46736                      
-system.ruby.DMA_Controller.Data          |         814    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.DMA_Controller.Data::total            814                      
+system.ruby.DMA_Controller.Data          |         819    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.DMA_Controller.Data::total            819                      
 system.ruby.DMA_Controller.Ack           |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.Ack::total           46736                      
-system.ruby.DMA_Controller.READY.ReadRequest |         814    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.DMA_Controller.READY.ReadRequest::total          814                      
+system.ruby.DMA_Controller.READY.ReadRequest |         819    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.DMA_Controller.READY.ReadRequest::total          819                      
 system.ruby.DMA_Controller.READY.WriteRequest |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.READY.WriteRequest::total        46736                      
-system.ruby.DMA_Controller.BUSY_RD.Data  |         814    100.00%    100.00% |           0      0.00%    100.00%
-system.ruby.DMA_Controller.BUSY_RD.Data::total          814                      
+system.ruby.DMA_Controller.BUSY_RD.Data  |         819    100.00%    100.00% |           0      0.00%    100.00%
+system.ruby.DMA_Controller.BUSY_RD.Data::total          819                      
 system.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
-system.ruby.L1Cache_Controller.Load      |    11499254     72.82%     72.82% |     4291328     27.18%    100.00%
-system.ruby.L1Cache_Controller.Load::total     15790582                      
-system.ruby.L1Cache_Controller.Ifetch    |   149790779     86.33%     86.33% |    23724467     13.67%    100.00%
-system.ruby.L1Cache_Controller.Ifetch::total    173515246                      
-system.ruby.L1Cache_Controller.Store     |     7553710     68.48%     68.48% |     3476730     31.52%    100.00%
-system.ruby.L1Cache_Controller.Store::total     11030440                      
-system.ruby.L1Cache_Controller.Inv       |       29958     53.68%     53.68% |       25849     46.32%    100.00%
-system.ruby.L1Cache_Controller.Inv::total        55807                      
-system.ruby.L1Cache_Controller.L1_Replacement |     2028024     78.37%     78.37% |      559829     21.63%    100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total      2587853                      
-system.ruby.L1Cache_Controller.Fwd_GETX  |       15400     51.07%     51.07% |       14755     48.93%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total        30155                      
-system.ruby.L1Cache_Controller.Fwd_GETS  |       23742     50.92%     50.92% |       22882     49.08%    100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total        46624                      
+system.ruby.L1Cache_Controller.Load      |    10196157     66.07%     66.07% |     5235889     33.93%    100.00%
+system.ruby.L1Cache_Controller.Load::total     15432046                      
+system.ruby.L1Cache_Controller.Ifetch    |   115008649     66.97%     66.97% |    56720132     33.03%    100.00%
+system.ruby.L1Cache_Controller.Ifetch::total    171728781                      
+system.ruby.L1Cache_Controller.Store     |     7399204     68.55%     68.55% |     3394987     31.45%    100.00%
+system.ruby.L1Cache_Controller.Store::total     10794191                      
+system.ruby.L1Cache_Controller.Inv       |       18502     52.28%     52.28% |       16889     47.72%    100.00%
+system.ruby.L1Cache_Controller.Inv::total        35391                      
+system.ruby.L1Cache_Controller.L1_Replacement |     1730094     65.23%     65.23% |      922339     34.77%    100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total      2652433                      
+system.ruby.L1Cache_Controller.Fwd_GETX  |       12336     51.16%     51.16% |       11775     48.84%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total        24111                      
+system.ruby.L1Cache_Controller.Fwd_GETS  |       14659     53.34%     53.34% |       12823     46.66%    100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total        27482                      
 system.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
-system.ruby.L1Cache_Controller.Data      |        1737     59.71%     59.71% |        1172     40.29%    100.00%
-system.ruby.L1Cache_Controller.Data::total         2909                      
-system.ruby.L1Cache_Controller.Data_Exclusive |     1207088     91.86%     91.86% |      106979      8.14%    100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total      1314067                      
-system.ruby.L1Cache_Controller.DataS_fromL1 |       22882     49.07%     49.07% |       23746     50.93%    100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total        46628                      
-system.ruby.L1Cache_Controller.Data_all_Acks |      821541     64.40%     64.40% |      454109     35.60%    100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total      1275650                      
-system.ruby.L1Cache_Controller.Ack       |       20322     47.96%     47.96% |       22047     52.04%    100.00%
-system.ruby.L1Cache_Controller.Ack::total        42369                      
-system.ruby.L1Cache_Controller.Ack_all   |       22059     48.72%     48.72% |       23219     51.28%    100.00%
-system.ruby.L1Cache_Controller.Ack_all::total        45278                      
-system.ruby.L1Cache_Controller.WB_Ack    |     1484202     87.25%     87.25% |      216896     12.75%    100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total      1701098                      
-system.ruby.L1Cache_Controller.NP.Load   |     1255942     89.89%     89.89% |      141182     10.11%    100.00%
-system.ruby.L1Cache_Controller.NP.Load::total      1397124                      
-system.ruby.L1Cache_Controller.NP.Ifetch |      483731     61.58%     61.58% |      301770     38.42%    100.00%
-system.ruby.L1Cache_Controller.NP.Ifetch::total       785501                      
-system.ruby.L1Cache_Controller.NP.Store  |      289373     71.05%     71.05% |      117901     28.95%    100.00%
-system.ruby.L1Cache_Controller.NP.Store::total       407274                      
-system.ruby.L1Cache_Controller.NP.Inv    |        6783     68.15%     68.15% |        3170     31.85%    100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total         9953                      
-system.ruby.L1Cache_Controller.I.Load    |       16474     50.55%     50.55% |       16114     49.45%    100.00%
-system.ruby.L1Cache_Controller.I.Load::total        32588                      
-system.ruby.L1Cache_Controller.I.Ifetch  |         448     49.61%     49.61% |         455     50.39%    100.00%
-system.ruby.L1Cache_Controller.I.Ifetch::total          903                      
-system.ruby.L1Cache_Controller.I.Store   |        7275     45.88%     45.88% |        8582     54.12%    100.00%
-system.ruby.L1Cache_Controller.I.Store::total        15857                      
-system.ruby.L1Cache_Controller.I.L1_Replacement |       14373     54.06%     54.06% |       12212     45.94%    100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total        26585                      
-system.ruby.L1Cache_Controller.S.Load    |      942765     61.54%     61.54% |      589150     38.46%    100.00%
-system.ruby.L1Cache_Controller.S.Load::total      1531915                      
-system.ruby.L1Cache_Controller.S.Ifetch  |   149306597     86.44%     86.44% |    23422240     13.56%    100.00%
-system.ruby.L1Cache_Controller.S.Ifetch::total    172728837                      
-system.ruby.L1Cache_Controller.S.Store   |       20327     47.97%     47.97% |       22049     52.03%    100.00%
-system.ruby.L1Cache_Controller.S.Store::total        42376                      
-system.ruby.L1Cache_Controller.S.Inv     |       22933     51.00%     51.00% |       22033     49.00%    100.00%
-system.ruby.L1Cache_Controller.S.Inv::total        44966                      
-system.ruby.L1Cache_Controller.S.L1_Replacement |      529449     61.55%     61.55% |      330721     38.45%    100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total       860170                      
-system.ruby.L1Cache_Controller.E.Load    |     2977799     80.56%     80.56% |      718721     19.44%    100.00%
-system.ruby.L1Cache_Controller.E.Load::total      3696520                      
-system.ruby.L1Cache_Controller.E.Store   |      117327     77.49%     77.49% |       34087     22.51%    100.00%
-system.ruby.L1Cache_Controller.E.Store::total       151414                      
-system.ruby.L1Cache_Controller.E.Inv     |          35     14.29%     14.29% |         210     85.71%    100.00%
-system.ruby.L1Cache_Controller.E.Inv::total          245                      
-system.ruby.L1Cache_Controller.E.L1_Replacement |     1087870     93.85%     93.85% |       71246      6.15%    100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total      1159116                      
-system.ruby.L1Cache_Controller.E.Fwd_GETX |         218     60.56%     60.56% |         142     39.44%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total          360                      
-system.ruby.L1Cache_Controller.E.Fwd_GETS |        1426     54.02%     54.02% |        1214     45.98%    100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total         2640                      
-system.ruby.L1Cache_Controller.M.Load    |     6306274     69.05%     69.05% |     2826161     30.95%    100.00%
-system.ruby.L1Cache_Controller.M.Load::total      9132435                      
-system.ruby.L1Cache_Controller.M.Store   |     7119408     68.37%     68.37% |     3294111     31.63%    100.00%
-system.ruby.L1Cache_Controller.M.Store::total     10413519                      
-system.ruby.L1Cache_Controller.M.Inv     |         202     31.76%     31.76% |         434     68.24%    100.00%
-system.ruby.L1Cache_Controller.M.Inv::total          636                      
-system.ruby.L1Cache_Controller.M.L1_Replacement |      396332     73.13%     73.13% |      145650     26.87%    100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total       541982                      
-system.ruby.L1Cache_Controller.M.Fwd_GETX |       15182     50.95%     50.95% |       14613     49.05%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total        29795                      
-system.ruby.L1Cache_Controller.M.Fwd_GETS |       22316     50.74%     50.74% |       21668     49.26%    100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total        43984                      
+system.ruby.L1Cache_Controller.Data      |         528     32.39%     32.39% |        1102     67.61%    100.00%
+system.ruby.L1Cache_Controller.Data::total         1630                      
+system.ruby.L1Cache_Controller.Data_Exclusive |      840504     62.87%     62.87% |      496438     37.13%    100.00%
+system.ruby.L1Cache_Controller.Data_Exclusive::total      1336942                      
+system.ruby.L1Cache_Controller.DataS_fromL1 |       12823     46.65%     46.65% |       14663     53.35%    100.00%
+system.ruby.L1Cache_Controller.DataS_fromL1::total        27486                      
+system.ruby.L1Cache_Controller.Data_all_Acks |      893218     67.59%     67.59% |      428349     32.41%    100.00%
+system.ruby.L1Cache_Controller.Data_all_Acks::total      1321567                      
+system.ruby.L1Cache_Controller.Ack       |       12681     52.16%     52.16% |       11631     47.84%    100.00%
+system.ruby.L1Cache_Controller.Ack::total        24312                      
+system.ruby.L1Cache_Controller.Ack_all   |       13209     50.92%     50.92% |       12733     49.08%    100.00%
+system.ruby.L1Cache_Controller.Ack_all::total        25942                      
+system.ruby.L1Cache_Controller.WB_Ack    |     1129907     64.87%     64.87% |      611895     35.13%    100.00%
+system.ruby.L1Cache_Controller.WB_Ack::total      1741802                      
+system.ruby.L1Cache_Controller.NP.Load   |      881473     62.40%     62.40% |      531116     37.60%    100.00%
+system.ruby.L1Cache_Controller.NP.Load::total      1412589                      
+system.ruby.L1Cache_Controller.NP.Ifetch |      550888     67.18%     67.18% |      269077     32.82%    100.00%
+system.ruby.L1Cache_Controller.NP.Ifetch::total       819965                      
+system.ruby.L1Cache_Controller.NP.Store  |      298756     70.81%     70.81% |      123170     29.19%    100.00%
+system.ruby.L1Cache_Controller.NP.Store::total       421926                      
+system.ruby.L1Cache_Controller.NP.Inv    |        5771     62.78%     62.78% |        3422     37.22%    100.00%
+system.ruby.L1Cache_Controller.NP.Inv::total         9193                      
+system.ruby.L1Cache_Controller.I.Load    |       10081     47.61%     47.61% |       11092     52.39%    100.00%
+system.ruby.L1Cache_Controller.I.Load::total        21173                      
+system.ruby.L1Cache_Controller.I.Ifetch  |         163     53.62%     53.62% |         141     46.38%    100.00%
+system.ruby.L1Cache_Controller.I.Ifetch::total          304                      
+system.ruby.L1Cache_Controller.I.Store   |        5712     48.96%     48.96% |        5955     51.04%    100.00%
+system.ruby.L1Cache_Controller.I.Store::total        11667                      
+system.ruby.L1Cache_Controller.I.L1_Replacement |        9111     53.32%     53.32% |        7975     46.68%    100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total        17086                      
+system.ruby.L1Cache_Controller.S.Load    |      850617     63.10%     63.10% |      497429     36.90%    100.00%
+system.ruby.L1Cache_Controller.S.Load::total      1348046                      
+system.ruby.L1Cache_Controller.S.Ifetch  |   114457594     66.97%     66.97% |    56450913     33.03%    100.00%
+system.ruby.L1Cache_Controller.S.Ifetch::total    170908507                      
+system.ruby.L1Cache_Controller.S.Store   |       12681     52.16%     52.16% |       11632     47.84%    100.00%
+system.ruby.L1Cache_Controller.S.Store::total        24313                      
+system.ruby.L1Cache_Controller.S.Inv     |       12466     48.73%     48.73% |       13117     51.27%    100.00%
+system.ruby.L1Cache_Controller.S.Inv::total        25583                      
+system.ruby.L1Cache_Controller.S.L1_Replacement |      591076     66.15%     66.15% |      302469     33.85%    100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total       893545                      
+system.ruby.L1Cache_Controller.E.Load    |     2398204     64.14%     64.14% |     1340570     35.86%    100.00%
+system.ruby.L1Cache_Controller.E.Load::total      3738774                      
+system.ruby.L1Cache_Controller.E.Store   |      120081     73.14%     73.14% |       44106     26.86%    100.00%
+system.ruby.L1Cache_Controller.E.Store::total       164187                      
+system.ruby.L1Cache_Controller.E.Inv     |          72     60.00%     60.00% |          48     40.00%    100.00%
+system.ruby.L1Cache_Controller.E.Inv::total          120                      
+system.ruby.L1Cache_Controller.E.L1_Replacement |      718896     61.46%     61.46% |      450874     38.54%    100.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement::total      1169770                      
+system.ruby.L1Cache_Controller.E.Fwd_GETX |         233     64.01%     64.01% |         131     35.99%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETX::total          364                      
+system.ruby.L1Cache_Controller.E.Fwd_GETS |        1000     46.06%     46.06% |        1171     53.94%    100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETS::total         2171                      
+system.ruby.L1Cache_Controller.M.Load    |     6055782     67.95%     67.95% |     2855682     32.05%    100.00%
+system.ruby.L1Cache_Controller.M.Load::total      8911464                      
+system.ruby.L1Cache_Controller.M.Store   |     6961974     68.44%     68.44% |     3210124     31.56%    100.00%
+system.ruby.L1Cache_Controller.M.Store::total     10172098                      
+system.ruby.L1Cache_Controller.M.Inv     |         193     39.07%     39.07% |         301     60.93%    100.00%
+system.ruby.L1Cache_Controller.M.Inv::total          494                      
+system.ruby.L1Cache_Controller.M.L1_Replacement |      411011     71.85%     71.85% |      161021     28.15%    100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total       572032                      
+system.ruby.L1Cache_Controller.M.Fwd_GETX |       12103     50.97%     50.97% |       11644     49.03%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total        23747                      
+system.ruby.L1Cache_Controller.M.Fwd_GETS |       13659     53.96%     53.96% |       11652     46.04%    100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total        25311                      
 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
-system.ruby.L1Cache_Controller.IS.Data_Exclusive |     1207088     91.86%     91.86% |      106979      8.14%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1314067                      
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 |       22882     49.07%     49.07% |       23746     50.93%    100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total        46628                      
-system.ruby.L1Cache_Controller.IS.Data_all_Acks |      526625     61.56%     61.56% |      328796     38.44%    100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total       855421                      
-system.ruby.L1Cache_Controller.IM.Data   |        1737     59.71%     59.71% |        1172     40.29%    100.00%
-system.ruby.L1Cache_Controller.IM.Data::total         2909                      
-system.ruby.L1Cache_Controller.IM.Data_all_Acks |      294916     70.18%     70.18% |      125313     29.82%    100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       420229                      
-system.ruby.L1Cache_Controller.SM.Inv    |           5     71.43%     71.43% |           2     28.57%    100.00%
-system.ruby.L1Cache_Controller.SM.Inv::total            7                      
-system.ruby.L1Cache_Controller.SM.Ack    |       20322     47.96%     47.96% |       22047     52.04%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total        42369                      
-system.ruby.L1Cache_Controller.SM.Ack_all |       22059     48.72%     48.72% |       23219     51.28%    100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total        45278                      
-system.ruby.L1Cache_Controller.M_I.Ifetch |           3     60.00%     60.00% |           2     40.00%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive |      840504     62.87%     62.87% |      496438     37.13%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1336942                      
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 |       12823     46.65%     46.65% |       14663     53.35%    100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total        27486                      
+system.ruby.L1Cache_Controller.IS.Data_all_Acks |      589278     66.24%     66.24% |      300325     33.76%    100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total       889603                      
+system.ruby.L1Cache_Controller.IM.Data   |         528     32.39%     32.39% |        1102     67.61%    100.00%
+system.ruby.L1Cache_Controller.IM.Data::total         1630                      
+system.ruby.L1Cache_Controller.IM.Data_all_Acks |      303940     70.36%     70.36% |      128024     29.64%    100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total       431964                      
+system.ruby.L1Cache_Controller.SM.Inv    |           0      0.00%      0.00% |           1    100.00%    100.00%
+system.ruby.L1Cache_Controller.SM.Inv::total            1                      
+system.ruby.L1Cache_Controller.SM.Ack    |       12681     52.16%     52.16% |       11631     47.84%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total        24312                      
+system.ruby.L1Cache_Controller.SM.Ack_all |       13209     50.92%     50.92% |       12733     49.08%    100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total        25942                      
+system.ruby.L1Cache_Controller.M_I.Ifetch |           4     80.00%     80.00% |           1     20.00%    100.00%
 system.ruby.L1Cache_Controller.M_I.Ifetch::total            5                      
-system.ruby.L1Cache_Controller.M_I.WB_Ack |     1484202     87.25%     87.25% |      216896     12.75%    100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total      1701098                      
-system.ruby.L2Cache_Controller.L1_GET_INSTR       786404      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETS        1430091      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_GETX         423139      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_UPGRADE        42377      0.00%      0.00%
-system.ruby.L2Cache_Controller.L1_PUTX        1701098      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement        98966      0.00%      0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean        14683      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Data        180859      0.00%      0.00%
-system.ruby.L2Cache_Controller.Mem_Ack         116450      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data          44624      0.00%      0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean         2640      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack               2261      0.00%      0.00%
-system.ruby.L2Cache_Controller.Ack_all           7632      0.00%      0.00%
-system.ruby.L2Cache_Controller.Unblock          46628      0.00%      0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock      1779574      0.00%      0.00%
-system.ruby.L2Cache_Controller.MEM_Inv           5602      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR        15956      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS        33107      0.00%      0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX       131796      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GET_INSTR       770425      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS        69021      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX         3068      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L1_UPGRADE        42369      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement          213      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7168      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS.MEM_Inv            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GET_INSTR           19      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS      1280960      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX       258119      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement        98446      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean         7182      0.00%      0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv         2554      0.00%      0.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack |     1129907     64.87%     64.87% |      611895     35.13%    100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total      1741802                      
+system.ruby.L2Cache_Controller.L1_GET_INSTR       820269      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETS        1434154      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_GETX         433597      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_UPGRADE        24313      0.00%      0.00%
+system.ruby.L2Cache_Controller.L1_PUTX        1741802      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement       100151      0.00%      0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean        13512      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Data        181234      0.00%      0.00%
+system.ruby.L2Cache_Controller.Mem_Ack         116748      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data          25809      0.00%      0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean         2171      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack               1865      0.00%      0.00%
+system.ruby.L2Cache_Controller.Ack_all           7090      0.00%      0.00%
+system.ruby.L2Cache_Controller.Unblock          27486      0.00%      0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock      1794848      0.00%      0.00%
+system.ruby.L2Cache_Controller.MEM_Inv           6170      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR        15428      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS        32321      0.00%      0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX       133485      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GET_INSTR       804811      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS        69338      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX         1923      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE        24312      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement          291      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean         6674      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS.MEM_Inv            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GET_INSTR           26      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS      1304621      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX       274075      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement        99609      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean         6704      0.00%      0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv         2851      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS        46624      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX        30155      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX      1701098      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement          307      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          333      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT.MEM_Inv          241      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack       116450      0.00%      0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv         2554      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data          495      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all           53      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_I.MEM_Inv          241      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data          141      0.00%      0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all          192      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack           2043      0.00%      0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all         7168      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack            218      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all          219      0.00%      0.00%
-system.ruby.L2Cache_Controller.S_I.MEM_Inv            6      0.00%      0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data        33107      0.00%      0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data        15956      0.00%      0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data       131796      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS          233      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        45437      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS          146      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETX            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1734137      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_UPGRADE            1      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data        43981      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2640      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data            7      0.00%      0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock        46621      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS        27482      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX        24111      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX      1741802      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement          251      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean          134      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT.MEM_Inv          229      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack       116748      0.00%      0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv         2851      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data          442      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.Ack_all           38      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_I.MEM_Inv          229      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data           52      0.00%      0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all           82      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack           1570      0.00%      0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all         6674      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack            295      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all          296      0.00%      0.00%
+system.ruby.L2Cache_Controller.S_I.MEM_Inv            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data        32321      0.00%      0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data        15428      0.00%      0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data       133485      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS          235      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETX            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        26235      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS          157      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETX            2      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1768613      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data        25310      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2170      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock            6      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data            5      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean            1      0.00%      0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock        27480      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 4fb206696..d9f455151 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,152 +1,152 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.141985                       # Number of seconds simulated
-sim_ticks                                5141984685500                       # Number of ticks simulated
-final_tick                               5141984685500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.140310                       # Number of seconds simulated
+sim_ticks                                5140310078000                       # Number of ticks simulated
+final_tick                               5140310078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 264541                       # Simulator instruction rate (inst/s)
-host_op_rate                                   525842                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5597553756                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1010248                       # Number of bytes of host memory used
-host_seconds                                   918.61                       # Real time elapsed on the host
-sim_insts                                   243010444                       # Number of instructions simulated
-sim_ops                                     483045307                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 269101                       # Simulator instruction rate (inst/s)
+host_op_rate                                   534933                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5691143534                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1043812                       # Number of bytes of host memory used
+host_seconds                                   903.21                       # Real time elapsed on the host
+sim_insts                                   243055556                       # Number of instructions simulated
+sim_ops                                     483158347                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           439936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4996672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           212288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2043456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         1408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           288960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          3313664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           444224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5333440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           157504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1822656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           355648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          3199424                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11325056                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       439936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       212288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       288960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          941184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9131200                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9131200                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11343552                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       444224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       157504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       355648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          957376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9153408                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9153408                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6874                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             78073                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3317                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             31929                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           22                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4515                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             51776                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              6941                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             83335                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2461                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             28479                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           31                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5557                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             49991                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                176954                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          142675                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142675                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                177243                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          143022                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143022                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               85558                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              971740                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               41285                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              397406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           274                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               56196                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              644433                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5514                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2202468                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          85558                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          41285                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          56196                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             183039                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1775812                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1775812                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1775812                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               86420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1037572                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               30641                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              354581                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           386                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               69188                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              622418                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2206784                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          86420                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          30641                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          69188                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             186249                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1780711                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1780711                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1780711                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              85558                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             971740                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              41285                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             397406                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          274                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              56196                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             644433                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5514                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3978280                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         91559                       # Number of read requests accepted
-system.physmem.writeReqs                        81706                       # Number of write requests accepted
-system.physmem.readBursts                       91559                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      81706                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5853184                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5229184                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5859776                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5229184                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu0.inst              86420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1037572                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              30641                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             354581                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          386                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              69188                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             622418                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3987495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         86962                       # Number of read requests accepted
+system.physmem.writeReqs                        83127                       # Number of write requests accepted
+system.physmem.readBursts                       86962                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      83127                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5558208                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5320128                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5565568                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5320128                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          24142                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5703                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4852                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5373                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5511                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5930                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4999                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5647                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5865                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5509                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                5229                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5185                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5201                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               6216                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6911                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6949                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6376                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5797                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4843                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5036                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5163                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5363                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4815                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4988                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5321                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4852                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4657                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4410                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4367                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               5498                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5314                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5778                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5504                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          33935                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5197                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4660                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5410                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5303                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5131                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                4781                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5593                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5451                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5257                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                4895                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5205                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5208                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5485                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6574                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6603                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6094                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5588                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5124                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5267                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4836                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5431                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5206                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5103                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5105                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5093                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5184                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5317                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5091                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4613                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5354                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5452                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5140984417000                       # Total gap between requests
+system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5136428746000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   91559                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   86962                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  81706                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     86389                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4169                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       743                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       148                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  83127                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     81204                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4342                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::4                        44                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -161,1114 +161,1119 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       125                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        62                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        54                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::10                       52                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::12                       52                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::14                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4169                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::19                     4441                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4540                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::22                     4800                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::29                     4596                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::31                     4114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4072                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::37                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       87                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::58                       14                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::60                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        40084                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      276.476998                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     167.125046                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     300.303961                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15966     39.83%     39.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9813     24.48%     64.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4306     10.74%     75.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2350      5.86%     80.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1723      4.30%     85.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1131      2.82%     88.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          740      1.85%     89.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          595      1.48%     91.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3460      8.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          40084                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4098                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.316984                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      232.117398                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            4096     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        39704                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      273.985896                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     164.719261                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     301.548634                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16089     40.52%     40.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9815     24.72%     65.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4115     10.36%     75.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2259      5.69%     81.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1546      3.89%     85.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1077      2.71%     87.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          717      1.81%     89.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          581      1.46%     91.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3505      8.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          39704                       # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::mean        21.636024                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-511            4011     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023            1      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1536-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4098                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4098                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.938019                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.673577                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.950142                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                68      1.66%      1.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 4      0.10%      1.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                3      0.07%      1.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               4      0.10%      1.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3475     84.80%     86.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              74      1.81%     88.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              28      0.68%     89.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             103      2.51%     91.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              14      0.34%     92.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              88      2.15%     94.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              45      1.10%     95.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               5      0.12%     95.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               8      0.20%     95.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               8      0.20%     95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.05%     95.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.10%     95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             126      3.07%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.02%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.02%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              13      0.32%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.02%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.05%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.05%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            15      0.37%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4098                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1118460500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2833260500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    457280000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12229.49                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4014                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4014                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.709268                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.149216                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.865339                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                66      1.64%      1.64% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::8-11                1      0.02%      1.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               5      0.12%      1.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3286     81.86%     83.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             102      2.54%     86.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              31      0.77%     87.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             110      2.74%     89.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              16      0.40%     90.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             107      2.67%     92.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              56      1.40%     94.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               3      0.07%     94.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              12      0.30%     94.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              20      0.50%     95.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.05%     95.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               4      0.10%     95.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             148      3.69%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.10%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              15      0.37%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.02%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.07%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            10      0.25%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4014                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1058164225                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2686545475                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    434235000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12184.23                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30979.49                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.14                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.02                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.14                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.02                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30934.23                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.08                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.03                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.08                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.03                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         7.88                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      73104                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     59973                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.93                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.40                       # Row buffer hit rate for writes
-system.physmem.avgGap                     29671222.79                       # Average gap between requests
-system.physmem.pageHitRate                      76.85                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  146323800                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   79666125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 342256200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                267792480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           250395110160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            96409908585                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2240143266750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             2587784324100                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.897651                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   3686083069500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    128013860000                       # Time in different power states
+system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         6.40                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      68775                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     61495                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.19                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.98                       # Row buffer hit rate for writes
+system.physmem.avgGap                     30198476.95                       # Average gap between requests
+system.physmem.pageHitRate                      76.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  145461960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   79191750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 323902800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                269956800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           250383413280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            96312598470                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2240118682500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             2587633207560                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.890236                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   3686035921978                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    128007880000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     19995411750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     19846503022                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  156711240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   85300875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 371092800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                261662400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           250395110160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96741256995                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2232099467250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             2580110601720                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.145421                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   3685614437250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    128013860000                       # Time in different power states
+system.physmem_1.actEnergy                  154700280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   84191250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 353503800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                268706160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           250383413280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            96598721655                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2233305647250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             2581148883675                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.102542                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   3685636098978                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    128007880000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     20427995000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     20213469772                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                      1069587616                       # number of cpu cycles simulated
+system.cpu0.numCycles                      1072285216                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   72296493                       # Number of instructions committed
-system.cpu0.committedOps                    147472982                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            135372886                       # Number of integer alu accesses
+system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu0.committedInsts                   71949475                       # Number of instructions committed
+system.cpu0.committedOps                    146629560                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            134558001                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     990052                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14329607                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   135372886                       # number of integer instructions
+system.cpu0.num_func_calls                     963710                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14252688                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   134558001                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          248231827                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         116398223                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          246915369                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         115616478                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            84256506                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           56232303                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13832544                       # number of memory refs
-system.cpu0.num_load_insts                   10299641                       # Number of load instructions
-system.cpu0.num_store_insts                   3532903                       # Number of store instructions
-system.cpu0.num_idle_cycles              1014098909.517961                       # Number of idle cycles
-system.cpu0.num_busy_cycles              55488706.482039                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.051879                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.948121                       # Percentage of idle cycles
-system.cpu0.Branches                         15685270                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                94460      0.06%      0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                133436032     90.48%     90.55% # Class of executed instruction
-system.cpu0.op_class::IntMult                   61341      0.04%     90.59% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    50787      0.03%     90.62% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.62% # Class of executed instruction
-system.cpu0.op_class::MemRead                10297804      6.98%     97.60% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3532903      2.40%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            83804950                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           55920141                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13826864                       # number of memory refs
+system.cpu0.num_load_insts                   10217566                       # Number of load instructions
+system.cpu0.num_store_insts                   3609298                       # Number of store instructions
+system.cpu0.num_idle_cycles              1017808473.109560                       # Number of idle cycles
+system.cpu0.num_busy_cycles              54476742.890440                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050804                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949196                       # Percentage of idle cycles
+system.cpu0.Branches                         15573120                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                93860      0.06%      0.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu                132602493     90.43%     90.50% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58992      0.04%     90.54% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    49730      0.03%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.57% # Class of executed instruction
+system.cpu0.op_class::MemRead                10215736      6.97%     97.54% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3609298      2.46%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 147473327                       # Class of executed instruction
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements          1636478                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999449                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19597198                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1636990                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            11.971483                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 146630109                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          1637599                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999082                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19598772                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1638111                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            11.964252                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.606115                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   212.665668                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   114.727666                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.360559                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.415363                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.224077                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.195837                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   211.604771                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   116.198475                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.359757                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.413291                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.226950                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999998                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          358                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          241                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          250                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88196545                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88196545                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5063587                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2515932                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      3866751                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11446270                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3403152                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1746042                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2940280                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8089474                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        21659                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10037                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        27859                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        59555                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8466739                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4261974                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6807031                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19535744                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8488398                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4272011                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6834890                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19595299                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       370405                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       158702                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       782991                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1312098                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       124734                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        62333                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       138967                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       326034                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       153415                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        61804                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       191235                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       406454                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       495139                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       221035                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       921958                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1638132                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       648554                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       282839                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1113193                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2044586                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2348294000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12545085500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14893379500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   4136391991                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   6933238397                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  11069630388                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   6484685991                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  19478323897                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  25963009888                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   6484685991                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  19478323897                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  25963009888                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5433992                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2674634                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4649742                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     12758368                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3527886                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1808375                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      3079247                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8415508                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       175074                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        71841                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       219094                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       466009                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8961878                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4483009                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7728989                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21173876                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9136952                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4554850                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7948083                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21639885                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.068164                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.059336                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.168395                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.102842                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.035357                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.034469                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.045130                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.038742                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.876287                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.860289                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.872845                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.872202                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.055249                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049305                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.119286                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.077366                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070981                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062096                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.140058                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.094482                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14796.877166                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16022.004723                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11350.813354                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 66359.584666                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 49891.257615                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 33952.380390                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 29337.824286                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21127.127154                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15849.156166                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22927.128122                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17497.706055                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12698.419087                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       213021                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88194499                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88194499                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4977444                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2398985                       # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       218464                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       466052                       # number of SoftPFReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.069281                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.060110                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.161402                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.102553                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038344                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.032699                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042761                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.038848                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.878841                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.857984                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.871105                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.872152                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.056824                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.049201                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115082                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.077255                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.072949                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062049                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.135228                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.094375                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14654.361060                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16189.128450                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11427.191997                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 66580.830690                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 49284.446103                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 31348.634727                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28389.287283                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20990.242910                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15405.352072                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22153.065901                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17387.243489                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12339.140939                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       206703                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            22215                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            22011                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.589061                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.390895                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1547054                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1547054                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           65                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       367229                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       367294                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1711                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        33525                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        35236                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1776                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       400754                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       402530                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1776                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       400754                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       402530                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       158637                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       415762                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       574399                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        60622                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       105442                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       166064                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        61803                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       187828                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       249631                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       219259                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       521204                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       740463                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       281062                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       709032                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       990094                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       185046                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       202918                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total       387964                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3480                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2043                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         5523                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       188526                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       204961                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total       393487                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2187272000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5900092500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8087364500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3897729991                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   6072748397                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9970478388                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1081694500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2966872000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   4048566500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6085001991                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11972840897                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  18057842888                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7166696491                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  14939712897                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  22106409388                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30549904500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32777781000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63327685500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    637496500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    432772500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1070269000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31187401000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33210553500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64397954500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059312                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.089416                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045021                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033523                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.034243                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019733                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.860275                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.857294                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.535678                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048909                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.067435                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.034971                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061706                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.089208                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.045753                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13787.905722                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14191.033572                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14079.698084                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64295.635099                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57593.258825                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 60039.974877                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17502.297623                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15795.685414                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16218.204069                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27752.575680                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22971.506161                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24387.231891                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25498.631942                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21070.576359                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22327.586459                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165093.568626                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 161532.150918                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 163230.829407                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183188.649425                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211831.864905                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 193783.994206                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165427.585585                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 162033.525890                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 163659.674907                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks      1548077                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1548077                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           70                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       363716                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       363786                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1660                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        33557                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        35217                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1730                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       397273                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       399003                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1730                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       397273                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       399003                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       153356                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       421425                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       574781                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        53517                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        99670                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       153187                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58722                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       186896                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       245618                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       206873                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       521095                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       727968                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       265595                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       707991                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       973586                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       176326                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       193522                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total       369848                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3494                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2876                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         6370                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       179820                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       196398                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total       376218                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2092039500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   6051222000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8143261500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3446784995                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5707170401                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9153955396                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1012070500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2960619500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3972690000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   5538824495                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11758392401                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  17297216896                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6550894995                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  14719011901                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  21269906896                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30675451000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32998765500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63674216500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    673827500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    612020000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1285847500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31349278500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33610785500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64960064000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.060083                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086633                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045028                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.031715                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031991                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018219                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.857969                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.855500                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.527018                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048793                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065299                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.034382                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061648                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086356                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.044992                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13641.719268                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14358.953550                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14167.589917                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64405.422483                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57260.664202                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59756.737817                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17234.946017                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15840.999807                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.262473                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26774.032837                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22564.776866                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23760.957756                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24664.978614                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20789.829109                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21846.972837                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.868883                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.203532                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192852.747567                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212802.503477                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201859.890110                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174336.995329                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.088453                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172666.018107                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           856629                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.743625                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          130224655                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           857141                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           151.929093                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     149031497500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   143.311880                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   129.505351                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   237.926394                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.279906                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.252940                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.464700                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997546                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           862079                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.743965                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          129387157                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           862591                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           149.998269                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     149036221500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   146.474513                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   126.887139                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   237.382314                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.286083                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.247826                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.463637                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997547                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          153                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          308                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          277                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        131961129                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       131961129                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     88027171                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     39361631                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2835853                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      130224655                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     88027171                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     39361631                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2835853                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       130224655                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     88027171                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     39361631                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2835853                       # number of overall hits
-system.cpu0.icache.overall_hits::total      130224655                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       330869                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       176943                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       371512                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       879324                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       330869                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       176943                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       371512                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        879324                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       330869                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       176943                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       371512                       # number of overall misses
-system.cpu0.icache.overall_misses::total       879324                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2702410000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5371996473                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8074406473                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2702410000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5371996473                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8074406473                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2702410000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5371996473                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8074406473                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     88358040                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     39538574                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3207365                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    131103979                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     88358040                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     39538574                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3207365                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    131103979                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     88358040                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     39538574                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3207365                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    131103979                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003745                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004475                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.115831                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.006707                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003745                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004475                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.115831                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.006707                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003745                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004475                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.115831                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.006707                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15272.771457                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14459.819529                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9182.515743                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15272.771457                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14459.819529                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  9182.515743                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15272.771457                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14459.819529                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  9182.515743                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        11595                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        131136403                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       131136403                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     87656734                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     38708215                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      3022208                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      129387157                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     87656734                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     38708215                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      3022208                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       129387157                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     87656734                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     38708215                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      3022208                       # number of overall hits
+system.cpu0.icache.overall_hits::total      129387157                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       322605                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       163640                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       400399                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       886644                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       322605                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       163640                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       400399                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        886644                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       322605                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       163640                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       400399                       # number of overall misses
+system.cpu0.icache.overall_misses::total       886644                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2424218000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5939623464                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   8363841464                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2424218000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   5939623464                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   8363841464                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2424218000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   5939623464                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   8363841464                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     87979339                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     38871855                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3422607                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    130273801                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     87979339                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     38871855                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3422607                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    130273801                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     87979339                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     38871855                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3422607                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    130273801                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003667                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004210                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.116987                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.006806                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003667                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004210                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.116987                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.006806                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003667                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004210                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.116987                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.006806                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14814.336348                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14834.261484                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  9433.145055                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14814.336348                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14834.261484                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9433.145055                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14814.336348                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14834.261484                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  9433.145055                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        13267                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              455                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              575                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.483516                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.073043                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        22174                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        22174                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        22174                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        22174                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        22174                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        22174                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       176943                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       349338                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       526281                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       176943                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       349338                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       526281                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       176943                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       349338                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       526281                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2525467000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4769426473                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7294893473                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2525467000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4769426473                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7294893473                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2525467000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4769426473                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   7294893473                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004475                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.108917                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004014                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004475                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.108917                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004014                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004475                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.108917                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004014                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14272.771457                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13652.755993                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13861.213825                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14272.771457                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13652.755993                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13861.213825                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14272.771457                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13652.755993                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13861.213825                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       862079                       # number of writebacks
+system.cpu0.icache.writebacks::total           862079                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        24042                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        24042                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        24042                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        24042                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        24042                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        24042                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       163640                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       376357                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       539997                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       163640                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       376357                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       539997                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       163640                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       376357                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       539997                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2260578000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5251926966                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   7512504966                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2260578000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5251926966                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   7512504966                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2260578000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5251926966                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   7512504966                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.109962                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004145                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.109962                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004145                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.109962                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004145                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.336348                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13954.641380                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13912.123523                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.336348                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13954.641380                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13912.123523                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.336348                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13954.641380                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13912.123523                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2608369012                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2606017772                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   35935781                       # Number of instructions committed
-system.cpu1.committedOps                     69853480                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             64823976                       # Number of integer alu accesses
+system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
+system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu1.committedInsts                   35434797                       # Number of instructions committed
+system.cpu1.committedOps                     68967057                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             63950611                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     488968                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6599189                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    64823976                       # number of integer instructions
+system.cpu1.num_func_calls                     471158                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6540301                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    63950611                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          120030856                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          55861909                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          118144126                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          55187106                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36569866                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           27235503                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4739526                       # number of memory refs
-system.cpu1.num_load_insts                    2929606                       # Number of load instructions
-system.cpu1.num_store_insts                   1809920                       # Number of store instructions
-system.cpu1.num_idle_cycles              2476291441.144386                       # Number of idle cycles
-system.cpu1.num_busy_cycles              132077570.855614                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.050636                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.949364                       # Percentage of idle cycles
-system.cpu1.Branches                          7267259                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                35769      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 65023245     93.08%     93.14% # Class of executed instruction
-system.cpu1.op_class::IntMult                   31643      0.05%     93.18% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    24977      0.04%     93.22% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.22% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2928241      4.19%     97.41% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1809920      2.59%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            36132535                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           26987071                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4484181                       # number of memory refs
+system.cpu1.num_load_insts                    2795215                       # Number of load instructions
+system.cpu1.num_store_insts                   1688966                       # Number of store instructions
+system.cpu1.num_idle_cycles              2475079667.780020                       # Number of idle cycles
+system.cpu1.num_busy_cycles              130938104.219980                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.050245                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.949755                       # Percentage of idle cycles
+system.cpu1.Branches                          7181908                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                31577      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 64398957     93.38%     93.42% # Class of executed instruction
+system.cpu1.op_class::IntMult                   30119      0.04%     93.47% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    23752      0.03%     93.50% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.50% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2793855      4.05%     97.55% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1688966      2.45%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  69853795                       # Class of executed instruction
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               28595724                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         28595724                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           274281                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            25954960                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               25419524                       # Number of BTB hits
+system.cpu1.op_class::total                  68967226                       # Class of executed instruction
+system.cpu2.branchPred.lookups               28923329                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         28923329                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           299282                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26177543                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               25594622                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.937057                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 541766                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             58217                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       155590039                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.773202                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 576797                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             63162                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       157005453                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9827756                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     141445049                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   28595724                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          25961290                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    144324316                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 577708                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     89529                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles                4628                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             9926                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        52140                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles           25                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles         1381                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3207378                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               141789                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2491                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         154597903                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.800587                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.004500                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          10540975                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     142872413                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   28923329                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26171419                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    144748563                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 631577                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                    103277                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles               10569                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             7821                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        68344                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles           26                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles         1893                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3422619                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               155063                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2960                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         155796605                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.805087                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.007326                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0               100285595     64.87%     64.87% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  850088      0.55%     65.42% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23359910     15.11%     80.53% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  558025      0.36%     80.89% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  768716      0.50%     81.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  809103      0.52%     81.91% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  512827      0.33%     82.24% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  703407      0.45%     82.70% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                26750232     17.30%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0               100986274     64.82%     64.82% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  876971      0.56%     65.38% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23450168     15.05%     80.43% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  581136      0.37%     80.81% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  798057      0.51%     81.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  839354      0.54%     81.86% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  536255      0.34%     82.20% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  727896      0.47%     82.67% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27000494     17.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           154597903                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.183789                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.909088                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 8590820                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             95748375                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 20322096                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              4023271                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                289506                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             275783905                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                289506                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                10203934                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               77122652                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4692669                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 22463307                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             14202064                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             274713209                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               193941                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               5398657                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 70031                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               7189088                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          328421156                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            598952608                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       367856783                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups              202                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            317944423                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                10476733                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            154897                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        156262                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 19984245                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6287198                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3639298                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           400920                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          367403                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 273029174                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             403661                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                271361789                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            92310                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7713990                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     11716947                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         58327                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    154597903                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.755275                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.385225                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           155796605                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.184219                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.909984                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 9166270                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             95860787                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 22254534                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              3994693                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                316440                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             278480395                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                316440                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                10781716                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               77380942                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       5123914                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 24366684                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             13623085                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             277321096                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               194260                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               5340054                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 70865                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               6669514                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          331396172                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            605049332                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       371619608                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups              206                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            320040545                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                11355627                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            162880                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        164114                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 19801512                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6563978                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3714528                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           447098                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          397095                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 275506715                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             407720                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                273559358                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            95175                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        8352705                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     12694060                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         62726                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    155796605                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.755875                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.385543                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           93164208     60.26%     60.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5135729      3.32%     63.58% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3649233      2.36%     65.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            3187928      2.06%     68.01% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           23055647     14.91%     82.92% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            2154571      1.39%     84.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           23598215     15.26%     99.58% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             439899      0.28%     99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             212473      0.14%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           93882329     60.26%     60.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5118192      3.29%     63.54% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3721128      2.39%     65.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            3254343      2.09%     68.02% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           23198440     14.89%     82.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            2207021      1.42%     84.33% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           23723391     15.23%     99.56% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             467418      0.30%     99.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             224343      0.14%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      154597903                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      155796605                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                1212353     81.77%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     81.77% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                211907     14.29%     96.06% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                58391      3.94%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                1207560     81.79%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     81.79% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                207213     14.03%     95.82% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                61669      4.18%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            71762      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            261142020     96.23%     96.26% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               52428      0.02%     96.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                48121      0.02%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                 75      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6661415      2.45%     98.75% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3385968      1.25%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            77609      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            263069409     96.17%     96.19% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               56423      0.02%     96.21% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                50250      0.02%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                 74      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6863260      2.51%     98.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3442333      1.26%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             271361789                       # Type of FU issued
-system.cpu2.iq.rate                          1.744082                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    1482651                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.005464                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         698896144                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        281150786                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    269884047                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                298                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes               286                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses          110                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             272772537                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                    141                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          697485                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             273559358                       # Type of FU issued
+system.cpu2.iq.rate                          1.742356                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    1476442                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.005397                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         704486629                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        284271419                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    272061524                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                309                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes               294                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses          118                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             274958042                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                    149                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          723498                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1044107                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         5365                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         4726                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       557112                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1134318                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         5680                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5091                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       595155                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       749552                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        25864                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       712054                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        23601                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                289506                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               69224885                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              4893125                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          273432835                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            29776                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6287198                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3639298                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            235948                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                164149                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              4411192                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          4726                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        153905                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       164065                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              317970                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            270855594                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6536848                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           455372                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                316440                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               69933639                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              4486006                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          275914435                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            35023                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6563978                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3714528                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            243237                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                162474                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              4012628                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5091                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        167077                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       180895                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              347972                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            273011944                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6727791                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           497508                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     9843230                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                27477788                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3306382                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.740829                       # Inst execution rate
-system.cpu2.iew.wb_sent                     270693369                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    269884157                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                210625616                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                345602988                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                    10089541                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27708179                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3361750                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.738869                       # Inst execution rate
+system.cpu2.iew.wb_sent                     272840114                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    272061642                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                212265363                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                348191102                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.734585                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.609444                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.732817                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.609623                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        7711989                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         345334                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           277097                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    153447715                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.731657                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.637088                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        8350016                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         344994                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           302940                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    154548999                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.731242                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.636335                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     96780970     63.07%     63.07% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4222028      2.75%     65.82% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1231000      0.80%     66.62% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24221852     15.79%     82.41% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       924771      0.60%     83.01% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       693299      0.45%     83.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       425605      0.28%     83.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     22935468     14.95%     98.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2012722      1.31%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     97452573     63.06%     63.06% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4255618      2.75%     65.81% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1276058      0.83%     66.64% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24388972     15.78%     82.42% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       952831      0.62%     83.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       707614      0.46%     83.49% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       433779      0.28%     83.77% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23017420     14.89%     98.66% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2064134      1.34%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    153447715                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           134778170                       # Number of instructions committed
-system.cpu2.commit.committedOps             265718845                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    154548999                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           135671284                       # Number of instructions committed
+system.cpu2.commit.committedOps             267561730                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8325277                       # Number of memory references committed
-system.cpu2.commit.loads                      5243091                       # Number of loads committed
-system.cpu2.commit.membars                     153740                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27132938                       # Number of branches committed
+system.cpu2.commit.refs                       8549033                       # Number of memory references committed
+system.cpu2.commit.loads                      5429660                       # Number of loads committed
+system.cpu2.commit.membars                     149565                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27339879                       # Number of branches committed
 system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                242753564                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              416792                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        41984      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       257254606     96.81%     96.83% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          50787      0.02%     96.85% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           46205      0.02%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5243061      1.97%     98.84% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       3082186      1.16%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                244517945                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              438137                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        46306      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       258863559     96.75%     96.77% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          54521      0.02%     96.79% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           48345      0.02%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5429610      2.03%     98.83% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       3119373      1.17%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        265718845                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              2012722                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   424836983                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  548017282                       # The number of ROB writes
-system.cpu2.timesIdled                         100227                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                         992136                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4909996040                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  134778170                       # Number of Instructions Simulated
-system.cpu2.committedOps                    265718845                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.154416                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.154416                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.866239                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.866239                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               360832495                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              216221900                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    73134                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   73024                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                137826475                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               106107258                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               87959882                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                137617                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq              3552161                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3552161                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57740                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57740                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1667                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1667                       # Transaction distribution
+system.cpu2.commit.op_class_0::total        267561730                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              2064134                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                   428366748                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  553077080                       # The number of ROB writes
+system.cpu2.timesIdled                         112413                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1208848                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4910585835                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  135671284                       # Number of Instructions Simulated
+system.cpu2.committedOps                    267561730                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.157249                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.157249                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.864118                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.864118                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               363754203                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              218036965                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    73086                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                138800226                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               106739606                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               88774953                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                143862                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq              3545348                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             3545348                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1644                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1644                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7080234                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1154                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7066648                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27868                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      7124546                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95256                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95256                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3334                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3334                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7223136                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      7110880                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95268                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3288                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3288                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 7209436                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3540117                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2308                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3533324                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13934                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      3568475                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027808                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027808                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6668                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6668                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6602951                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2194728                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total      3561720                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027856                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027856                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  6596152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2378920                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                41500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 4000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy                 2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              3095000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              5419500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 7000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                 8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy               748000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy               921000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                22000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                40500                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                15000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy                21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            140118000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            199977500                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              340000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              507000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy              142000                       # Layer occupancy (ticks)
+system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy             8907000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy            11026500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer16.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           119418499                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy           144387981                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy             1032000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy             1052000                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           295238000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           283491000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            23500000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            31080000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy              920000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy              979000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47573                       # number of replacements
-system.iocache.tags.tagsinuse                0.105025                       # Cycle average of tags in use
+system.iocache.tags.replacements                47579                       # number of replacements
+system.iocache.tags.tagsinuse                0.099877                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47589                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47595                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000694858009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.105025                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006564                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.006564                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000697713509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.099877                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006242                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.006242                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428652                       # Number of tag accesses
-system.iocache.tags.data_accesses              428652                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          908                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              908                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428706                       # Number of tag accesses
+system.iocache.tags.data_accesses              428706                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          914                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              914                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          908                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               908                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          908                       # number of overall misses
-system.iocache.overall_misses::total              908                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide     17834920                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     17834920                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3008484579                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   3008484579                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide     17834920                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     17834920                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide     17834920                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     17834920                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          908                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            908                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          914                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               914                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          914                       # number of overall misses
+system.iocache.overall_misses::total              914                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    126880276                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    126880276                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3631346705                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   3631346705                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    126880276                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    126880276                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    126880276                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    126880276                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          914                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            914                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          908                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             908                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          908                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            908                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          914                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             914                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          914                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            914                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1277,323 +1282,327 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 19641.982379                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 19641.982379                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 64393.933626                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 64393.933626                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 19641.982379                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 19641.982379                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 19641.982379                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 19641.982379                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138818.682713                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 138818.682713                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77725.742830                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 77725.742830                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138818.682713                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 138818.682713                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138818.682713                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 138818.682713                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           745                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   69                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.797101                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          150                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          150                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        23200                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        23200                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          150                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          150                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          150                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          150                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     10334920                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     10334920                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1848484579                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1848484579                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     10334920                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     10334920                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     10334920                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     10334920                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.165198                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.165198                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.496575                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.496575                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.165198                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.165198                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.165198                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.165198                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68899.466667                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79676.059440                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79676.059440                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68899.466667                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68899.466667                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          756                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          756                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        27936                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        27936                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          756                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          756                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          756                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          756                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     89080276                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     89080276                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   2234546705                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2234546705                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     89080276                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     89080276                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     89080276                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     89080276                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.827133                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.597945                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.597945                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.827133                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.827133                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.052910                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79988.069337                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79988.069337                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 117831.052910                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 117831.052910                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104099                       # number of replacements
-system.l2c.tags.tagsinuse                64798.751400                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4622477                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168145                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    27.491017                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   104604                       # number of replacements
+system.l2c.tags.tagsinuse                64807.192442                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4639119                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168682                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    27.502158                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50975.916354                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.134600                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1575.171206                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4997.364493                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      516.989893                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1851.248692                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker     5.076348                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst      959.125226                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3917.724589                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.777831                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   51005.596123                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.135096                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1646.370611                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4933.032602                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      515.170721                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1886.198863                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker     9.247587                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      884.114832                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     3927.326006                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.778284                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.024035                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.076254                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.007889                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.028248                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000077                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.014635                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.059780                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.988750                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64046                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3569                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7409                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52933                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.977264                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 41263442                       # Number of tag accesses
-system.l2c.tags.data_accesses                41263442                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        19237                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        10440                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        11603                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         6238                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        52514                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        10913                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 110945                       # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.025122                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu2.inst       0.013491                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.059926                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.988879                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64078                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          267                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2840                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6913                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        54019                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.977753                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 41426818                       # Number of tag accesses
+system.l2c.tags.data_accesses                41426818                       # Number of data accesses
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+system.l2c.ReadReq_hits::total                 118250                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1547054                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1547054                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              89                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              72                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data             110                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 271                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            61093                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            33233                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            64950                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               159276                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        323982                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        173626                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        344819                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            842427                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       508184                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       215306                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       591519                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          1315009                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         19237                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         10442                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              323982                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              569277                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         11603                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          6238                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              173626                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              248539                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         52514                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         10913                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              344819                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              656469                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2427659                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        19237                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        10442                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             323982                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             569277                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        11603                       # number of overall hits
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-system.l2c.overall_hits::cpu1.inst             173626                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             248539                       # number of overall hits
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-system.l2c.overall_hits::cpu2.itb.walker        10913                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             344819                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             656469                       # number of overall hits
-system.l2c.overall_hits::total                2427659                       # number of overall hits
+system.l2c.WritebackDirty_hits::writebacks      1548077                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         1548077                       # number of WritebackDirty hits
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+system.l2c.WritebackClean_hits::total          861736                       # number of WritebackClean hits
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+system.l2c.UpgradeReq_hits::cpu1.data              31                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data             113                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 274                       # number of UpgradeReq hits
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+system.l2c.ReadCleanReq_hits::total            847616                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       512536                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       207467                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::total          1315553                       # number of ReadSharedReq hits
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+system.l2c.demand_hits::cpu2.data              657100                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2441240                       # number of demand (read+write) hits
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+system.l2c.overall_hits::cpu2.data             657100                       # number of overall hits
+system.l2c.overall_hits::total                2441240                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::total                   27                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           513                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           271                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           590                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1374                       # number of UpgradeReq misses
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-system.l2c.ReadExReq_misses::total             129930                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst         6874                       # number of ReadCleanReq misses
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-system.l2c.ReadCleanReq_misses::total           14706                       # number of ReadCleanReq misses
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-system.l2c.ReadSharedReq_misses::total          32791                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::total          32748                       # number of ReadSharedReq misses
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-system.l2c.demand_misses::cpu0.inst              6874                       # number of demand (read+write) misses
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-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.842857                       # miss rate for UpgradeReq accesses
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+system.l2c.overall_accesses::cpu2.dtb.walker        57391                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker        12726                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         376344                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         707354                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2618987                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000540                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.000304                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.844498                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.829670                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.822884                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.834541                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.497223                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.452781                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.378810                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.448562                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.021516                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.015039                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.014768                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.017343                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.029201                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.021742                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.020912                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.024288                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.021516                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.125852                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.015039                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.108362                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000540                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.014768                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.071045                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.067869                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000457                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.021516                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.125852                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.015039                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.108362                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000540                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.014768                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.071045                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.067869                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 140338.709677                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 120847.222222                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 43274.834437                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 38002.857143                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 19164.978292                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126170.600414                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 129572.361059                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 60847.741975                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130352.905323                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 136253.328535                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 72065.140374                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131442.420299                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 137706.092767                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 71995.312691                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 130352.905323                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 127015.785265                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 140338.709677                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 136253.328535                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 131631.123891                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 63857.823198                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 130352.905323                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 127015.785265                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 140338.709677                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 136253.328535                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 131631.123891                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 63857.823198                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1602,210 +1611,208 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               96008                       # number of writebacks
-system.l2c.writebacks::total                    96008                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           22                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total              22                       # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks           60                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total           60                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          271                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          590                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          861                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        27048                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        39843                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         66891                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         3317                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         4515                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total         7832                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         5134                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data        12021                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total        17155                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         3317                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        32182                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           22                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         4515                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        51864                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            91900                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         3317                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        32182                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           22                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         4515                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        51864                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           91900                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data       185046                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data       202918                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total       387964                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3480                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         2043                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total         5523                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data       188526                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data       204961                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       393487                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      3145500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total      3145500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19128000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     41736500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     60864500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3164632000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   4782281000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   7946913000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    403207500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    569013500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total    972221000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    626215500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1539731000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   2165946500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    403207500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3790847500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      3145500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    569013500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   6322012000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  11088226000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    403207500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3790847500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      3145500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    569013500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   6322012000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  11088226000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28236829500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30241305000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  58478134500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    597476500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    409274000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1006750500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28834306000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30650579000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  59484885000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000419                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.000198                       # mshr miss rate for ReadReq accesses
-system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.790087                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.842857                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.523404                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.448699                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.380207                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.231292                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018746                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.012925                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.009137                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.023290                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.019917                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.012728                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018746                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.114641                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000419                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.012925                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.073220                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.035277                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018746                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.114641                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000419                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.012925                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.073220                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.035277                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 142977.272727                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70583.025830                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70739.830508                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70690.476190                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117000.591541                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 120028.135432                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 118803.919810                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121557.883630                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126027.353267                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124134.448417                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121974.191663                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 128086.764828                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126257.446809                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121557.883630                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117794.030825                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126027.353267                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121895.958661                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 120655.342764                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121557.883630                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117794.030825                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126027.353267                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121895.958661                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 120655.342764                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152593.568626                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149032.145990                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150730.826829                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171688.649425                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200329.907000                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 182283.269962                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152946.044577                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 149543.469245                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 151173.698242                       # average overall mshr uncacheable latency
+system.l2c.writebacks::writebacks               96355                       # number of writebacks
+system.l2c.writebacks::total                    96355                       # number of writebacks
+system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           31                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total              31                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          151                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          525                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          676                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        24150                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        37534                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         61684                       # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         2461                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5557                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total         8018                       # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data         4611                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data        12720                       # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total        17331                       # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2461                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        28761                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           31                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         5557                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        50254                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            87064                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2461                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        28761                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           31                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         5557                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        50254                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           87064                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data       176326                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data       193522                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total       369848                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3494                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data         2876                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total         6370                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data       179820                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data       196398                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       376218                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      4040500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total      4040500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     10668000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     37156500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     47824500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2805520000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   4488029000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   7293549000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    296188500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    701637000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total    997825500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    559971000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1624421500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total   2184392500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    296188500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3365491000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      4040500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    701637000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   6112450500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  10479807500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    296188500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3365491000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      4040500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    701637000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   6112450500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  10479807500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28471375500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30579722500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  59051098000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    633646000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    578928500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1212574500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  29105021500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31158651000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60263672500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000540                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.000262                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.829670                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.822884                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.408213                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.452781                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.378810                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.212834                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014766                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.009295                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021742                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.020912                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.012854                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.108362                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000540                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014766                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.071045                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.033243                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.108362                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000540                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014766                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.071045                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.033243                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 130338.709677                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70649.006623                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70774.285714                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70746.301775                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116170.600414                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119572.361059                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 118240.532391                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126261.831924                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124448.179097                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121442.420299                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127706.092767                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126039.611101                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117015.785265                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126261.831924                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121631.123891                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 120369.010153                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117015.785265                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126261.831924                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121631.123891                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 120369.010153                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161470.092329                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.775870                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.153512                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181352.604465                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201296.418637                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190357.064364                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161856.420309                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.551431                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.852761                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             5081876                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5130307                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13937                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13937                       # Transaction distribution
-system.membus.trans_dist::Writeback            142675                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8457                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1667                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1667                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129637                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129637                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         48432                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1667                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1667                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            1                       # Transaction distribution
+system.membus.trans_dist::ReadReq             5063565                       # Transaction distribution
+system.membus.trans_dist::ReadResp            5112222                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13898                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13898                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       143022                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8552                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1672                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1672                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129713                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129713                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         48657                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1644                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1644                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3334                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3334                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7124546                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3067080                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       461494                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10653122                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       142139                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       142139                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10798595                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6668                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6668                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3568475                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6134157                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17466624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     27169256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3035200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3035200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                30211124                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              409                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5475610                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.000304                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.017446                       # Request fanout histogram
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3288                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7110880                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3044046                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       462447                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total     10617373                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141987                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141987                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               10762648                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3561720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6088089                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17501760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     27151569                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3025152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      3025152                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                30183297                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              664                       # Total snoops (count)
+system.membus.snoop_fanout::samples           5457993                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.000301                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.017353                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 5473943     99.97%     99.97% # Request fanout histogram
-system.membus.snoop_fanout::2                    1667      0.03%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 5456349     99.97%     99.97% # Request fanout histogram
+system.membus.snoop_fanout::2                    1644      0.03%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             5475610                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           227177500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             5457993                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           219248500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           301308000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           286800000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1840000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2377080                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           538434425                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           547350354                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy             920000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1398080                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1326481306                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1208209380                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           41176558                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           52355698                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -1815,60 +1822,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.snoop_filter.tot_requests      5040257                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2546109                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests          319                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1148                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1148                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5045321                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2544604                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests          482                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1171                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1171                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            5235870                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7440960                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13939                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13939                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback          1628762                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          950991                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1645                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1645                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           289206                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          289206                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        857150                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1347950                       # Transaction distribution
-system.toL2Bus.trans_dist::MessageReq             920                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError            1                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq        23200                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2570707                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15105454                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        66396                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       204903                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17947460                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54857344                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213491432                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       241048                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       697376                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              269287200                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          238040                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         10439686                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.005090                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.071166                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            5213952                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7425084                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13900                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13900                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      1631207                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       861736                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           94941                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1656                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1656                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           289822                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          289822                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        862602                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1349057                       # Transaction distribution
+system.toL2Bus.trans_dist::MessageReq             979                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        27936                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2586927                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15072185                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        70382                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       205946                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17935440                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    110356800                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213581265                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       259408                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       748104                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              324945577                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          226314                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          8918759                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.005043                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.070832                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               10386543     99.49%     99.49% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  53143      0.51%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                8873785     99.50%     99.50% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  44974      0.50%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           10439686                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         2709674498                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8918759                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3217757998                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           251420                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           405376                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         789952436                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         810539408                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1874874404                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1832719254                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          23291487                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          24003478                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          94859175                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          87328075                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index 2f7887688..508ed63ed 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.061241                       # Nu
 sim_ticks                                 61241011500                       # Number of ticks simulated
 final_tick                                61241011500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 252391                       # Simulator instruction rate (inst/s)
-host_op_rate                                   253648                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              170598134                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 450980                       # Number of bytes of host memory used
-host_seconds                                   358.98                       # Real time elapsed on the host
+host_inst_rate                                 266495                       # Simulator instruction rate (inst/s)
+host_op_rate                                   267822                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              180131185                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451088                       # Number of bytes of host memory used
+host_seconds                                   339.98                       # Real time elapsed on the host
 sim_insts                                    90602850                       # Number of instructions simulated
 sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895           40      2.59%     51.26% # By
 system.physmem.bytesPerActivate::896-1023           47      3.05%     54.31% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          705     45.69%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total           1543                       # Bytes accessed per row activation
-system.physmem.totQLat                       73241750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 365254250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                       73240250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 365252750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4702.82                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        4702.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23452.82                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  23452.73                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          16.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       16.28                       # Average system read bandwidth in MiByte/s
@@ -227,28 +227,28 @@ system.physmem_0.preEnergy                    3440250                       # En
 system.physmem_0.readEnergy                  63772800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             3999824400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2491477695                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34557963000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41122783185                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.511702                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57480391250                       # Time in different power states
+system.physmem_0.actBackEnergy             2491483680                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34557957750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41122783920                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.511714                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57480384250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      2044900000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1713925750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1713932750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                    5360040                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                    2924625                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                  57509400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             3999824400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2555146980                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34502112750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41122878195                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.513254                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57387655250                       # Time in different power states
+system.physmem_1.actBackEnergy             2555148690                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34502111250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41122878405                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.513257                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57387653250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      2044900000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1806574750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1806576750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                20752188                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          17062075                       # Number of conditional branches predicted
@@ -386,8 +386,8 @@ system.cpu.discardedOps                       2176623                       # Nu
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
 system.cpu.cpi                               1.351856                       # CPI: cycles per instruction
 system.cpu.ipc                               0.739724                       # IPC: instructions per cycle
-system.cpu.tickCycles                       109255164                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        13226859                       # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles                       109255161                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        13226862                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            946097                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          3616.872758                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            26263183                       # Total number of references to valid blocks.
@@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data       989217                       # n
 system.cpu.dcache.demand_misses::total         989217                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       989221                       # number of overall misses
 system.cpu.dcache.overall_misses::total        989221                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11919048000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11919048000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2542627500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2542627500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14461675500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14461675500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14461675500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14461675500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11919046000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11919046000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2542633500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2542633500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14461679500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14461679500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14461679500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14461679500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     22509137                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     22509137                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
@@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.036309
 system.cpu.dcache.demand_miss_rate::total     0.036309                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.036309                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.036309                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14619.315580                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14619.256465                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.333358                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.333358                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.323390                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.323390                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.319624                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14619.319624                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.260509                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14619.260509                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       950190
 system.cpu.dcache.demand_mshr_misses::total       950190                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       950193                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       950193                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865351000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865351000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1481616500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1481616500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865349000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865349000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1481625500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1481625500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       156500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       156500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12346967500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12346967500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12347124000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12347124000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12346974500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12346974500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12347131000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12347131000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040136                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040136                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009876                       # mshr miss rate for WriteReq accesses
@@ -516,16 +516,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034877
 system.cpu.dcache.demand_mshr_miss_rate::total     0.034877                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034876                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.034876                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.841188                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.841188                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.358602                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.358602                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.216420                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.216420                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.340097                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.340097                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 5                       # number of replacements
 system.cpu.icache.tags.tagsinuse           689.439811                       # Cycle average of tags in use
@@ -587,6 +587,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks            5                       # number of writebacks
+system.cpu.icache.writebacks::total                 5                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          802                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
@@ -613,12 +615,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536
 system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10245.556298                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        10245.556296                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1833992                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15557                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs           117.888539                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9355.655412                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks  9355.655409                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.444539                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.data   215.456347                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.285512                       # Average percentage of cache occupancy
@@ -634,8 +636,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13876
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474762                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         15237898                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        15237898                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       943278                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       943278                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       943278                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       943278                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks            4                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total            4                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        32221                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        32221                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           26                       # number of ReadCleanReq hits
@@ -660,20 +664,22 @@ system.cpu.l2cache.demand_misses::total         15582                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          776                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14806                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15582                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1067673500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1067673500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1067670500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1067670500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     57597000                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadCleanReq_miss_latency::total     57597000                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     21897000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::total     21897000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.inst     57597000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1089570500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1147167500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1089567500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1147164500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.inst     57597000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1089570500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1147167500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       943278                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       943278                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_miss_latency::cpu.data   1089567500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1147164500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       943278                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       943278                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks            4                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total            4                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        46765                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        46765                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          802                       # number of ReadCleanReq accesses(hits+misses)
@@ -698,18 +704,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.016385                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967581                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015582                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016385                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.687844                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.687844                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878                       # average ReadSharedReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.592057                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73621.133359                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.592057                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73621.133359                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -740,18 +746,18 @@ system.cpu.l2cache.demand_mshr_misses::total        15574
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          774                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14800                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    922233500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    922233500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    922230500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    922230500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     49710000                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     49710000                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     18946000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     18946000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     49710000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    941179500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    990889500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    941176500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    990886500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     49710000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    941179500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    990889500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    941176500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    990886500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311002                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311002                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for ReadCleanReq accesses
@@ -764,18 +770,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.687844                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.687844                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.006757                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.406061                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.006757                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.406061                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1897097                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       946118                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -784,8 +790,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        904230                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       943278                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         2674                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       943278                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            4                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         2670                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        46765                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        46765                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          802                       # Transaction distribution
@@ -793,22 +800,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq       903428
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1608                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2846334                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           2847942                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51584                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121182144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          121233472                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          121233728                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1897097                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000167                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.012905                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples       950995                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000175                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.013211                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1896781     99.98%     99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                316      0.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             950829     99.98%     99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                166      0.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1897097                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1891826500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         950995                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1891831500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1203998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
@@ -833,9 +840,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               15574                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21741000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            21739000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           82130750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           82131250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 6db072c1c..a88ddf684 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,116 +1,116 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058181                       # Number of seconds simulated
-sim_ticks                                 58181475500                       # Number of ticks simulated
-final_tick                                58181475500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058178                       # Number of seconds simulated
+sim_ticks                                 58178156500                       # Number of ticks simulated
+final_tick                                58178156500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 122946                       # Simulator instruction rate (inst/s)
-host_op_rate                                   123559                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               78962453                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 448784                       # Number of bytes of host memory used
-host_seconds                                   736.82                       # Real time elapsed on the host
+host_inst_rate                                 123327                       # Simulator instruction rate (inst/s)
+host_op_rate                                   123942                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               79202629                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 528964                       # Number of bytes of host memory used
+host_seconds                                   734.55                       # Real time elapsed on the host
 sim_insts                                    90589799                       # Number of instructions simulated
 sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             44416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             50176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       933312                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1027904                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        44416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           44416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        28672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             28672                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                694                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                784                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        14583                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 16061                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             448                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  448                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               763404                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               862405                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     16041394                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                17667204                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          763404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             763404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            492803                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 492803                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            492803                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              763404                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              862405                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     16041394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18160007                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         16061                       # Number of read requests accepted
-system.physmem.writeReqs                          448                       # Number of write requests accepted
-system.physmem.readBursts                       16061                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        448                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1014144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     13760                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     26688                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1027904                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  28672                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      215                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             44736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             55744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       924288                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1024768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        44736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           44736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        10048                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             10048                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                699                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                871                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        14442                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 16012                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             157                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  157                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               768948                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               958160                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     15887200                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                17614309                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          768948                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             768948                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            172711                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 172711                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            172711                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              768948                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              958160                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     15887200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17787019                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         16013                       # Number of read requests accepted
+system.physmem.writeReqs                          157                       # Number of write requests accepted
+system.physmem.readBursts                       16013                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        157                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1017152                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                      8064                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1024832                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  10048                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1015                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 876                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 960                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1024                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1064                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1138                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1126                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1116                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1048                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs             56                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                1166                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 919                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 952                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1030                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1062                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1117                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1098                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1090                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                947                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                936                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                909                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                891                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                939                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                932                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  39                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                905                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                898                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                901                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                934                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                   7                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                  11                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   6                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                  33                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  78                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                  51                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                  44                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                   8                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                  12                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  30                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                   2                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                   5                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                 13                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  2                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  8                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                 25                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                 64                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                 39                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                 11                       # Per bank write bursts
+system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                  4                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                 16                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                 23                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                  2                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58181318500                       # Total gap between requests
+system.physmem.totGap                     58178148000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   16061                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   16013                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    448                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10962                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2513                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    157                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     10974                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2533                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                       456                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       396                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       299                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       294                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       298                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       275                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       295                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       392                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       294                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       292                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       315                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       291                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       292                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        54                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
@@ -148,26 +148,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
@@ -197,93 +197,90 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1956                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      531.533742                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     297.285521                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     435.040107                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            621     31.75%     31.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          232     11.86%     43.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           86      4.40%     48.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           69      3.53%     51.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           49      2.51%     54.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           52      2.66%     56.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           53      2.71%     59.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           46      2.35%     61.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          748     38.24%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1956                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples            23                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       686.869565                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       31.250235                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     3138.483903                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511              22     95.65%     95.65% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      4.35%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total              23                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples            23                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.130435                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.125203                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.457697                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                 21     91.30%     91.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1      4.35%     95.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  1      4.35%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total              23                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      162337192                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 459449692                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     79230000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10244.68                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1767                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      579.332201                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     345.781267                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     429.630743                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            460     26.03%     26.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          205     11.60%     37.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           93      5.26%     42.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           63      3.57%     46.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           46      2.60%     49.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           57      3.23%     52.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           50      2.83%     55.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           49      2.77%     57.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          744     42.11%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1767                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples             7                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2257.857143                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       93.171857                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     5824.405132                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511               6     85.71%     85.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-15871            1     14.29%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total               7                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples             7                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean               18                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.000000                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  7    100.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total               7                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      173222344                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 471216094                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     79465000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10899.29                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28994.68                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          17.43                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.46                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       17.67                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.49                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29649.29                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          17.48                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.14                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       17.62                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.17                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.14                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.43                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.72                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14167                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       131                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.40                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  29.57                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3524218.21                       # Average gap between requests
-system.physmem.pageHitRate                      87.78                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    7983360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    4356000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  64662000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                  1438560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3799960320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2503358775                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            32711543250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              39093302265                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.947294                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    54407827569                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1942720000                       # Time in different power states
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        19.20                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      14205                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                        38                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.38                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  25.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3597906.49                       # Average gap between requests
+system.physmem.pageHitRate                      88.77                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    7673400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    4186875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  65488800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                   421200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3799451760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2652037290                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            32576451750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              39105711075                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              672.250549                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    54182179525                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1942460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1828586181                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2046707975                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6788880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3704250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  58663800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                  1263600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3799960320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2462347845                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            32747517750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              39080246445                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.722887                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    54468275483                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1942720000                       # Time in different power states
+system.physmem_1.actEnergy                    5654880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3085500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  58141200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                   395280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3799451760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2310125355                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            32876366250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              39053220225                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.348359                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    54689145986                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1942460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1768727017                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1544922014                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                28257355                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23279453                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            837859                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11842476                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11784812                       # Number of BTB hits
+system.cpu.branchPred.lookups                28257532                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23279536                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            837837                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11842353                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11784700                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.513075                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   75760                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             99.513163                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   75800                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 88                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -403,83 +400,83 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        116362952                       # number of cpu cycles simulated
+system.cpu.numCycles                        116356314                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles             748921                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      134986415                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    28257355                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11860572                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     114720736                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1679131                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  953                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          835                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  32301690                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   580                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          116311010                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.165818                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.319039                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles             748715                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      134987552                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    28257532                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11860500                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     114713884                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1679087                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  977                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          833                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  32302381                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   573                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          116303952                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.165899                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.319044                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58740461     50.50%     50.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 13941673     11.99%     62.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9230825      7.94%     70.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34398051     29.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58732386     50.50%     50.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13942591     11.99%     62.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9230864      7.94%     70.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34398111     29.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            116311010                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.242838                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.160046                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8839998                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              64050748                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  33034874                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9558063                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 827327                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4101313                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12342                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              114429656                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               1996969                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 827327                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15281198                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                49893829                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         109582                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  35425015                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14774059                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110898152                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               1415674                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              11131476                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1144261                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1527056                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 488175                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           129955893                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             483270095                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        119473614                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               428                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            116303952                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.242853                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.160122                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8839872                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64043721                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  33034735                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9558318                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 827306                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4101307                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12341                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              114430502                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               1996250                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 827306                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15281424                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                49886472                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         109365                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35424721                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14774664                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110898746                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1414946                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              11132654                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1143672                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1526966                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 487708                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           129956476                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             483272295                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        119473751                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               431                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22642974                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4363                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           4358                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  21507084                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26812785                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5349554                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads            517855                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           254082                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  109689870                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                8247                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 101387714                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1074676                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18657087                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41688114                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             29                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     116311010                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.871695                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.989305                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 22643557                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4364                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           4359                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  21508806                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26812600                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5350060                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            518904                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           253933                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  109691142                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                8248                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 101388881                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1075842                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18658360                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41690770                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             30                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     116303952                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.871758                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.989325                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            54670243     47.00%     47.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            31362294     26.96%     73.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22008143     18.92%     92.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7072499      6.08%     98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1197518      1.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            54663353     47.00%     47.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            31360946     26.96%     73.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22009705     18.92%     92.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7071580      6.08%     98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1198055      1.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                 313      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -487,44 +484,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       116311010                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       116303952                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9794091     48.69%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     50      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9615955     47.81%     96.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                703739      3.50%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9787032     48.68%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     50      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9614737     47.82%     96.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                704136      3.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              71984145     71.00%     71.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10710      0.01%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              71984931     71.00%     71.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10711      0.01%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.01% # Type of FU issued
@@ -546,90 +543,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.01% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              52      0.00%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              54      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            123      0.00%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24343095     24.01%     95.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5049585      4.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24343463     24.01%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5049594      4.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              101387714                       # Type of FU issued
-system.cpu.iq.rate                           0.871306                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    20113848                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.198385                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          340274513                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128355901                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     99625297                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 449                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                614                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          111                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              121501328                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     234                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           290500                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              101388881                       # Type of FU issued
+system.cpu.iq.rate                           0.871366                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    20105968                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.198305                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          340263064                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128358435                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     99626003                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 460                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                626                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          112                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              121494609                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     240                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           289420                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4336874                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1516                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4336689                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1514                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation         1345                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       604710                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores       605216                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7564                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        130574                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         7563                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        130752                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 827327                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8118136                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                684680                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           109710785                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 827306                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8114677                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                684104                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           109712059                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26812785                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5349554                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               4359                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 179049                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                342646                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewDispLoadInsts              26812600                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5350060                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               4360                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 178830                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                342365                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents           1345                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         436655                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       412870                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               849525                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             100126849                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23806470                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1260865                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect         436596                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       412868                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               849464                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             100127809                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23806782                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1261072                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12668                       # number of nop insts executed
-system.cpu.iew.exec_refs                     28724380                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 20624234                       # Number of branches executed
-system.cpu.iew.exec_stores                    4917910                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.860470                       # Inst execution rate
-system.cpu.iew.wb_sent                       99710000                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      99625408                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  59703416                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95544446                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         12669                       # number of nop insts executed
+system.cpu.iew.exec_refs                     28724706                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 20624810                       # Number of branches executed
+system.cpu.iew.exec_stores                    4917924                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.860528                       # Inst execution rate
+system.cpu.iew.wb_sent                       99710755                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      99626115                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  59703966                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95545842                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.856161                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.624876                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.856216                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.624872                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        17385130                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        17384633                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            825621                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    113618734                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.801396                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.737990                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            825600                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    113611791                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.801445                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.737925                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     77195687     67.94%     67.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18614563     16.38%     84.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      7151371      6.29%     90.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3466253      3.05%     93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1641564      1.44%     95.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       544784      0.48%     95.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       704352      0.62%     96.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       179993      0.16%     96.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4120167      3.63%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     77186972     67.94%     67.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18613328     16.38%     84.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      7152554      6.30%     90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3469014      3.05%     93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1644498      1.45%     95.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       541954      0.48%     95.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       704210      0.62%     96.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       178949      0.16%     96.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4120312      3.63%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    113618734                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    113611791                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
 system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -675,78 +672,78 @@ system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               4120167                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    217931602                       # The number of ROB reads
-system.cpu.rob.rob_writes                   219570402                       # The number of ROB writes
-system.cpu.timesIdled                             589                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           51942                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               4120312                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    217924017                       # The number of ROB reads
+system.cpu.rob.rob_writes                   219569293                       # The number of ROB writes
+system.cpu.timesIdled                             582                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           52362                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
 system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.284504                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.284504                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.778511                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.778511                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                108111563                       # number of integer regfile reads
-system.cpu.int_regfile_writes                58701013                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        59                       # number of floating regfile reads
+system.cpu.cpi                               1.284431                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.284431                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.778555                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.778555                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                108111974                       # number of integer regfile reads
+system.cpu.int_regfile_writes                58701043                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       92                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 369063684                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 58693489                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                28414952                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                 369066936                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 58693781                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                28415091                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           5470194                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.787648                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18251935                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           5470706                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              3.336303                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          35373500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.787648                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999585                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999585                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           5470182                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.784909                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18253071                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           5470694                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              3.336518                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          35707500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.784909                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999580                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999580                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          343                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          355                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          61908668                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         61908668                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13889868                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13889868                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4353786                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4353786                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          61911082                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         61911082                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13891036                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13891036                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4353748                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4353748                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      18243654                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18243654                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18244176                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18244176                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9585829                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9585829                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       381195                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       381195                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      18244784                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18244784                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18245306                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18245306                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9585874                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9585874                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       381233                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       381233                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           15                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           15                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      9967024                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9967024                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9967031                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9967031                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  88721011000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  88721011000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4006916840                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4006916840                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      9967107                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9967107                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9967114                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9967114                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  88735069500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  88735069500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4002231848                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4002231848                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       296500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       296500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  92727927840                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  92727927840                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  92727927840                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  92727927840                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23475697                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23475697                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  92737301348                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  92737301348                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  92737301348                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  92737301348                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23476910                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23476910                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
@@ -755,298 +752,310 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28210678                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28210678                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28211207                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28211207                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408330                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.408330                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080506                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080506                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     28211891                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28211891                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28212420                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28212420                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408311                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.408311                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080514                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080514                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003859                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003859                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.353307                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.353307                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.353300                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.353300                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9255.434350                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9255.434350                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.462218                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.462218                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.353295                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.353295                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.353288                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.353288                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9256.857486                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9256.857486                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10498.125419                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10498.125419                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9303.471913                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9303.471913                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9303.465379                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9303.465379                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       329844                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       111014                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            121439                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           12836                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.716129                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     8.648644                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9304.334884                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9304.334884                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9304.328349                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9304.328349                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       329976                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       109342                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            121408                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           12843                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717910                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     8.513743                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      5433212                       # number of writebacks
-system.cpu.dcache.writebacks::total           5433212                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4337614                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4337614                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158708                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       158708                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      5470182                       # number of writebacks
+system.cpu.dcache.writebacks::total           5470182                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4337666                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4337666                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158748                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       158748                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           15                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           15                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4496322                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4496322                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4496322                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4496322                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248215                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5248215                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222487                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       222487                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4496414                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4496414                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4496414                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4496414                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248208                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5248208                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222485                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       222485                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      5470702                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      5470702                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      5470706                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      5470706                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43247632500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43247632500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2285123725                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2285123725                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      5470693                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      5470693                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      5470697                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      5470697                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43256008000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43256008000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2285824228                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2285824228                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       214500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       214500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45532756225                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  45532756225                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45532970725                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  45532970725                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223559                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223559                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45541832228                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  45541832228                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45542046728                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  45542046728                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223548                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223548                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046988                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046988                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193923                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.193923                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193920                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.193920                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8240.446037                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8240.446037                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.819082                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.819082                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193914                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.193914                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193911                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.193911                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8242.052906                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8242.052906                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.059950                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.059950                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53625                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53625                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8323.018915                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8323.018915                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8323.052038                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8323.052038                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8324.691630                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8324.691630                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8324.724752                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8324.724752                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               451                       # number of replacements
-system.cpu.icache.tags.tagsinuse           428.507470                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            32300517                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               910                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          35495.073626                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               452                       # number of replacements
+system.cpu.icache.tags.tagsinuse           428.759370                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            32301211                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               911                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          35456.872667                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   428.507470                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.836929                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.836929                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   428.759370                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.837421                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.837421                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          459                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          331                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.896484                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          64604262                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         64604262                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     32300517                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        32300517                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      32300517                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         32300517                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     32300517                       # number of overall hits
-system.cpu.icache.overall_hits::total        32300517                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1159                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1159                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1159                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1159                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1159                       # number of overall misses
-system.cpu.icache.overall_misses::total          1159                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62258984                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62258984                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62258984                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62258984                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62258984                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62258984                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     32301676                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     32301676                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     32301676                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     32301676                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     32301676                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     32301676                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          64605645                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         64605645                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     32301211                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        32301211                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      32301211                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         32301211                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     32301211                       # number of overall hits
+system.cpu.icache.overall_hits::total        32301211                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1156                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1156                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1156                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1156                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1156                       # number of overall misses
+system.cpu.icache.overall_misses::total          1156                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     61324481                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     61324481                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     61324481                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     61324481                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     61324481                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     61324481                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     32302367                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     32302367                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     32302367                       # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total     32302367                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53717.846419                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53717.846419                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53717.846419                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53717.846419                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53717.846419                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53717.846419                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        18998                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          136                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               221                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53048.858997                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53048.858997                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53048.858997                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53048.858997                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53048.858997                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53048.858997                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        18977                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          108                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               225                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    85.963801                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    27.200000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    84.342222                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    21.600000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          249                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          249                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          249                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          249                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          249                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          249                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          910                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          910                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          910                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50293988                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     50293988                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50293988                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     50293988                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50293988                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     50293988                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks          452                       # number of writebacks
+system.cpu.icache.writebacks::total               452                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          244                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          244                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          244                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          244                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          244                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          244                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          912                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          912                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          912                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          912                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          912                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          912                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50084985                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     50084985                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50084985                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     50084985                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50084985                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     50084985                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55268.118681                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55268.118681                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55268.118681                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 55268.118681                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55268.118681                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 55268.118681                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54917.746711                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54917.746711                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54917.746711                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54917.746711                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54917.746711                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54917.746711                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      4980719                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      5295706                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       273829                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      4981768                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      5296904                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit       273976                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage     14074518                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements              620                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        12071.188165                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           10691146                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            16060                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           665.700249                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage     14074864                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements              212                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        11227.859430                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5316692                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            14883                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           357.232547                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 11063.420038                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   575.029353                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   219.514162                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   213.224612                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.675258                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035097                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.013398                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.013014                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.736767                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          266                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15174                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           22                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3            9                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.926147                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        175272147                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       175272147                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      5433212                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      5433212                       # number of Writeback hits
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data       226519                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       226519                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000096                       # miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.000185                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.data     0.000185                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.000312                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83115.913556                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83115.913556                       # average ReadExReq miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68976.978417                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60588.118812                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60588.118812                       # average ReadSharedReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71896.449704                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70709.186659                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71896.449704                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70709.186659                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.768640                       # miss rate for ReadCleanReq accesses
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22666.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22666.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82046.719682                       # average ReadExReq miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68114.122682                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68728.241563                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68728.241563                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::total 72275.891341                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75012.664165                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72275.891341                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1055,147 +1064,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          448                       # number of writebacks
-system.cpu.l2cache.writebacks::total              448                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          166                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total          166                       # number of ReadExReq MSHR hits
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 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           64                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           64                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           32                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           32                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          230                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          231                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          230                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          231                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           11                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total           11                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        20740                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        20740                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          343                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          343                       # number of ReadExReq MSHR misses
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-system.cpu.l2cache.demand_mshr_misses::cpu.inst          694                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          784                       # number of demand (read+write) MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::cpu.inst          694                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          784                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        20740                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        22218                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    848794725                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    848794725                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32842000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32842000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43715500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43715500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     24991500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     24991500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43715500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     57833500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    101549000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43715500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     57833500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    848794725                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    950343725                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.overall_mshr_hits::cpu.data          193                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          194                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       316256                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       316256                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            3                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            3                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          342                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          342                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          700                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          700                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          531                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          531                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          700                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          873                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         1573                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          700                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          873                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       316256                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       317829                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    852114791                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    852114791                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        50000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        50000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32658500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32658500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43494500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43494500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     34061500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     34061500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43494500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     66720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    110214500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43494500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     66720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    852114791                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    962329291                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001514                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001514                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.762637                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.762637                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000084                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.762637                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000143                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.000270                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.762637                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000143                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001510                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001510                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.767544                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.767544                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000101                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000101                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.767544                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000160                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.000287                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.767544                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000160                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.004061                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 40925.493009                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95749.271137                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95749.271137                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62990.634006                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62990.634006                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56670.068027                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56670.068027                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62990.634006                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.219388                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68707.036536                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62990.634006                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.219388                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42773.594608                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.058087                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2694.383003                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  2694.383003                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16666.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16666.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95492.690058                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95492.690058                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst        62135                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total        62135                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64145.951036                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64145.951036                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        62135                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76426.116838                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70066.433566                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        62135                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76426.116838                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2694.383003                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total  3027.820907                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     10942261                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      5470659                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2913                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         6201                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         6201                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       5245097                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      5433660                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        34692                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        22620                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests     10942243                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      5470651                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2916                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       303048                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302740                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          308                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       5245086                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      5453690                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        14185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         1285                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       318131                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFResp            5                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq            3                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            3                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       226519                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       226519                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          910                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244187                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2259                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16408705                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16410964                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    697850752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          697908992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       23240                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     10965501                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001098                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.033119                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          912                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244175                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2263                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16408677                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          16410940                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        86464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700030528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          700116992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      319578                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5791182                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.052888                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.224048                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           10953460     99.89%     99.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              12041      0.11%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            5485204     94.72%     94.72% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             305670      5.28%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                308      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       10965501                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10904342500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization         18.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1367495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        5791182                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10941755515                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization         18.8                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy         7525                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1367997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    8206062992                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    8206046991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              15718                       # Transaction distribution
-system.membus.trans_dist::Writeback               448                       # Transaction distribution
-system.membus.trans_dist::CleanEvict              139                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               343                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              343                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         15718                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32709                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  32709                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1056576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1056576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              15672                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          157                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               51                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                5                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               5                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               340                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              340                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         15673                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32243                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  32243                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1034816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1034816                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             16648                       # Request fanout histogram
+system.membus.snoop_fanout::samples             16226                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   16648    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   16226    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               16648                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            28374711                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               16226                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            26763807                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           84025804                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           83802056                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 8cbe9f760..5dc111e3a 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.361489                       # Number of seconds simulated
-sim_ticks                                361488536500                       # Number of ticks simulated
-final_tick                               361488536500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.361598                       # Number of seconds simulated
+sim_ticks                                361597758500                       # Number of ticks simulated
+final_tick                               361597758500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1117046                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1117092                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1656101101                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 428664                       # Number of bytes of host memory used
-host_seconds                                   218.28                       # Real time elapsed on the host
+host_inst_rate                                1135132                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1135179                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1683423955                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 429008                       # Number of bytes of host memory used
+host_seconds                                   214.80                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total           56256                       # Nu
 system.physmem.num_reads::cpu.inst                879                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14724                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15603                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               155623                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2606821                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2762444                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          155623                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             155623                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              155623                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2606821                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2762444                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               155576                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2606034                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2761610                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          155576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             155576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              155576                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2606034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2761610                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        722977073                       # number of cpu cycles simulated
+system.cpu.numCycles                        723195517                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   243825150                       # Number of instructions committed
@@ -50,7 +50,7 @@ system.cpu.num_mem_refs                     105711441                       # nu
 system.cpu.num_load_insts                    82803521                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               722977072.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               723195516.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29302884                       # Number of branches fetched
@@ -90,18 +90,18 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  244431613                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            935475                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3562.469029                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3562.412338                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           104186699                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            939571                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            110.887521                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle      134366269500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3562.469029                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.869743                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.869743                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle      134409733500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3562.412338                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.869730                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.869730                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1418                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2513                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1416                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2526                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           46                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         211192111                       # Number of tag accesses
@@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data       939567                       # n
 system.cpu.dcache.demand_misses::total         939567                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       939567                       # number of overall misses
 system.cpu.dcache.overall_misses::total        939567                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11613736000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11613736000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1219002000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1219002000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data        94000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total        94000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  12832738000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  12832738000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  12832738000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  12832738000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11614835000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11614835000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1320964000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1320964000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       101000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       101000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  12935799000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  12935799000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  12935799000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  12935799000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     82220433                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     82220433                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     22901951                       # number of WriteReq accesses(hits+misses)
@@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_miss_rate::total     0.008938                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.008938                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.008938                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        23500                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total        23500                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13658.140399                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13658.140399                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        25250                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total        25250                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13767.830288                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13767.830288                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       939567
 system.cpu.dcache.demand_mshr_misses::total       939567                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       939567                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       939567                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10720879000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10720879000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1172292000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1172292000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        90000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total        90000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11893171000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11893171000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11893171000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11893171000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10721978000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10721978000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1274254000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1274254000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        97000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        97000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11996232000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11996232000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11996232000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11996232000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002040                       # mshr miss rate for WriteReq accesses
@@ -206,26 +206,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_mshr_miss_rate::total     0.008938                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.008938                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        22500                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        22500                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        24250                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        24250                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                25                       # number of replacements
-system.cpu.icache.tags.tagsinuse           725.412972                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           725.404879                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           244420617                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               882                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          277120.880952                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   725.412972                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.354206                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.354206                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   725.404879                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.354202                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.354202                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          857                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
@@ -246,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst          882                       # n
 system.cpu.icache.demand_misses::total            882                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          882                       # number of overall misses
 system.cpu.icache.overall_misses::total           882                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     48389500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     48389500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     48389500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     48389500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     48389500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     48389500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     54543500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     54543500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     54543500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     54543500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     54543500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     54543500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    244421499                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    244421499                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    244421499                       # number of demand (read+write) accesses
@@ -264,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000004
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54863.378685                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54863.378685                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61840.702948                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61840.702948                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -278,44 +278,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks           25                       # number of writebacks
+system.cpu.icache.writebacks::total                25                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          882                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          882                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          882                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          882                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          882                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          882                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     47507500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     47507500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     47507500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     47507500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     47507500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     47507500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     53661500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     53661500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     53661500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     53661500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     53661500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     53661500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         9730.625106                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         9729.320449                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1813523                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15586                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs           116.355896                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8847.670068                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   738.635584                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   144.319455                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.270009                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  8846.376929                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   738.627938                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   144.315582                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.269970                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.022541                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.004404                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.296955                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.296915                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        15586                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
@@ -325,8 +327,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13986
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.475647                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         15069916                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        15069916                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       935266                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       935266                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       935266                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       935266                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks           25                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total           25                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        32147                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        32147                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            3                       # number of ReadCleanReq hits
@@ -351,20 +355,22 @@ system.cpu.l2cache.demand_misses::total         15603                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          879                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14724                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15603                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    764767500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    764767500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     46150500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     46150500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      8242500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total      8242500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     46150500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    773010000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    819160500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     46150500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    773010000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    819160500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       935266                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       935266                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    866736500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    866736500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     52304000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     52304000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data      9341500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total      9341500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     52304000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    876078000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    928382000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     52304000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    876078000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    928382000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       935266                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       935266                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks           25                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total           25                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        46714                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        46714                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          882                       # number of ReadCleanReq accesses(hits+misses)
@@ -389,18 +395,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.016591                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996599                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015671                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016591                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        59500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        59500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        59500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        59500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        59500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        59500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -421,18 +427,18 @@ system.cpu.l2cache.demand_mshr_misses::total        15603
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          879                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14724                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    619097500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    619097500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     37360500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     37360500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      6672500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      6672500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     37360500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    625770000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    663130500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     37360500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    625770000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    663130500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    721066500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    721066500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43514000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43514000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      7771500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      7771500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43514000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    728838000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    772352000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43514000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    728838000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    772352000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311834                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311834                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for ReadCleanReq accesses
@@ -445,18 +451,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.016591
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015671                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016591                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        49500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        49500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1875953                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       935500                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -465,8 +471,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        893739                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       935266                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict          233                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       935266                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           25                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          208                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        46714                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        46714                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          882                       # Transaction distribution
@@ -474,22 +481,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq       892857
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1789                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2814616                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           2816405                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58048                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    119989568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          120046016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          120047616                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1875953                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples       940453                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000001                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.001033                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.001031                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1875951    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  2      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             940452    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1875953                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1873242500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         940453                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1873267500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1323000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
@@ -514,9 +521,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               15603                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            15606000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            15606500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           78018000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           78015000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 9774ca6b0..92e3ee5b5 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.061602                       # Number of seconds simulated
-sim_ticks                                 61602395500                       # Number of ticks simulated
-final_tick                                61602395500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                 61602281500                       # Number of ticks simulated
+final_tick                                61602281500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109389                       # Simulator instruction rate (inst/s)
-host_op_rate                                   192617                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               42652748                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 458300                       # Number of bytes of host memory used
-host_seconds                                  1444.28                       # Real time elapsed on the host
+host_inst_rate                                 108860                       # Simulator instruction rate (inst/s)
+host_op_rate                                   191684                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42446103                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 458164                       # Number of bytes of host memory used
+host_seconds                                  1451.31                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -18,41 +18,41 @@ system.physmem.bytes_read::cpu.data           1883136                       # Nu
 system.physmem.bytes_read::total              1947008                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        63872                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           63872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        11776                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             11776                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks        12160                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             12160                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                998                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              29424                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 30422                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             184                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  184                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1036843                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             30569201                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                31606044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1036843                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1036843                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            191161                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 191161                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            191161                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1036843                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            30569201                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               31797205                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::writebacks             190                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  190                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1036845                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             30569257                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                31606102                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1036845                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1036845                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            197395                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 197395                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            197395                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1036845                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            30569257                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               31803497                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                         30422                       # Number of read requests accepted
-system.physmem.writeReqs                          184                       # Number of write requests accepted
+system.physmem.writeReqs                          190                       # Number of write requests accepted
 system.physmem.readBursts                       30422                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        184                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1941952                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5056                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     10304                       # Total number of bytes written to DRAM
+system.physmem.writeBursts                        190                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1941504                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      5504                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     10240                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                   1947008                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  11776                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       79                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytesWrittenSys                  12160                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       86                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       1                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs             24                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                1928                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2065                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2059                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                2023                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                1928                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                2026                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                2025                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1901                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                1952                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1864                       # Per bank write bursts
@@ -65,12 +65,12 @@ system.physmem.perBankRdBursts::13               1800                       # Pe
 system.physmem.perBankRdBursts::14               1818                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               1778                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                  82                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                  78                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   7                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                  28                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                   6                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                   7                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  13                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  16                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   5                       # Per bank write bursts
@@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61602210500                       # Total gap between requests
+system.physmem.totGap                     61602096500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -96,9 +96,9 @@ system.physmem.writePktSize::2                      0                       # Wr
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    184                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     29859                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       382                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    190                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     29853                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       381                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
@@ -151,13 +151,13 @@ system.physmem.wrQLenPdf::18                       10                       # Wh
 system.physmem.wrQLenPdf::19                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       10                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
@@ -193,186 +193,184 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         2722                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      716.414401                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     516.531797                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     387.717070                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            355     13.04%     13.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          240      8.82%     21.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          126      4.63%     26.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          120      4.41%     30.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           92      3.38%     34.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          131      4.81%     39.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          110      4.04%     43.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           67      2.46%     45.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1481     54.41%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           2722                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples         2721                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      716.489526                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     515.486965                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     387.954881                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            364     13.38%     13.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          231      8.49%     21.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          123      4.52%     26.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          120      4.41%     30.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           92      3.38%     34.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          132      4.85%     39.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          112      4.12%     43.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           67      2.46%     45.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1480     54.39%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2721                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples             9                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      3364.888889                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       25.331779                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    10055.293027                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      3363.777778                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    10055.709980                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-1023              8     88.89%     88.89% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::29696-30719            1     11.11%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total               9                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples             9                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.888889                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.873018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.781736                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.777778                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.765969                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.666667                       # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::16                  1     11.11%     11.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  7     77.78%     88.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1     11.11%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  8     88.89%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total               9                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      132940250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 701871500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    151715000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4381.25                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                      133021500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 701821500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    151680000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4384.94                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23131.25                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  23134.94                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          31.52                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.17                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       31.61                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.19                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.20                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.25                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.25                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        15.66                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      27667                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       105                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        15.67                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27659                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       106                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   91.18                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  57.38                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2012749.48                       # Average gap between requests
-system.physmem.pageHitRate                      90.98                       # Row buffer hit rate, read and write combined
+system.physmem.writeRowHitRate                  56.08                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2012351.25                       # Average gap between requests
+system.physmem.pageHitRate                      90.96                       # Row buffer hit rate, read and write combined
 system.physmem_0.actEnergy                   10924200                       # Energy for activate commands per rank (pJ)
 system.physmem_0.preEnergy                    5960625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 122031000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                   991440                       # Energy for write commands per rank (pJ)
+system.physmem_0.readEnergy                 121984200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                   984960                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             4023218160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2832436305                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34473777000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41469338730                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              673.233237                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57335755750                       # Time in different power states
+system.physmem_0.actBackEnergy             2835924705                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34470717000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41469713850                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              673.239327                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57330547250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      2056860000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      2206091250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2211196750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                    9608760                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                    5242875                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 114207600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                    51840                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             4023218160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3020027580                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34309215000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41481571815                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              673.431985                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57061184750                       # Time in different power states
+system.physmem_1.actBackEnergy             3020047245                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34309197750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41481574230                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              673.432024                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57061053250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      2056860000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      2480864750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2480893250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                36908902                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          36908902                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                36908905                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          36908905                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            741640                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             21094595                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21013332                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             21094596                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21013333                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             99.614769                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5443329                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS                 5443330                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               4414                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        123204792                       # number of cpu cycles simulated
+system.cpu.numCycles                        123204564                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27815548                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      199030226                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    36908902                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           26456661                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      94542157                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1553197                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  368                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          5286                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           27815555                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      199030250                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    36908905                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           26456663                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      94541896                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1553195                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  366                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5275                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines                  27443892                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                182896                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          123139971                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.847273                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.366420                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  27443897                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                182895                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          123139703                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.847279                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.366421                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 62945586     51.12%     51.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3649644      2.96%     54.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3480667      2.83%     56.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5913875      4.80%     61.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7544210      6.13%     67.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5413973      4.40%     72.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3251113      2.64%     74.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2020097      1.64%     76.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 28920806     23.49%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 62945303     51.12%     51.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3649645      2.96%     54.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3480674      2.83%     56.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5913881      4.80%     61.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7544216      6.13%     67.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5413971      4.40%     72.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3251108      2.64%     74.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2020095      1.64%     76.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 28920810     23.49%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            123139971                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            123139703                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.299574                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.615442                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 12941533                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63708539                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  35887594                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9825707                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 776598                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              331225454                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 776598                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18253440                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8529193                       # Number of cycles rename is blocking
+system.cpu.fetch.rate                        1.615445                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 12941515                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63708297                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  35887575                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9825719                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 776597                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              331225446                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 776597                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18253426                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8529207                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles          16791                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  40202739                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              55361210                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              325142958                       # Number of instructions processed by rename
+system.cpu.rename.RunCycles                  40202725                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              55360957                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              325142954                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                  1786                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 778279                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               48626800                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4947589                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           327068190                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             863737834                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        532004035                       # Number of integer rename lookups
+system.cpu.rename.IQFullEvents                 778303                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               48626694                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4947433                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           327068188                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             863737810                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        532004029                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               425                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 47855443                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 47855441                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                492                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            490                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  66412234                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                  66412323                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads            105336194                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            36169393                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          49402360                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8500454                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  322302016                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.memDep0.insertedStores            36169392                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          49402348                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8500449                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  322302018                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                1714                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 306103022                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                 306103027                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued             45906                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        44111266                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     63884636                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined        44111268                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     63884608                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved           1269                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     123139971                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.485814                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.139103                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     123139703                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.485819                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.139102                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            30260078     24.57%     24.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19566758     15.89%     40.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            16687037     13.55%     54.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17331221     14.07%     68.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            14759373     11.99%     80.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12567435     10.21%     90.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             6273256      5.09%     95.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3904180      3.17%     98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1790633      1.45%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            30259811     24.57%     24.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19566759     15.89%     40.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            16687041     13.55%     54.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17331203     14.07%     68.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            14759381     11.99%     80.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12567446     10.21%     90.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             6273248      5.09%     95.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3904177      3.17%     98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1790637      1.45%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       123139971                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       123139703                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  338797      8.53%      8.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  338800      8.53%      8.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      8.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.53% # attempts to use FU when none available
@@ -401,12 +399,12 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.53% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                3433516     86.49%     95.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                197609      4.98%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3433517     86.49%     95.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                197610      4.98%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33341      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             174121945     56.88%     56.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             174121950     56.88%     56.89% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                11182      0.00%     56.90% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                   343      0.00%     56.90% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     56.90% # Type of FU issued
@@ -439,80 +437,80 @@ system.cpu.iq.FU_type_0::MemRead             98066351     32.04%     88.94% # Ty
 system.cpu.iq.FU_type_0::MemWrite            33869829     11.06%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              306103022                       # Type of FU issued
-system.cpu.iq.rate                           2.484506                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3969922                       # FU busy when requested
+system.cpu.iq.FU_type_0::total              306103027                       # Type of FU issued
+system.cpu.iq.rate                           2.484510                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3969927                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.012969                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          739361486                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         366454631                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    304282654                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_reads          739361233                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         366454635                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    304282659                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 357                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                618                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses          133                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              310039423                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              310039433                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     180                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         58196276                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads         58196288                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread0.squashedLoads     14556809                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses        63678                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation        41328                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      4729641                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores      4729640                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads         3641                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        141546                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked        141544                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 776598                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5329301                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3100559                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           322303730                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 776597                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5329160                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3100599                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           322303732                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts             76830                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts             105336194                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             36169393                       # Number of dispatched store instructions
+system.cpu.iew.iewDispStoreInsts             36169392                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                475                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                   2588                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3102582                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3102623                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          41328                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect         371679                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       414777                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               786456                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             305156723                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              97750585                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            946299                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect       414776                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               786455                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             305156727                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              97750586                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            946300                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    131430383                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31401847                       # Number of branches executed
+system.cpu.iew.exec_refs                    131430384                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31401849                       # Number of branches executed
 system.cpu.iew.exec_stores                   33679798                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.476825                       # Inst execution rate
-system.cpu.iew.wb_sent                      304565840                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     304282787                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 230213925                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 333861001                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     2.476830                       # Inst execution rate
+system.cpu.iew.wb_sent                      304565842                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     304282792                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 230213909                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 333860979                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.469732                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       2.469736                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.689550                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        44209684                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        44209690                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            742009                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    117119203                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.375293                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.092758                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            742008                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    117118936                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.375299                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.092759                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     52926112     45.19%     45.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     15815584     13.50%     58.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     10978620      9.37%     68.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8749335      7.47%     75.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1860124      1.59%     77.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1720771      1.47%     78.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       865932      0.74%     79.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       690108      0.59%     79.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     23512617     20.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     52925822     45.19%     45.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     15815600     13.50%     58.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     10978628      9.37%     68.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8749337      7.47%     75.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1860126      1.59%     77.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1720772      1.47%     78.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       865935      0.74%     79.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       690105      0.59%     79.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     23512611     20.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    117119203                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    117118936                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -558,73 +556,73 @@ system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              23512617                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    416008734                       # The number of ROB reads
-system.cpu.rob.rob_writes                   650833809                       # The number of ROB writes
+system.cpu.commit.bw_lim_events              23512611                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    416008479                       # The number of ROB reads
+system.cpu.rob.rob_writes                   650833820                       # The number of ROB writes
 system.cpu.timesIdled                             568                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           64821                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           64861                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.779834                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.779834                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.282325                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.282325                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                491477122                       # number of integer regfile reads
-system.cpu.int_regfile_writes               239432260                       # number of integer regfile writes
+system.cpu.cpi                               0.779832                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.779832                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.282327                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.282327                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                491477132                       # number of integer regfile reads
+system.cpu.int_regfile_writes               239432261                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       110                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                       84                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107533023                       # number of cc regfile reads
+system.cpu.cc_regfile_reads                 107533030                       # number of cc regfile reads
 system.cpu.cc_regfile_writes                 64416979                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               195275944                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               195275946                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements           2072313                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.012942                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            68071048                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4068.012890                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            68071038                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           2076409                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             32.783063                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             32.783059                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle       19455459500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4068.012942                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.012890                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993167                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993167                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          630                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3339                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          633                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3336                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         143788667                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        143788667                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     36725223                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        36725223                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31345824                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31345824                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68071047                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68071047                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68071047                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68071047                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         143788645                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        143788645                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     36725212                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        36725212                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31345825                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31345825                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      68071037                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         68071037                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     68071037                       # number of overall hits
+system.cpu.dcache.overall_hits::total        68071037                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      2691154                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       2691154                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        93928                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        93928                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2785082                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2785082                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2785082                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2785082                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32304507500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32304507500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2956593494                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2956593494                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35261100994                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35261100994                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35261100994                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35261100994                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     39416377                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     39416377                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data        93927                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        93927                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2785081                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2785081                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2785081                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2785081                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32304267000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32304267000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2956614994                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2956614994                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35260881994                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35260881994                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35260881994                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35260881994                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     39416366                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     39416366                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     70856129                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     70856129                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     70856129                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     70856129                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     70856118                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     70856118                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     70856118                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     70856118                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.068275                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.068275                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002988                       # miss rate for WriteReq accesses
@@ -633,19 +631,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.039306
 system.cpu.dcache.demand_miss_rate::total     0.039306                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.039306                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.039306                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12660.704781                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12660.704781                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       221514                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.871573                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.871573                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.630694                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12660.630694                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.630694                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12660.630694                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       221476                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             43222                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             43220                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.125029                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.124387                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -653,12 +651,12 @@ system.cpu.dcache.writebacks::writebacks      2066601                       # nu
 system.cpu.dcache.writebacks::total           2066601                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       696788                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total       696788                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11884                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        11884                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       708672                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       708672                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       708672                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       708672                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11883                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        11883                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       708671                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       708671                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       708671                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       708671                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994366                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      1994366                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82044                       # number of WriteReq MSHR misses
@@ -667,14 +665,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      2076410
 system.cpu.dcache.demand_mshr_misses::total      2076410                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      2076410                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      2076410                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24196144500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24196144500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2799371995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2799371995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26995516495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26995516495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26995516495                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26995516495                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24195993500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24195993500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2799396995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2799396995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26995390495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26995390495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26995390495                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26995390495                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050597                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050597                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002610                       # mshr miss rate for WriteReq accesses
@@ -683,68 +681,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029305
 system.cpu.dcache.demand_mshr_miss_rate::total     0.029305                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029305                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.029305                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.173082                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.173082                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.992335                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.992335                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.992335                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.992335                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                53                       # number of replacements
-system.cpu.icache.tags.tagsinuse           825.039934                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27442569                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           825.039758                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27442574                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              1013                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          27090.393880                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          27090.398815                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   825.039934                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.402852                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.402852                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   825.039758                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.402851                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.402851                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          960                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          870                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.468750                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          54888798                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         54888798                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27442569                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27442569                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27442569                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27442569                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27442569                       # number of overall hits
-system.cpu.icache.overall_hits::total        27442569                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          54888808                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         54888808                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27442574                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27442574                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27442574                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27442574                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27442574                       # number of overall hits
+system.cpu.icache.overall_hits::total        27442574                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         1323                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          1323                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         1323                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           1323                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         1323                       # number of overall misses
 system.cpu.icache.overall_misses::total          1323                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     97144000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     97144000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     97144000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     97144000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     97144000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     97144000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27443892                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27443892                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27443892                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27443892                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27443892                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27443892                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     97204000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     97204000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     97204000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     97204000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     97204000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     97204000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27443897                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27443897                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27443897                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27443897                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27443897                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27443897                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000048                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000048                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000048                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000048                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000048                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73427.059713                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73427.059713                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73472.411187                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73472.411187                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73472.411187                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73472.411187                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73472.411187                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73472.411187                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -753,6 +751,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks           53                       # number of writebacks
+system.cpu.icache.writebacks::total                53                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          309                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total          309                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst          309                       # number of demand (read+write) MSHR hits
@@ -765,49 +765,51 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         1014
 system.cpu.icache.demand_mshr_misses::total         1014                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         1014                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         1014                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     77391000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     77391000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     77391000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     77391000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     77391000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     77391000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     77418000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     77418000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     77418000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     77418000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     77418000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     77418000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000037                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements              487                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20712.335726                       # Cycle average of tags in use
+system.cpu.l2cache.tags.replacements              493                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        20712.318868                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4035103                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30405                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           132.711824                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30411                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           132.685640                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.841852                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   245.917522                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.603991                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.841856                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   245.917380                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.603990                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020595                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.007505                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.632090                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29918                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          780                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1385                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27629                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          782                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1386                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27623                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913025                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         33310467                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33310467                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2066601                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2066601                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         33310473                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33310473                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2066601                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2066601                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks           53                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total           53                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        53071                       # number of ReadExReq hits
@@ -834,20 +836,22 @@ system.cpu.l2cache.demand_misses::total         30422                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          998                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        29424                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        30422                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2118128500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   2118128500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75694000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     75694000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     32848500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     32848500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     75694000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   2150977000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   2226671000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     75694000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   2150977000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   2226671000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2066601                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2066601                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2118138000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2118138000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75717000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     75717000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     32704000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     32704000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     75717000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   2150842000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   2226559000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     75717000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   2150842000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2226559000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2066601                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2066601                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks           53                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total           53                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        82069                       # number of ReadExReq accesses(hits+misses)
@@ -874,18 +878,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.014644                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.984221                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.014171                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.014644                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76769.953052                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76769.953052                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.219141                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73189.106568                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.219141                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73189.106568                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -894,10 +898,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          184                       # number of writebacks
-system.cpu.l2cache.writebacks::total              184                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            6                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            6                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.writebacks::writebacks          190                       # number of writebacks
+system.cpu.l2cache.writebacks::total              190                       # number of writebacks
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28998                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        28998                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          998                       # number of ReadCleanReq MSHR misses
@@ -910,20 +912,18 @@ system.cpu.l2cache.demand_mshr_misses::total        30422
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          998                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        29424                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        30422                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1828148500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1828148500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65714000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65714000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     28588500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     28588500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65714000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1856737000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1922451000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65714000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1856737000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1922451000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1828158000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1828158000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65737000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65737000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     28444000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     28444000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65737000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1856602000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1922339000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65737000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1856602000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1922339000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353337                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353337                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.984221                       # mshr miss rate for ReadCleanReq accesses
@@ -936,18 +936,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.014644
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.984221                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014171                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.014644                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66769.953052                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66769.953052                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.219141                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.106568                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.219141                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.106568                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      4149790                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2072370                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -956,8 +956,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops          279                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          279                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp       1995354                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2066785                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         6027                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2066791                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           53                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         5974                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        82069                       # Transaction distribution
@@ -967,39 +968,39 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq      1994340
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2081                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6225092                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           6227173                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        64896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68288                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265152640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          265217536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         487                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4150277                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000088                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.009390                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size::total          265220928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         493                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2077917                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000156                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.012505                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            4149911     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                366      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2077592     99.98%     99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                325      0.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4150277                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4141496000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2077917                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4141549000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          6.7                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1521000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    3114614000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          5.1                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp               1424                       # Transaction distribution
-system.membus.trans_dist::Writeback               184                       # Transaction distribution
-system.membus.trans_dist::CleanEvict               30                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          190                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               24                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             28998                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            28998                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq          1424                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61058                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61058                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  61058                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1958784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1958784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1958784                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1959168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1959168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1959168                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
 system.membus.snoop_fanout::samples             30636                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
@@ -1011,9 +1012,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               30636                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            42746000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            42770500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          160323750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          160321750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index d05ee6d96..ff948a783 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.365989                       # Number of seconds simulated
-sim_ticks                                365988859500                       # Number of ticks simulated
-final_tick                               365988859500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.366199                       # Number of seconds simulated
+sim_ticks                                366199170500                       # Number of ticks simulated
+final_tick                               366199170500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 563395                       # Simulator instruction rate (inst/s)
-host_op_rate                                   992048                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1305133674                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 455224                       # Number of bytes of host memory used
-host_seconds                                   280.42                       # Real time elapsed on the host
+host_inst_rate                                 639917                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1126791                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1483253517                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 455604                       # Number of bytes of host memory used
+host_seconds                                   246.89                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -25,21 +25,21 @@ system.physmem.num_reads::cpu.data              29241                       # Nu
 system.physmem.num_reads::total                 30044                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks             102                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  102                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               140420                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              5113336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 5253756                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          140420                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             140420                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks             17837                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                  17837                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks             17837                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              140420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5113336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5271592                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               140339                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              5110399                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 5250738                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          140339                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             140339                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks             17826                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                  17826                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks             17826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              140339                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5110399                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5268565                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        731977719                       # number of cpu cycles simulated
+system.cpu.numCycles                        732398341                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   157988548                       # Number of instructions committed
@@ -60,7 +60,7 @@ system.cpu.num_mem_refs                     122219137                       # nu
 system.cpu.num_load_insts                    90779385                       # Number of load instructions
 system.cpu.num_store_insts                   31439752                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               731977718.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               732398340.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          29309705                       # Number of branches fetched
@@ -100,18 +100,18 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  278192465                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           2062733                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4076.488591                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4076.299825                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           120152370                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           2066829                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             58.133677                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle      126079705500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4076.488591                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995236                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995236                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle      126122344500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4076.299825                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.995190                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.995190                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1796                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2178                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1779                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2195                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         246505227                       # Number of tag accesses
@@ -132,14 +132,14 @@ system.cpu.dcache.demand_misses::cpu.data      2066829                       # n
 system.cpu.dcache.demand_misses::total        2066829                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      2066829                       # number of overall misses
 system.cpu.dcache.overall_misses::total       2066829                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  25498474000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  25498474000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2598457000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2598457000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  28096931000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  28096931000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  28096931000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  28096931000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  25499993500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  25499993500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2801625000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2801625000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  28301618500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  28301618500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  28301618500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  28301618500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     90779447                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     90779447                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
@@ -156,14 +156,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.016911
 system.cpu.dcache.demand_miss_rate::total     0.016911                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.016911                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.016911                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.648292                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.648292                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.563647                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.563647                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.221389                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13594.221389                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.221389                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13594.221389                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13693.255949                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13693.255949                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      2066829
 system.cpu.dcache.demand_mshr_misses::total      2066829                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      2066829                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      2066829                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23537754000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23537754000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2492348000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2492348000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26030102000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26030102000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26030102000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26030102000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23539273500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23539273500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2695516000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2695516000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26234789500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26234789500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26234789500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26234789500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.021599                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.021599                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003375                       # mshr miss rate for WriteReq accesses
@@ -198,24 +198,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016911
 system.cpu.dcache.demand_mshr_miss_rate::total     0.016911                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.016911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12004.648292                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12004.648292                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23488.563647                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23488.563647                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12594.221389                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12594.221389                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12594.221389                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12594.221389                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                24                       # number of replacements
-system.cpu.icache.tags.tagsinuse           665.632473                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           665.627299                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           217695356                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               808                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          269424.945545                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   665.632473                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.325016                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.325016                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   665.627299                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.325013                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.325013                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          784                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           23                       # Occupied blocks per task id
@@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst          808                       # n
 system.cpu.icache.demand_misses::total            808                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          808                       # number of overall misses
 system.cpu.icache.overall_misses::total           808                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     44233500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     44233500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     44233500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     44233500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     44233500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     44233500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     49857000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     49857000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     49857000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     49857000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     49857000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     49857000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    217696164                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    217696164                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    217696164                       # number of demand (read+write) accesses
@@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000004
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54744.430693                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54744.430693                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54744.430693                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54744.430693                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54744.430693                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54744.430693                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61704.207921                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61704.207921                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -267,44 +267,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks           24                       # number of writebacks
+system.cpu.icache.writebacks::total                24                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          808                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          808                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          808                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          808                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     43425500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     43425500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     43425500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     43425500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     43425500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     43425500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     49049000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     49049000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     49049000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     49049000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     49049000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     49049000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53744.430693                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53744.430693                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53744.430693                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53744.430693                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53744.430693                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53744.430693                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements              313                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20041.891909                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        20037.622351                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3992697                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            30021                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs           132.996802                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19329.043320                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   556.394677                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   156.453912                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.589876                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.016980                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   556.457266                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   156.452862                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.589743                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.016982                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.004775                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.611630                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.611500                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29708                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
@@ -314,8 +316,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27876
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.906616                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses         33179282                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses        33179282                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2062482                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2062482                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2062482                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2062482                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks           24                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total           24                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        77085                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        77085                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            5                       # number of ReadCleanReq hits
@@ -340,20 +344,22 @@ system.cpu.l2cache.demand_misses::total         30044                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          803                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        29241                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        30044                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1523791000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1523791000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     42159500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     42159500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     11392500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     11392500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     42159500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1535183500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1577343000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     42159500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1535183500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1577343000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2062482                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2062482                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1726959000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1726959000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     47782000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     47782000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     12911500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     12911500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     47782000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1739870500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1787652500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     47782000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1739870500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1787652500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2062482                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2062482                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks           24                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total           24                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       106109                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       106109                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          808                       # number of ReadCleanReq accesses(hits+misses)
@@ -378,18 +384,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.014531                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993812                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.014148                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.014531                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.490660                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.490660                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.490660                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.060155                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52501.098389                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.490660                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.060155                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52501.098389                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        59500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        59500                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -412,18 +418,18 @@ system.cpu.l2cache.demand_mshr_misses::total        30044
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          803                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        29241                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        30044                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1233551000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1233551000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     34129500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     34129500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data      9222500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total      9222500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34129500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1242773500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1276903000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34129500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1242773500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1276903000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1436719000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1436719000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     39752000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     39752000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     10741500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     10741500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     39752000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1447460500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1487212500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     39752000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1447460500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1487212500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.273530                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.273530                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.993812                       # mshr miss rate for ReadCleanReq accesses
@@ -436,18 +442,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.014531
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993812                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014148                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.014531                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42501.068082                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42501.068082                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.490660                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.490660                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.490660                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.060155                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.098389                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        49500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        49500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      4130394                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2062757                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -456,8 +462,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops          197                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          197                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp       1961528                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2062584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict          486                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2062584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           24                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          462                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       106109                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       106109                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          808                       # Transaction distribution
@@ -465,29 +472,29 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq      1960720
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1640                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6196391                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           6198031                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        53248                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    264275904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          264327616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          264329152                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                         313                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4130707                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000048                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.006906                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      2067950                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000095                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.009760                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            4130510    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                197      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2067753     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                197      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4130707                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4127679000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2067950                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4127703000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1212000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    3100243500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp               1020                       # Transaction distribution
-system.membus.trans_dist::Writeback               102                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          102                       # Transaction distribution
 system.membus.trans_dist::CleanEvict               14                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             29024                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            29024                       # Transaction distribution
@@ -509,9 +516,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total               30160                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            30601000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            30602500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          150253000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          150220000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index 91596dbee..168253993 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.412080                       # Number of seconds simulated
-sim_ticks                                412080064500                       # Number of ticks simulated
-final_tick                               412080064500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.412076                       # Number of seconds simulated
+sim_ticks                                412076211500                       # Number of ticks simulated
+final_tick                               412076211500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 310711                       # Simulator instruction rate (inst/s)
-host_op_rate                                   310711                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              209245414                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301844                       # Number of bytes of host memory used
-host_seconds                                  1969.36                       # Real time elapsed on the host
+host_inst_rate                                 332870                       # Simulator instruction rate (inst/s)
+host_op_rate                                   332870                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              224166223                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300688                       # Number of bytes of host memory used
+host_seconds                                  1838.26                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            170880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24123968                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24294848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       170880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          170880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18781376                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18781376                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2670                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             376937                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                379607                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293459                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293459                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               414677                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             58541944                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                58956621                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          414677                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             414677                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45577007                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45577007                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45577007                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              414677                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            58541944                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              104533628                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        379607                       # Number of read requests accepted
-system.physmem.writeReqs                       293459                       # Number of write requests accepted
-system.physmem.readBursts                      379607                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293459                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24271744                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     23104                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18779968                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24294848                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18781376                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      361                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            156480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24143168                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24299648                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       156480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          156480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18790784                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18790784                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2445                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             377237                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                379682                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293606                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293606                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               379736                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             58589085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                58968820                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          379736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             379736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45600264                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45600264                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45600264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              379736                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            58589085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              104569084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        379682                       # Number of read requests accepted
+system.physmem.writeReqs                       293606                       # Number of write requests accepted
+system.physmem.readBursts                      379682                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     293606                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24277120                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     22528                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18788736                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24299648                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18790784                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      352                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               23711                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               23184                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          51706                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               23686                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               23158                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               23442                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24496                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25435                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23571                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23637                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23952                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23149                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23951                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24706                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              22760                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23713                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24379                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22720                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              22440                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               17781                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24500                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25445                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23568                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23655                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23906                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23193                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23982                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24711                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              22783                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23721                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24390                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22740                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              22450                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               17782                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               17456                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17945                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18847                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               17944                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18851                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               19513                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18587                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18727                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18653                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18413                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18933                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18590                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18777                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18659                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18440                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18941                       # Per bank write bursts
 system.physmem.perBankWrBursts::10              19255                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18037                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18264                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18729                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17175                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17122                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18046                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18263                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18731                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17195                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17131                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    412079976500                       # Total gap between requests
+system.physmem.totGap                    412076182000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  379607                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  379682                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293459                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    377839                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1392                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293606                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    377941                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1374                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,31 +144,31 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    17014                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17467                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17482                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17538                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17498                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    17028                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17479                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17546                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17637                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17354                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       40                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
@@ -193,39 +193,39 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       142258                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      302.629870                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.695929                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.359961                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          50814     35.72%     35.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38804     27.28%     63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13098      9.21%     72.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         8314      5.84%     78.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5760      4.05%     82.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3818      2.68%     84.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2956      2.08%     86.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2613      1.84%     88.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16081     11.30%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         142258                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17331                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.881888                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      237.076982                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17323     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            3      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            2      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       142335                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      302.556532                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.740913                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.275213                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50726     35.64%     35.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38947     27.36%     63.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13162      9.25%     72.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8307      5.84%     78.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5691      4.00%     82.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3798      2.67%     84.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3047      2.14%     86.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2540      1.78%     88.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16117     11.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         142335                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17335                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.880819                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      236.752171                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17326     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17331                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17331                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.931337                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.860812                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.636907                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17131     98.85%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             149      0.86%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              30      0.17%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               5      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               5      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           17335                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17335                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.935333                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.864235                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.642113                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17130     98.82%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             152      0.88%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              27      0.16%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               9      0.05%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               6      0.03%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::36-39               1      0.01%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::52-55               1      0.01%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::56-59               1      0.01%     99.95% # Writes before turning the bus around for reads
@@ -235,87 +235,87 @@ system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Wr
 system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::156-159             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::224-227             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17331                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4068932250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11179794750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1896230000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10729.01                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           17335                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4058081750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11170519250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1896650000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10698.02                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29479.01                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          58.90                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          45.57                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       58.96                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       45.58                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29448.02                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          58.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          45.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       58.97                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       45.60                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.54                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     314133                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    216290                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.83                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                       612243.04                       # Average gap between requests
-system.physmem.pageHitRate                      78.85                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  548364600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  299206875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1493138400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                955858320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26915029440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            62103866355                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           192770777250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             285086241240                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              691.822973                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   320142846250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13760240000                       # Time in different power states
+system.physmem.avgWrQLen                        19.82                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314253                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    216307                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.84                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.67                       # Row buffer hit rate for writes
+system.physmem.avgGap                       612035.54                       # Average gap between requests
+system.physmem.pageHitRate                      78.84                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  548334360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  299190375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1492491000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                956130480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            26914520880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            61976871495                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           192877504500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             285065043090                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              691.784602                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   320322978500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13759980000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     78176682500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     77989027750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  527105880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  287607375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1464957000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                945613440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26915029440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            59197387905                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           195320319750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             284658020790                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              690.783804                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   324404039000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13760240000                       # Time in different power states
+system.physmem_1.actEnergy                  527491440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  287817750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1465854000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                945995760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26914520880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            59032825200                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           195460001250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             284634506280                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              690.739793                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   324635867250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13759980000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     73915489750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     73676135250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               123917174                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          87658941                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6214604                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             71577859                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67272092                       # Number of BTB hits
+system.cpu.branchPred.lookups               123917200                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87658954                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6214605                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71577882                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67272105                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.984499                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15041850                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1126019                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.984487                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15041853                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1126020                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    149344667                       # DTB read hits
-system.cpu.dtb.read_misses                     549014                       # DTB read misses
+system.cpu.dtb.read_hits                    149344669                       # DTB read hits
+system.cpu.dtb.read_misses                     549013                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                149893681                       # DTB read accesses
+system.cpu.dtb.read_accesses                149893682                       # DTB read accesses
 system.cpu.dtb.write_hits                    57319597                       # DTB write hits
 system.cpu.dtb.write_misses                     63704                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                57383301                       # DTB write accesses
-system.cpu.dtb.data_hits                    206664264                       # DTB hits
-system.cpu.dtb.data_misses                     612718                       # DTB misses
+system.cpu.dtb.data_hits                    206664266                       # DTB hits
+system.cpu.dtb.data_misses                     612717                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                207276982                       # DTB accesses
-system.cpu.itb.fetch_hits                   226051197                       # ITB hits
+system.cpu.dtb.data_accesses                207276983                       # DTB accesses
+system.cpu.itb.fetch_hits                   226051267                       # ITB hits
 system.cpu.itb.fetch_misses                        48                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               226051245                       # ITB accesses
+system.cpu.itb.fetch_accesses               226051315                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -329,24 +329,24 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu.numCycles                        824160129                       # number of cpu cycles simulated
+system.cpu.numCycles                        824152423                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   611901617                       # Number of instructions committed
 system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      12834592                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      12834608                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.346883                       # CPI: cycles per instruction
-system.cpu.ipc                               0.742455                       # IPC: instructions per cycle
-system.cpu.tickCycles                       739333640                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        84826489                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.346871                       # CPI: cycles per instruction
+system.cpu.ipc                               0.742462                       # IPC: instructions per cycle
+system.cpu.tickCycles                       739334528                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        84817895                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements           2535265                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.660702                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           202570424                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4087.660624                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           202570425                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           2539361                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             79.772204                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             79.772205                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1635033500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.660702                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.660624                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997964                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -355,16 +355,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1           73
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          829                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         3145                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         414584973                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        414584973                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146904267                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146904267                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses         414584975                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        414584975                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146904268                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146904268                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     55666157                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       55666157                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     202570424                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        202570424                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    202570424                       # number of overall hits
-system.cpu.dcache.overall_hits::total       202570424                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     202570425                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        202570425                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    202570425                       # number of overall hits
+system.cpu.dcache.overall_hits::total       202570425                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      1908505                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1908505                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      1543877                       # number of WriteReq misses
@@ -373,22 +373,22 @@ system.cpu.dcache.demand_misses::cpu.data      3452382                       # n
 system.cpu.dcache.demand_misses::total        3452382                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      3452382                       # number of overall misses
 system.cpu.dcache.overall_misses::total       3452382                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  37715152000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  37715152000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  47725761500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  47725761500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  85440913500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  85440913500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  85440913500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  85440913500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    148812772                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    148812772                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  37724666000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  37724666000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  47726490500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  47726490500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  85451156500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  85451156500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  85451156500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  85451156500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    148812773                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    148812773                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     57210034                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    206022806                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    206022806                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    206022806                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    206022806                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    206022807                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    206022807                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    206022807                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    206022807                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012825                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012825                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026986                       # miss rate for WriteReq accesses
@@ -397,14 +397,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.016757
 system.cpu.dcache.demand_miss_rate::total     0.016757                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.016757                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.016757                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19761.620745                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19761.620745                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30912.929916                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30912.929916                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24748.395021                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24748.395021                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24748.395021                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24748.395021                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19766.605799                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19766.605799                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30913.402104                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30913.402104                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24751.361958                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24751.361958                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24751.361958                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24751.361958                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -413,8 +413,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2339622                       # number of writebacks
-system.cpu.dcache.writebacks::total           2339622                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      2339407                       # number of writebacks
+system.cpu.dcache.writebacks::total           2339407                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143967                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total       143967                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769054                       # number of WriteReq MSHR hits
@@ -431,14 +431,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      2539361
 system.cpu.dcache.demand_mshr_misses::total      2539361                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      2539361                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      2539361                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33198964500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33198964500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23344010000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  23344010000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56542974500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  56542974500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56542974500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  56542974500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33207035500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33207035500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23344377500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  23344377500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56551413000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  56551413000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56551413000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  56551413000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.011857                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011857                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.013543                       # mshr miss rate for WriteReq accesses
@@ -447,69 +447,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012326
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012326                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012326                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012326                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18814.536440                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18814.536440                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.184114                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.184114                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22266.615302                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22266.615302                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22266.615302                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22266.615302                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18819.110441                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18819.110441                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.658416                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.658416                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22269.938382                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22269.938382                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22269.938382                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22269.938382                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              3153                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1116.819230                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           226046216                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4981                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          45381.693636                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              3156                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1116.812774                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           226046283                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4984                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45354.390650                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1116.819230                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545322                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.545322                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1116.812774                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.545319                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.545319                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1828                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1590                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.892578                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         452107375                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        452107375                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    226046216                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       226046216                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     226046216                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        226046216                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    226046216                       # number of overall hits
-system.cpu.icache.overall_hits::total       226046216                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4981                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4981                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4981                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4981                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4981                       # number of overall misses
-system.cpu.icache.overall_misses::total          4981                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    245472000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    245472000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    245472000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    245472000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    245472000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    245472000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    226051197                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    226051197                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    226051197                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    226051197                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    226051197                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    226051197                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         452107518                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        452107518                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    226046283                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       226046283                       # number of ReadReq hits
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+system.cpu.icache.demand_hits::total        226046283                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    226046283                       # number of overall hits
+system.cpu.icache.overall_hits::total       226046283                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4984                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4984                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4984                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4984                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4984                       # number of overall misses
+system.cpu.icache.overall_misses::total          4984                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    231170500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    231170500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    231170500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    231170500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    231170500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    231170500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    226051267                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    226051267                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    226051267                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    226051267                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    226051267                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    226051267                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49281.670347                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49281.670347                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49281.670347                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49281.670347                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49281.670347                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49281.670347                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46382.524077                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 46382.524077                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 46382.524077                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 46382.524077                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 46382.524077                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 46382.524077                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -518,129 +518,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4981                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4981                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4981                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4981                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4981                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4981                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    240491000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    240491000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    240491000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    240491000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    240491000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    240491000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         3156                       # number of writebacks
+system.cpu.icache.writebacks::total              3156                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4984                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4984                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4984                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4984                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4984                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4984                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    226186500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    226186500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    226186500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    226186500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    226186500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    226186500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48281.670347                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48281.670347                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48281.670347                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48281.670347                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48281.670347                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48281.670347                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45382.524077                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 45382.524077                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 45382.524077                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           346897                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29502.927026                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3908665                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           379320                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.304400                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     189124044500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21307.222747                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   177.805871                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8017.898409                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.650245                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005426                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.244687                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.900358                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32423                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           78                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           347699                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29505.280941                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3908745                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           380129                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.282680                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     189125528500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21321.882455                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.938322                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8022.460164                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.650692                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004911                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.244826                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.900430                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32430                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13170                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18832                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989471                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41819560                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41819560                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2339622                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2339622                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       571899                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       571899                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2311                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         2311                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590525                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1590525                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2311                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2162424                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2164735                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2311                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2162424                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2164735                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206261                       # number of ReadExReq misses
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989685                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80630.219333                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78539.263804                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::total 79525.146043                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -649,122 +655,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       293459                       # number of writebacks
-system.cpu.l2cache.writebacks::total           293459                       # number of writebacks
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 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69564.106203                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69554.365436                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.265125                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265125                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.490570                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.490570                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.097051                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.097051                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.490570                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148556                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.149226                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.490570                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148556                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.149226                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68621.281082                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68621.281082                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68539.263804                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68539.263804                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70630.219333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70630.219333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68539.263804                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.535878                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69525.146043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68539.263804                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.535878                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69525.146043                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5082760                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538418                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5082766                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538421                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         2391                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2391                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       1766182                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2633081                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       252234                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1766185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2633013                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         3156                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       249951                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       778160                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       778160                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4981                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4984                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761201                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13115                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13124                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7613987                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7627102                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       318784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312254912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312573696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      346897                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5429657                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000440                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.020980                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count::total           7627111                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       520960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312241152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312762112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      347699                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2892044                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000827                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.028741                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5427266     99.96%     99.96% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2391      0.04%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2889653     99.92%     99.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2391      0.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5429657                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4881002000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2892044                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4883946000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7471500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7476000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    3809041500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             173346                       # Transaction distribution
-system.membus.trans_dist::Writeback            293459                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            51785                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206261                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206261                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        173346                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104458                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1104458                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43076224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43076224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             173372                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       293606                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            51706                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206310                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206310                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        173372                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104676                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1104676                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43090432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43090432                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            724851                       # Request fanout histogram
+system.membus.snoop_fanout::samples            724994                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  724851    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  724994    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              724851                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2020156500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              724994                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2020992000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2008875000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2009252250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 7a68c081f..232b217c8 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.363600                       # Number of seconds simulated
-sim_ticks                                363599502500                       # Number of ticks simulated
-final_tick                               363599502500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.363578                       # Number of seconds simulated
+sim_ticks                                363578056500                       # Number of ticks simulated
+final_tick                               363578056500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 226144                       # Simulator instruction rate (inst/s)
-host_op_rate                                   244944                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              162315109                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 321124                       # Number of bytes of host memory used
-host_seconds                                  2240.08                       # Real time elapsed on the host
+host_inst_rate                                 237399                       # Simulator instruction rate (inst/s)
+host_op_rate                                   257134                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              170382928                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321244                       # Number of bytes of host memory used
+host_seconds                                  2133.89                       # Real time elapsed on the host
 sim_insts                                   506582156                       # Number of instructions simulated
 sim_ops                                     548695379                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            219456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9004480                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9223936                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       219456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          219456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6189376                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6189376                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3429                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140695                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                144124                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96709                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                96709                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               603565                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             24764830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25368396                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          603565                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             603565                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          17022510                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               17022510                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          17022510                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              603565                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            24764830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42390905                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        144124                       # Number of read requests accepted
-system.physmem.writeReqs                        96709                       # Number of write requests accepted
-system.physmem.readBursts                      144124                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      96709                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9217920                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6016                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6188224                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9223936                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6189376                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       94                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            179648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9032384                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9212032                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       179648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          179648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6219008                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6219008                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2807                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141131                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                143938                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97172                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97172                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               494111                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24843039                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25337151                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          494111                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             494111                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          17105015                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               17105015                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          17105015                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              494111                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            24843039                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42442165                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        143938                       # Number of read requests accepted
+system.physmem.writeReqs                        97172                       # Number of write requests accepted
+system.physmem.readBursts                      143938                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97172                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9204928                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7104                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6217152                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9212032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6219008                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      111                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9331                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8969                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9003                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8675                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9453                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9352                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8945                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8102                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8582                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8674                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8765                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9476                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9348                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9513                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8719                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9123                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6195                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6094                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6011                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5821                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6181                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6188                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6015                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5499                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5743                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5830                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5965                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6463                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6312                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6285                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6003                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6086                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          12571                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9337                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8920                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8993                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8670                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9385                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9354                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8954                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8104                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8602                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8629                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8738                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9458                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9338                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9514                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8722                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9109                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6210                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6096                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6031                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5885                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6239                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6240                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6045                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5507                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5786                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5860                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5977                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6497                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6353                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6323                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6005                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6089                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    363599476500                       # Total gap between requests
+system.physmem.totGap                    363578030500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  144124                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  143938                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  96709                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    143660                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       349                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97172                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    143477                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       330                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2957                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5541                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5659                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5712                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5596                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2944                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5718                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5621                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
@@ -193,124 +193,112 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65302                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      235.912652                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     156.372535                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     241.914583                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24788     37.96%     37.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18406     28.19%     66.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6849     10.49%     76.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7905     12.11%     88.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2084      3.19%     91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1111      1.70%     93.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          761      1.17%     94.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          643      0.98%     95.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2755      4.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65302                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5583                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.797421                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      381.883100                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5579     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            3      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65452                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      235.611563                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     156.275569                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     241.348204                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24841     37.95%     37.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18422     28.15%     66.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6870     10.50%     76.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7970     12.18%     88.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2117      3.23%     92.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1100      1.68%     93.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          791      1.21%     94.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          584      0.89%     95.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2757      4.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65452                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5612                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.626515                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      380.491009                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5610     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5583                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5583                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.318825                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.224966                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.238810                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               2516     45.07%     45.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 99      1.77%     46.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               2663     47.70%     94.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                163      2.92%     97.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 38      0.68%     98.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 18      0.32%     98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 14      0.25%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  8      0.14%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  6      0.11%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  9      0.16%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  5      0.09%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  4      0.07%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  4      0.07%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  6      0.11%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  2      0.04%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  3      0.05%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  2      0.04%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  4      0.07%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34                  2      0.04%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  2      0.04%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  2      0.04%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40                  1      0.02%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  1      0.02%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::43                  1      0.02%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44                  1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::47                  1      0.02%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50                  2      0.04%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52                  1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::53                  1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::55                  1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::61                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5583                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1538433000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4238995500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    720150000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10681.34                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5612                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5612                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.309872                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.213078                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.394006                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            2658     47.36%     47.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            2810     50.07%     97.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              50      0.89%     98.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              29      0.52%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              20      0.36%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              11      0.20%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               6      0.11%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               6      0.11%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               3      0.05%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               7      0.12%     99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               1      0.02%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39               1      0.02%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               1      0.02%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47               1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               2      0.04%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-73               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-97               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5612                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1537591000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4234347250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    719135000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10690.56                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29431.34                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.35                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          17.02                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.37                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       17.02                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29440.56                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.32                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          17.10                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.34                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       17.11                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.80                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     110870                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64542                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.98                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.74                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1509757.70                       # Average gap between requests
-system.physmem.pageHitRate                      72.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  248293080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  135477375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 560086800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                310832640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            23748226320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47486002320                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           176502477750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             248991396285                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              684.804658                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   293320694250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     12141220000                       # Time in different power states
+system.physmem.avgWrQLen                        19.82                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     110822                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64690                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.05                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.57                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1507934.26                       # Average gap between requests
+system.physmem.pageHitRate                      72.83                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  249245640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  135997125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 559174200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                312459120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            23746700640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            47224643355                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           176717716500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             248945936580                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              684.723644                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   293681207750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12140440000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     58133810750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     57750923750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  245148120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  133761375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 562957200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                315401040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            23748226320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            46957937220                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           176965692750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             248929124025                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              684.633389                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   294092512000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     12141220000                       # Time in different power states
+system.physmem_1.actEnergy                  245314440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  133852125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 562247400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                316716480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            23746700640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            46957257495                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           176952265500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             248914354080                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              684.636777                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   294072895750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12140440000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     57361058000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     57359475250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               131895360                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98029927                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6139026                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             68388068                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                64396789                       # Number of BTB hits
+system.cpu.branchPred.lookups               131892190                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98029664                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6137262                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             68271020                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                64393265                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.163779                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9981632                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              18119                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.320057                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9980136                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              17826                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -429,98 +417,98 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        727199005                       # number of cpu cycles simulated
+system.cpu.numCycles                        727156113                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506582156                       # Number of instructions committed
 system.cpu.committedOps                     548695379                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13199573                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      13195789                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.435501                       # CPI: cycles per instruction
-system.cpu.ipc                               0.696621                       # IPC: instructions per cycle
-system.cpu.tickCycles                       690715590                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        36483415                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1139984                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.789434                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           171168644                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1144080                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            149.612478                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.435416                       # CPI: cycles per instruction
+system.cpu.ipc                               0.696662                       # IPC: instructions per cycle
+system.cpu.tickCycles                       690690437                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        36465676                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1139983                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.787946                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           171168228                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1144079                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            149.612245                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        4896334500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.789434                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.787946                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993845                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993845                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          551                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3499                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3500                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         346592332                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        346592332                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114650184                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114650184                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     53538625                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53538625                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         346591347                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        346591347                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114649758                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114649758                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53538635                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53538635                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         2753                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          2753                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168188809                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168188809                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168191562                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168191562                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       854786                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        854786                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       700681                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       700681                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1555467                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1555467                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1555482                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1555482                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14024022500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14024022500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21893600500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21893600500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35917623000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35917623000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35917623000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35917623000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    115504970                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    115504970                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     168188393                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168188393                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168191146                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168191146                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       854719                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        854719                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       700671                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       700671                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           16                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           16                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1555390                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1555390                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1555406                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1555406                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14046321000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14046321000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21904504500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21904504500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35950825500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35950825500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35950825500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35950825500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    115504477                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115504477                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2768                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2768                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2769                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2769                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    169744276                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    169744276                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    169747044                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    169747044                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    169743783                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169743783                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    169746552                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169746552                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007400                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.007400                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012918                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.012918                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005419                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.005419                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009164                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009164                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009164                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009164                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.471912                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.471912                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31246.174079                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31246.174079                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23091.215050                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23091.215050                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.992374                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23090.992374                       # average overall miss latency
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005778                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.005778                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009163                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009163                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009163                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009163                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16433.846679                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16433.846679                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31262.182251                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31262.182251                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23113.704923                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23113.704923                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23113.467159                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23113.467159                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -529,111 +517,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1068583                       # number of writebacks
-system.cpu.dcache.writebacks::total           1068583                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66886                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        66886                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344513                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344513                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       411399                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       411399                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       411399                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       411399                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787900                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       787900                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356168                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356168                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1144068                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1144068                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1144080                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1144080                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12337991000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12337991000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11121217500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11121217500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       946000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       946000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23459208500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23459208500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23460154500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  23460154500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      1068257                       # number of writebacks
+system.cpu.dcache.writebacks::total           1068257                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66817                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        66817                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344507                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       344507                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       411324                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       411324                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       411324                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       411324                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       787902                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       787902                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356164                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       356164                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           13                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total           13                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1144066                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1144066                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1144079                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1144079                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12362476000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12362476000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11126251500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11126251500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1030500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1030500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23488727500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23488727500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23489758000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  23489758000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006821                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006821                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006567                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006567                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004335                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004335                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004695                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004695                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006740                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006740                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006740                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006740                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.336210                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.336210                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31224.639777                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31224.639777                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78833.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78833.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20505.082303                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20505.082303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20505.694095                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20505.694095                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15690.372661                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15690.372661                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.124392                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.124392                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79269.230769                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79269.230769                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20530.919982                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20530.919982                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20531.587417                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20531.587417                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             17702                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1188.317648                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           199314883                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             19574                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          10182.634260                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             17711                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1188.286888                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           199302654                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             19583                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          10177.330031                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1188.317648                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.580233                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.580233                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1188.286888                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.580218                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.580218                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          306                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1404                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          309                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1403                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         398688488                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        398688488                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    199314883                       # number of ReadReq hits
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-system.cpu.icache.demand_misses::total          19574                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        19574                       # number of overall misses
-system.cpu.icache.overall_misses::total         19574                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    491333500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    491333500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    491333500                       # number of demand (read+write) miss cycles
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000098                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000098                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000098                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000098                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000098                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000098                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25101.333401                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25101.333401                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25101.333401                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25101.333401                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25101.333401                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25101.333401                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22968.314354                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22968.314354                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22968.314354                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22968.314354                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22968.314354                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22968.314354                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -642,128 +630,134 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19574                       # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total    471759500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    471759500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    471759500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    471759500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    471759500                       # number of overall MSHR miss cycles
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+system.cpu.icache.writebacks::total             17711                       # number of writebacks
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000098                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000098                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24101.333401                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24101.333401                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24101.333401                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24101.333401                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24101.333401                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24101.333401                       # average overall mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21968.314354                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::total 21968.314354                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21968.314354                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21968.314354                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           111370                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27634.033642                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1767249                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           142558                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.396702                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     163253473000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23457.713364                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   389.652620                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3786.667658                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.715873                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_percent::cpu.data     0.115560                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.843324                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31188                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          323                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4939                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25857                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951782                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         19030322                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        19030322                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      1068583                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1068583                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       255591                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       255591                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        16143                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        16143                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       747780                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       747780                       # number of ReadSharedReq hits
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-system.cpu.l2cache.demand_hits::cpu.data      1003371                       # number of demand (read+write) hits
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-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82301.792879                       # average ReadSharedReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79511.179100                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::total 79507.686971                       # average overall miss latency
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+system.cpu.l2cache.tags.tagsinuse        27636.027175                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1768435                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           143575                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.317151                       # Average number of references to valid blocks.
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78394.300605                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78394.300605                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79777.599715                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79777.599715                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82300.370444                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82300.370444                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79777.599715                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79507.410819                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79512.681222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79777.599715                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79507.410819                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79512.681222                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -772,132 +766,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        96709                       # number of writebacks
-system.cpu.l2cache.writebacks::total            96709                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
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 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           14                       # number of ReadSharedReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1197                       # number of CleanEvict MSHR misses
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-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282894                       # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68407.432386                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68407.432386                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69320.939049                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69320.939049                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72297.923042                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72297.923042                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69320.939049                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69509.804897                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69505.311399                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69320.939049                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69509.804897                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69505.311399                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100923                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       100923                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2807                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2807                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        40208                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        40208                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2807                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       141131                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       143938                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2807                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       141131                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       143938                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6902558000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6902558000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    195877500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    195877500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2907247000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2907247000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195877500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9809805000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10005682500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195877500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9809805000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10005682500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283161                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283161                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.143339                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.143339                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.051047                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.051047                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.143339                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123358                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123694                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.143339                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123358                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123694                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68394.300605                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68394.300605                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69781.795511                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69781.795511                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72305.188022                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72305.188022                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69781.795511                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69508.506281                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.835818                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69781.795511                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69508.506281                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69513.835818                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      2321340                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      1157756                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4922                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2616                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2613                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      2321356                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      1157764                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4913                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2623                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2620                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        807234                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1165292                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        98842                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       356420                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       356420                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        19574                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       787660                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56613                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3423459                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3480072                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1252736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141610432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          142863168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      111370                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2432710                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.005152                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.071609                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        807247                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1165429                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        17475                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        82243                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       356415                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       356415                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        19583                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       787664                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56641                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3423464                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3480105                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2371712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141589504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          143961216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      112366                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1276028                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.005963                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.077021                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2420180     99.48%     99.48% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              12527      0.51%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1268422     99.40%     99.40% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               7603      0.60%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2432710                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2229253000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1276028                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2246646000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      29379463                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      29392963                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1716126986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1716126983                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              43295                       # Transaction distribution
-system.membus.trans_dist::Writeback             96709                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            13242                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100829                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100829                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         43295                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       398199                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 398199                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15413312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15413312                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              43015                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        97172                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            12571                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100923                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100923                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         43015                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397619                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 397619                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15431040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15431040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            254075                       # Request fanout histogram
+system.membus.snoop_fanout::samples            253681                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  254075    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  253681    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              254075                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           683661500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              253681                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           685231500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          765035500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          764006500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 153b00611..29a3d1e47 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.233306                       # Number of seconds simulated
-sim_ticks                                233306027000                       # Number of ticks simulated
-final_tick                               233306027000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.234001                       # Number of seconds simulated
+sim_ticks                                234001297000                       # Number of ticks simulated
+final_tick                               234001297000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128535                       # Simulator instruction rate (inst/s)
-host_op_rate                                   139249                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59354207                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322028                       # Number of bytes of host memory used
-host_seconds                                  3930.74                       # Real time elapsed on the host
+host_inst_rate                                 134504                       # Simulator instruction rate (inst/s)
+host_op_rate                                   145716                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               62295833                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 343376                       # Number of bytes of host memory used
+host_seconds                                  3756.29                       # Real time elapsed on the host
 sim_insts                                   505237724                       # Number of instructions simulated
 sim_ops                                     547350945                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            683648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9174464                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     16490944                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26349056                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       683648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          683648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18702784                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18702784                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              10682                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             143351                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       257671                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                411704                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          292231                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               292231                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2930263                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39323733                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     70683746                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               112937742                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2930263                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2930263                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          80164170                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               80164170                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          80164170                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2930263                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39323733                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     70683746                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              193101912                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        411704                       # Number of read requests accepted
-system.physmem.writeReqs                       292231                       # Number of write requests accepted
-system.physmem.readBursts                      411704                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     292231                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26211648                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    137408                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18700672                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26349056                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18702784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2147                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       4                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              2                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26604                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25479                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25122                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24753                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27168                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               26312                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25243                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24096                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25848                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24676                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25150                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              26103                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26513                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25940                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25062                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25488                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18828                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               18294                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17806                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               17978                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18719                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18281                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               17995                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               17635                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18144                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17824                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18107                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18749                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18847                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18260                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              18418                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              18313                       # Per bank write bursts
+system.physmem.bytes_read::cpu.inst            517504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10131008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     16480064                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             27128576                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       517504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          517504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18730688                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18730688                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               8086                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158297                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       257501                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                423884                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292667                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292667                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2211543                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             43294666                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     70427234                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               115933443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2211543                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2211543                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          80045232                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               80045232                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          80045232                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2211543                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            43294666                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     70427234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              195978674                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        423884                       # Number of read requests accepted
+system.physmem.writeReqs                       292667                       # Number of write requests accepted
+system.physmem.readBursts                      423884                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292667                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26972992                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    155584                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18728832                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  27128576                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18730688                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     2431                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          98651                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               26584                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25337                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25274                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               32197                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27335                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               28299                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25126                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24198                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25368                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25926                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25318                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              26278                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27572                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25872                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25056                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25713                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18662                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               18231                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18003                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               17875                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18721                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18310                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               17836                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               17744                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               17983                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17940                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18239                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18938                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18976                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18211                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              18390                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              18579                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    233306009000                       # Total gap between requests
+system.physmem.totGap                    234001244500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  411704                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  423884                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 292231                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    311101                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     49294                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13059                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9199                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7392                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6207                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5318                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4408                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3416                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        86                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       39                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       19                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 292667                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    323806                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     49376                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     12876                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8979                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7297                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5227                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4284                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3341                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        70                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,35 +148,35 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6347                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    13179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    15360                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    16390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    16942                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    18016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    18369                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    18501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    18840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    20067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    18284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     7238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    12413                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    15049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    16333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    16979                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17603                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17899                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    18115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    18307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    18692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    18718                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    18910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    19072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17647                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
@@ -197,103 +197,112 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       306850                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      146.361336                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     102.891492                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     182.277612                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         184544     60.14%     60.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        81708     26.63%     86.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        16503      5.38%     92.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7231      2.36%     94.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         4881      1.59%     96.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2237      0.73%     96.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1756      0.57%     97.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1532      0.50%     97.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6458      2.10%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         306850                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17319                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.647035                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      116.821350                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           17318     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17319                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17319                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.871528                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.829762                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.229266                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              10538     60.85%     60.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                299      1.73%     62.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               5524     31.90%     94.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                601      3.47%     97.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                136      0.79%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 86      0.50%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 52      0.30%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 38      0.22%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 24      0.14%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 14      0.08%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  5      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17319                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     9105020732                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16784214482                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2047785000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22231.39                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       322061                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      141.901068                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      99.764285                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     180.057081                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         202493     62.87%     62.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        79759     24.77%     87.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        15144      4.70%     92.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7279      2.26%     94.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         4961      1.54%     96.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2580      0.80%     96.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1828      0.57%     97.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1538      0.48%     97.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6479      2.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         322061                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17076                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.676095                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      143.384257                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17074     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::18432-19455            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           17076                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17076                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.137386                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.076722                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.519222                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               9254     54.19%     54.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                359      2.10%     56.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               5270     30.86%     87.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1365      7.99%     95.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                405      2.37%     97.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                163      0.95%     98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                106      0.62%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 62      0.36%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 41      0.24%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 19      0.11%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 11      0.06%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  5      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  3      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  3      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  3      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  2      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17076                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8693371575                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16595615325                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2107265000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20627.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  40981.39                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         112.35                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          80.16                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      112.94                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       80.16                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39377.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         115.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          80.04                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      115.93                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       80.05                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.50                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.88                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           1.53                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.90                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.84                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     299267                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95628                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.07                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  32.72                       # Row buffer hit rate for writes
-system.physmem.avgGap                       331431.18                       # Average gap between requests
-system.physmem.pageHitRate                      56.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1155833280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  630663000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1596964200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                942956640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            15237983280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            74824379370                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            74344372500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             168733152270                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              723.246471                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   123152752220                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7790380000                       # Time in different power states
+system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.60                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     306420                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     85606                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   72.71                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  29.25                       # Row buffer hit rate for writes
+system.physmem.avgGap                       326566.07                       # Average gap between requests
+system.physmem.pageHitRate                      54.90                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1224553680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  668159250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1671883200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                942075360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            15283753680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            82043634285                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            68432158500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             170266217955                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              727.632069                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   113312610225                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7813780000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    102358687280                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    112874154775                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1163673000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  634940625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1597073400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                950279040                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            15237983280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            74177760825                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            74911581750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             168673291920                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              722.989890                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   124105976502                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7790380000                       # Time in different power states
+system.physmem_1.actEnergy                 1210227480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  660342375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1615325400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                954218880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            15283753680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            79914700530                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            70299646500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             169938214845                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              726.230337                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   116426727240                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7813780000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    101406021498                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    109759940510                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               175092094                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         131341607                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7444018                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90535143                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83876326                       # Number of BTB hits
+system.cpu.branchPred.lookups               175128597                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         131371974                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7444955                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90537565                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83893856                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.645047                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12109430                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104164                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.661931                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12111370                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104180                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -412,129 +421,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        466612055                       # number of cpu cycles simulated
+system.cpu.numCycles                        468002595                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            7841296                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      731804732                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   175092094                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           95985756                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     450426990                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14940841                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 5959                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           183                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        13996                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 236719309                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 34673                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          465758844                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.701594                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.179451                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            7807530                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      731939592                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   175128597                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           96005226                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     452073756                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14942657                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 4553                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           179                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        11657                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 236761982                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 33954                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          467369003                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.696062                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.181505                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 93829138     20.15%     20.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                132701430     28.49%     48.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 57853582     12.42%     61.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                181374694     38.94%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 95368751     20.41%     20.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                132719598     28.40%     48.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 57874720     12.38%     61.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                181405934     38.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            465758844                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.375241                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.568337                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32366390                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             117283842                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 287098365                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              22028374                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6981873                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             24050011                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                496385                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              715808617                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              30003155                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6981873                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 63420619                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                54156177                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       40346363                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276695654                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              24158158                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              686602803                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13340804                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               9402338                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2387140                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1669358                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1928954                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           831026912                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3019223277                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        723937000                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            467369003                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.374204                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.563965                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32359971                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             118993599                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 286955454                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              22077159                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6982820                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             24051378                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                496211                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              715838012                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              30014698                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6982820                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 63444256                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                55810223                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       40372652                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 276569326                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              24189726                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              686622974                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13340540                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               9445783                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2386683                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1668073                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1901045                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           831058832                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3019300335                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        723953090                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               416                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             654123751                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                176903161                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1544702                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1535188                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  42285800                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            143529225                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            67986348                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12855797                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11202653                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  668172379                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2978330                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 610256171                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5859842                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       123799764                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    319235639                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            698                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     465758844                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.310241                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.101448                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                176935081                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1544712                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1535132                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  42423418                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            143529755                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            67982396                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12868793                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11217167                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  668185878                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2978339                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 610253474                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5862945                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       123813272                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    319307246                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            707                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     467369003                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.305721                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.102066                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           148618613     31.91%     31.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           101179975     21.72%     53.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           145721974     31.29%     84.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            63321350     13.60%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6916462      1.48%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 470      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           150209828     32.14%     32.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           101164226     21.65%     53.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           145806231     31.20%     84.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            63278562     13.54%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6909680      1.48%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 476      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       465758844                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       467369003                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                71923603     52.95%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     30      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44560845     32.81%     85.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              19351011     14.25%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                71905667     52.96%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     30      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44557603     32.82%     85.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              19305643     14.22%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             413149972     67.70%     67.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               351777      0.06%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             413150420     67.70%     67.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               351795      0.06%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
@@ -562,84 +571,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            134213690     21.99%     89.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            62540729     10.25%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            134216313     21.99%     89.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            62534943     10.25%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              610256171                       # Type of FU issued
-system.cpu.iq.rate                           1.307845                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   135835489                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.222588                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1827966224                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         794978756                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    594986581                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              610253474                       # Type of FU issued
+system.cpu.iq.rate                           1.303953                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   135768943                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.222480                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1829507546                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         795005708                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    594983942                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 293                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                316                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              746091483                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              746022240                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     177                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          7271635                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          7274295                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     27644469                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        25562                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        29008                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     11125871                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     27644999                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        25509                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        28969                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     11121919                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       225728                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         22400                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       225058                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         22341                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6981873                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                22924718                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                919849                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           672638124                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                6982820                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                22939909                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                921157                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           672651686                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             143529225                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             67986348                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1489788                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 258699                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                524927                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          29008                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3821848                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3731355                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7553203                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             599403304                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             129574600                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10852867                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             143529755                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             67982396                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1489797                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 258383                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                526747                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          28969                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3822799                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3731713                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7554512                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             599398028                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             129575309                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10855446                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1487415                       # number of nop insts executed
-system.cpu.iew.exec_refs                    190539133                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                131373270                       # Number of branches executed
-system.cpu.iew.exec_stores                   60964533                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.284586                       # Inst execution rate
-system.cpu.iew.wb_sent                      596281070                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     594986597                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 349903865                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 570650112                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       1487469                       # number of nop insts executed
+system.cpu.iew.exec_refs                    190532110                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                131373386                       # Number of branches executed
+system.cpu.iew.exec_stores                   60956801                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.280758                       # Inst execution rate
+system.cpu.iew.wb_sent                      596278477                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     594983958                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 349895185                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 570621697                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.275121                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.613167                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.271326                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.613182                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       110031903                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       110038028                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6955471                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    448643201                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.223009                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.887847                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6956447                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    450252376                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.218638                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.886273                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    219610457     48.95%     48.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    116308832     25.92%     74.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43746420      9.75%     84.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     23291517      5.19%     89.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11578245      2.58%     92.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7791027      1.74%     94.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8269909      1.84%     95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4243315      0.95%     96.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     13803479      3.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    221217275     49.13%     49.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    116327442     25.84%     74.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43752953      9.72%     84.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     23318372      5.18%     89.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11527046      2.56%     92.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7779334      1.73%     94.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8252081      1.83%     95.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4233959      0.94%     96.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13843914      3.07%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    448643201                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    450252376                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506581608                       # Number of instructions committed
 system.cpu.commit.committedOps              548694829                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -685,385 +694,391 @@ system.cpu.commit.op_class_0::MemWrite       56860477     10.36%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         548694829                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              13803479                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1093559316                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1334598854                       # The number of ROB writes
-system.cpu.timesIdled                           13995                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          853211                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              13843914                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1095134181                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1334612111                       # The number of ROB writes
+system.cpu.timesIdled                           12504                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          633592                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505237724                       # Number of Instructions Simulated
 system.cpu.committedOps                     547350945                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.923550                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.923550                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.082779                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.082779                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                611100755                       # number of integer regfile reads
-system.cpu.int_regfile_writes               328116502                       # number of integer regfile writes
+system.cpu.cpi                               0.926302                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.926302                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.079562                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.079562                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                611088799                       # number of integer regfile reads
+system.cpu.int_regfile_writes               328120173                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                2170188783                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                376538117                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               217976814                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                2170182732                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                376542810                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               217972310                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2820876                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.631746                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           169355780                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2821388                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             60.025697                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         498153000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.631746                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999281                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999281                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2820726                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.629844                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           169352944                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2821238                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             60.027883                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         500883000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.629844                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999277                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999277                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          273                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          281                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         356248226                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        356248226                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114651895                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114651895                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     51723951                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       51723951                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2787                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2787                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488560                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488560                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         356245422                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        356245422                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114648159                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114648159                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     51724842                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       51724842                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2783                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2783                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488558                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488558                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     166375846                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        166375846                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    166378633                       # number of overall hits
-system.cpu.dcache.overall_hits::total       166378633                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4842252                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4842252                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2515355                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2515355                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     166373001                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        166373001                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    166375784                       # number of overall hits
+system.cpu.dcache.overall_hits::total       166375784                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4844666                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4844666                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2514464                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2514464                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      7357607                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        7357607                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7357619                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7357619                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  56173880000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  56173880000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  19052445440                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  19052445440                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1310000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      1310000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  75226325440                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  75226325440                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  75226325440                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  75226325440                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    119494147                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    119494147                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           67                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           67                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      7359130                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7359130                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7359142                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7359142                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57569719500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57569719500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18925127941                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18925127941                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       941000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       941000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  76494847441                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  76494847441                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  76494847441                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  76494847441                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    119492825                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    119492825                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2799                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2799                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488626                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488626                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2795                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2795                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488625                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488625                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    173733453                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    173733453                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    173736252                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    173736252                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040523                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040523                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046375                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.046375                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004287                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.004287                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.042350                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.042350                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.042349                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.042349                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11600.775837                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11600.775837                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7574.455868                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  7574.455868                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19848.484848                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19848.484848                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10224.292415                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10224.292415                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10224.275739                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10224.275739                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           92                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       932011                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 8                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          221163                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     4.214136                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    173732131                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    173732131                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    173734926                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    173734926                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040544                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040544                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046359                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.046359                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004293                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.004293                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000045                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000045                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.042359                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.042359                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.042358                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.042358                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7526.505824                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  7526.505824                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10394.550367                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10394.533417                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           17                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       905651                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          221227                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     4.093763                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2352880                       # number of writebacks
-system.cpu.dcache.writebacks::total           2352880                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2540436                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2540436                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1995769                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1995769                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4536205                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4536205                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4536205                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4536205                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2301816                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2301816                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519586                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       519586                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      2820726                       # number of writebacks
+system.cpu.dcache.writebacks::total           2820726                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2542974                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      2542974                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1994900                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1994900                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           67                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           67                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      4537874                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4537874                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4537874                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4537874                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2301692                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2301692                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519564                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       519564                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2821402                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2821402                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2821412                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2821412                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28692574000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  28692574000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4617588494                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4617588494                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       686000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       686000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33310162494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  33310162494                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  33310848494                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  33310848494                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019263                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019263                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009580                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009580                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003573                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003573                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016240                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016240                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016240                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.016240                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12465.190093                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12465.190093                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8887.053335                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8887.053335                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        68600                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        68600                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11806.244730                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11806.244730                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11806.446026                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11806.446026                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_misses::cpu.data      2821256                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2821256                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2821266                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2821266                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29568664500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  29568664500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603651495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603651495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       644000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       644000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34172315995                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  34172315995                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34172959995                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  34172959995                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019262                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019262                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009579                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009579                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003578                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003578                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016239                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016239                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016239                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.016239                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12846.490538                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12846.490538                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8860.605229                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8860.605229                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        64400                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        64400                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.447787                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.447787                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.633121                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.633121                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             73459                       # number of replacements
-system.cpu.icache.tags.tagsinuse           466.213956                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           236636536                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             73971                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3199.044707                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      114942017500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   466.213956                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.910574                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.910574                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             73505                       # number of replacements
+system.cpu.icache.tags.tagsinuse           466.324466                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           236680067                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             74017                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3197.644690                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      115567558500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   466.324466                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.910790                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.910790                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          119                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4           17                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          120                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           19                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4           16                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         473512362                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        473512362                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    236636536                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       236636536                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     236636536                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        236636536                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    236636536                       # number of overall hits
-system.cpu.icache.overall_hits::total       236636536                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        82647                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         82647                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        82647                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          82647                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        82647                       # number of overall misses
-system.cpu.icache.overall_misses::total         82647                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1564864673                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1564864673                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1564864673                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1564864673                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1564864673                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1564864673                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    236719183                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    236719183                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    236719183                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    236719183                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    236719183                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    236719183                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000349                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000349                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000349                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000349                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000349                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000349                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18934.319128                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18934.319128                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18934.319128                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18934.319128                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18934.319128                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18934.319128                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       190768                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           95                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              6939                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    27.492146                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    23.750000                       # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses         473597840                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        473597840                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    236680067                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       236680067                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     236680067                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        236680067                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    236680067                       # number of overall hits
+system.cpu.icache.overall_hits::total       236680067                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        81831                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         81831                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        81831                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          81831                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        81831                       # number of overall misses
+system.cpu.icache.overall_misses::total         81831                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1321953198                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1321953198                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1321953198                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1321953198                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1321953198                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1321953198                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    236761898                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    236761898                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    236761898                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    236761898                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    236761898                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    236761898                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000346                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000346                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000346                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000346                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000346                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000346                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16154.674854                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16154.674854                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16154.674854                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16154.674854                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16154.674854                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16154.674854                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       160057                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          121                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              6454                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    24.799659                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    24.200000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8650                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         8650                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         8650                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         8650                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         8650                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         8650                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        73997                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        73997                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        73997                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        73997                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        73997                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        73997                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1275745779                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1275745779                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1275745779                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1275745779                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1275745779                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1275745779                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks        73505                       # number of writebacks
+system.cpu.icache.writebacks::total             73505                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7785                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         7785                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         7785                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         7785                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         7785                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         7785                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        74046                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        74046                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        74046                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        74046                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        74046                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        74046                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1096634301                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1096634301                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1096634301                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1096634301                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1096634301                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1096634301                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000313                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000313                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000313                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17240.506764                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17240.506764                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17240.506764                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17240.506764                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17240.506764                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17240.506764                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14810.176120                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14810.176120                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14810.176120                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14810.176120                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14810.176120                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14810.176120                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      8512194                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      8513359                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          195                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      8513868                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      8515266                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          405                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage       743225                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           400641                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15417.686844                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5068283                       # Total number of references to valid blocks.
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-system.cpu.l2cache.tags.warmup_cycle      34590463000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  8465.103002                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   476.521367                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.927429                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         93194547                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        93194547                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2352880                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2352880                       # number of Writeback hits
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    502200000                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  11114003000                       # number of ReadSharedReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data  11616203000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data  11616203000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12403339500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2352880                       # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           24                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.041667                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009842                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.144534                       # miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.data     0.052770                       # miss rate for overall accesses
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97761.339303                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97761.339303                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73626.087363                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73626.087363                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77315.341324                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77315.341324                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73626.087363                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78020.787717                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77726.360942                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73626.087363                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78020.787717                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77726.360942                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.109358                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.069066                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.069066                       # miss rate for ReadSharedReq accesses
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  2482.142857                       # average UpgradeReq miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72617.926859                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72617.926859                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76139.633881                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76139.633881                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72617.926859                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76732.877214                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76539.249940                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72617.926859                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76732.877214                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76539.249940                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1072,159 +1087,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       292231                       # number of writebacks
-system.cpu.l2cache.writebacks::total           292231                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1476                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1476                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            8                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4058                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4058                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         5534                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         5542                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         5534                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         5542                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         6918                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         6918                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       275358                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       275358                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3661                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3661                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10683                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10683                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       139691                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       139691                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10683                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143352                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       154035                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10683                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143352                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       275358                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       429393                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  19097746561                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  19097746561                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        17500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        17500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    337925500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    337925500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    722686500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    722686500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   9966004000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   9966004000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    722686500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10303929500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11026616000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    722686500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10303929500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  19097746561                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  30124362561                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.writebacks::writebacks       292667                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292667                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1428                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1428                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            7                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4193                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4193                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            7                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         5621                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         5628                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            7                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         5621                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         5628                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       350851                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       350851                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           28                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           28                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3690                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3690                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8087                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8087                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       154608                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       154608                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         8087                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158298                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166385                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         8087                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158298                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       350851                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       517236                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18662693863                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18662693863                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       481000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       481000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    335947000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    335947000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    538896500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    538896500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  10864639500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  10864639500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    538896500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11200586500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11739483000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    538896500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11200586500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18662693863                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  30402176863                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.041667                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.041667                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007014                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007014                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.144425                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.144425                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.060750                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.060750                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.144425                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.050809                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.053201                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.144425                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.050809                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007070                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007070                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.109263                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.109263                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.067242                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.067242                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.109263                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056109                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.057468                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.109263                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056109                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.148304                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69356.062148                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        17500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        17500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92304.151871                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92304.151871                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67648.272957                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67648.272957                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71343.207508                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71343.207508                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67648.272957                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71878.519309                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71585.133249                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67648.272957                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71878.519309                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70155.690850                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.178650                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5789744                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2894372                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23770                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        30234                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        30144                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           90                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       2373438                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2645111                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       626124                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       317103                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           24                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           24                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       521946                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       521946                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        73997                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2299442                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       220575                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8440808                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8661383                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4733952                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    331153152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          335887104                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      717772                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      6507488                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.011967                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.108866                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      5789543                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2894272                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23735                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       260412                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       244232                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        16180                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       2373325                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2649267                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       513929                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       265680                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       392283                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           28                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           28                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       521957                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       521957                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        74046                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2299281                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       220710                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8440410                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8661120                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9386496                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    359623424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          369009920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      950663                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3845942                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.078099                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.283574                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            6429701     98.80%     98.80% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              77697      1.19%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                 90      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3561756     92.61%     92.61% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             268006      6.97%     99.58% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              16180      0.42%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        6507488                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5247752000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     111080826                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3845942                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5789002505                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy         1506                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     111143345                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4232108471                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4231890461                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             408044                       # Transaction distribution
-system.membus.trans_dist::Writeback            292231                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           102781                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3660                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3660                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        408044                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1218424                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1218424                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45051840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                45051840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             420198                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       292667                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            98618                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               33                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              33                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3685                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3685                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        420199                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1239118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1239118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45859200                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                45859200                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            806718                       # Request fanout histogram
+system.membus.snoop_fanout::samples            815202                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  806718    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  815202    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              806718                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2171550377                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              815202                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2212929834                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2176359308                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2242544064                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index ad7524f92..d23424e24 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.707537                       # Number of seconds simulated
-sim_ticks                                707536959500                       # Number of ticks simulated
-final_tick                               707536959500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.708526                       # Number of seconds simulated
+sim_ticks                                708526400500                       # Number of ticks simulated
+final_tick                               708526400500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1064510                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1152817                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1491485099                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 319084                       # Number of bytes of host memory used
-host_seconds                                   474.38                       # Real time elapsed on the host
+host_inst_rate                                 974268                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1055088                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1366955379                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319428                       # Number of bytes of host memory used
+host_seconds                                   518.32                       # Real time elapsed on the host
 sim_insts                                   504986854                       # Number of instructions simulated
 sim_ops                                     546878105                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            175360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8946752                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9122112                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       175360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          175360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6146048                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6146048                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2740                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             139793                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                142533                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           96032                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                96032                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               247846                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12644925                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                12892771                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          247846                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             247846                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           8686540                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                8686540                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           8686540                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              247846                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12644925                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               21579311                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            147392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8963904                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9111296                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       147392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          147392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6165120                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6165120                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2303                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             140061                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                142364                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           96330                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                96330                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               208026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12651475                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                12859501                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          208026                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             208026                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8701327                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8701327                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8701327                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              208026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12651475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               21560828                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -154,7 +154,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                       1415073919                       # number of cpu cycles simulated
+system.cpu.numCycles                       1417052801                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   504986854                       # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs                     172745235                       # nu
 system.cpu.num_load_insts                   115884756                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               1415073918.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               1417052800.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         121548302                       # Number of branches fetched
@@ -215,14 +215,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  548695379                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           1134822                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4065.318106                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4065.260615                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           170180456                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           1138918                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            149.422922                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       11716435500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4065.318106                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992509                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992509                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle       11750119500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4065.260615                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992495                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992495                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
@@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data      1138917                       # n
 system.cpu.dcache.demand_misses::total        1138917                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11820971000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11820971000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8866220000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8866220000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  20687191000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  20687191000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  20687191000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  20687191000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12104797500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12104797500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9574077500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9574077500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  21678875000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  21678875000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  21678875000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  21678875000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    114100415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    114100415                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
@@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.006766
 system.cpu.dcache.demand_miss_rate::total     0.006766                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.006765                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.006765                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18163.914491                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18163.898542                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15466.286636                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15466.286636                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26873.849155                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26873.849155                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19034.639925                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19034.639925                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19034.623213                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19034.623213                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1064880                       # number of writebacks
-system.cpu.dcache.writebacks::total           1064880                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1064678                       # number of writebacks
+system.cpu.dcache.writebacks::total           1064678                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782657                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       782657                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356260                       # number of WriteReq MSHR misses
@@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1138917
 system.cpu.dcache.demand_mshr_misses::total      1138917                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11038314000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  11038314000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8509960000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8509960000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        54000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        54000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19548274000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  19548274000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19548328000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  19548328000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11322140500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  11322140500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9217817500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9217817500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        61000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        61000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20539958000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  20539958000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20540019000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  20540019000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
@@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006766
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006766                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006765                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006765                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.286636                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.286636                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25873.849155                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25873.849155                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        61000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        61000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18034.639925                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18034.639925                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18034.677650                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18034.677650                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9788                       # number of replacements
-system.cpu.icache.tags.tagsinuse           983.371232                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           983.180611                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           516599856                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             11521                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          44839.845152                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   983.371232                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.480162                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.480162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   983.180611                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.480069                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.480069                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1733                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
@@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst        11521                       # n
 system.cpu.icache.demand_misses::total          11521                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        11521                       # number of overall misses
 system.cpu.icache.overall_misses::total         11521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    265444000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    265444000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    265444000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    265444000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    265444000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    265444000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    263208000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    263208000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    263208000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    263208000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    263208000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    263208000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    516611377                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    516611377                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    516611377                       # number of demand (read+write) accesses
@@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000022
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23040.013888                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23040.013888                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22845.933513                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22845.933513                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22845.933513                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22845.933513                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22845.933513                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22845.933513                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -409,92 +409,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks         9788                       # number of writebacks
+system.cpu.icache.writebacks::total              9788                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11521                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        11521                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        11521                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total        11521                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        11521                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        11521                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    253923000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    253923000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    253923000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    253923000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    253923000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    253923000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    251687000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    251687000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    251687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    251687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    251687000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    251687000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21845.933513                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21845.933513                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21845.933513                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21845.933513                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21845.933513                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21845.933513                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           109779                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27249.077163                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1743796                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           140956                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.371208                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     338494154000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   287.705462                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3616.365578                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.712433                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008780                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.110363                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.831576                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31177                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           110394                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        27250.637055                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1744409                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           141582                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.320839                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     339114860000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23374.350264                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   240.190674                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3636.096117                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.713329                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007330                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.110965                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.831623                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31188                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3657                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27180                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951447                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18829920                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18829920                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      1064880                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1064880                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       255527                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       255527                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8781                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         8781                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       743598                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       743598                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8781                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       999125                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1007906                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8781                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       999125                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1007906                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       100733                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       100733                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2740                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2740                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        39060                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        39060                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2740                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       139793                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        142533                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2740                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       139793                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       142533                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5292536500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5292536500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    144147000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    144147000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2053419500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2053419500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    144147000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   7345956000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   7490103000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    144147000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   7345956000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   7490103000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      1064880                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1064880                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27176                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951782                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18830546                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18830546                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      1064678                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      1064678                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         9751                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         9751                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       255472                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       255472                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         9218                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         9218                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       743385                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       743385                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         9218                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       998857                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1008075                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         9218                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       998857                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1008075                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       100788                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       100788                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2303                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2303                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        39273                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        39273                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2303                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       140061                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        142364                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2303                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       140061                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       142364                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6000938500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   6000938500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    137230000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    137230000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2339453000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2339453000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    137230000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   8340391500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   8477621500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    137230000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   8340391500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   8477621500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      1064678                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      1064678                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         9751                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         9751                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       356260                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       356260                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11521                       # number of ReadCleanReq accesses(hits+misses)
@@ -507,30 +513,30 @@ system.cpu.l2cache.demand_accesses::total      1150439                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst        11521                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1138918                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      1150439                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282751                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.282751                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.237827                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.237827                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.049907                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.049907                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.237827                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.122742                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.123894                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.237827                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.122742                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123894                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282906                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.282906                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.199896                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.199896                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050179                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050179                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.199896                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.122977                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123748                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.199896                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.122977                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.123748                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.208160                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.208160                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59587.494572                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59587.494572                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59568.991419                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59568.991419                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59587.494572                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.278964                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59548.913349                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59587.494572                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.278964                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59548.913349                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -539,70 +545,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        96032                       # number of writebacks
-system.cpu.l2cache.writebacks::total            96032                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          792                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          792                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100733                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       100733                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2740                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2740                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        39060                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        39060                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2740                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       139793                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       142533                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2740                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       139793                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       142533                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4285206500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4285206500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    116747000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    116747000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1662819500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1662819500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    116747000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5948026000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   6064773000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    116747000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5948026000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   6064773000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks        96330                       # number of writebacks
+system.cpu.l2cache.writebacks::total            96330                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100788                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       100788                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2303                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2303                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        39273                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        39273                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2303                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       140061                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       142364                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2303                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       140061                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       142364                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4993058500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4993058500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    114200000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    114200000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1946723000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1946723000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    114200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6939781500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   7053981500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    114200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6939781500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   7053981500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282751                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282751                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.237827                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.237827                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.049907                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.049907                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.237827                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122742                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123894                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.237827                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122742                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123894                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282906                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282906                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.199896                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.199896                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050179                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050179                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.199896                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.122977                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123748                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.199896                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.122977                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123748                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.208160                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.208160                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49587.494572                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49587.494572                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49568.991419                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49568.991419                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49587.494572                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.278964                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.913349                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49587.494572                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.278964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.913349                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      2295049                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      1144662                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3461                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2140                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2139                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2146                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2145                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        794179                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1160912                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        90016                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1161008                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         9751                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        80784                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       356260                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       356260                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq        11521                       # Transaction distribution
@@ -610,51 +617,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq       782658
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32793                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3409234                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           3442027                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       737344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141043072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          141780416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      109779                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2404828                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.003790                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.061455                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1361408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141030144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          142391552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      110394                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1260833                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.004489                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.066862                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2395714     99.62%     99.62% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               9113      0.38%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1255174     99.55%     99.55% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               5658      0.45%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2404828                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2212404500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1260833                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2221990500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      17281500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1708377000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              41800                       # Transaction distribution
-system.membus.trans_dist::Writeback             96032                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            12399                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100733                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100733                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         41800                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393497                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 393497                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15268160                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15268160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              41576                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        96330                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            11920                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100788                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100788                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         41576                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       392978                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 392978                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15276416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15276416                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            251058                       # Request fanout histogram
+system.membus.snoop_fanout::samples            250615                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  251058    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  250615    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              251058                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           643796492                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              250615                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           644475328                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          719009164                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          711820000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 987362254..e3c4d5903 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.403931                       # Number of seconds simulated
-sim_ticks                                403931323500                       # Number of ticks simulated
-final_tick                               403931323500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.403830                       # Number of seconds simulated
+sim_ticks                                403830091000                       # Number of ticks simulated
+final_tick                               403830091000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95186                       # Simulator instruction rate (inst/s)
-host_op_rate                                   176009                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               46498470                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 433064                       # Number of bytes of host memory used
-host_seconds                                  8686.98                       # Real time elapsed on the host
+host_inst_rate                                  95719                       # Simulator instruction rate (inst/s)
+host_op_rate                                   176996                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46747318                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 431916                       # Number of bytes of host memory used
+host_seconds                                  8638.57                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            217984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24500544                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24718528                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       217984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          217984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18869632                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18869632                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             382821                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                386227                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          294838                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               294838                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               539656                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             60655222                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                61194878                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          539656                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             539656                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          46714951                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               46714951                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          46714951                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              539656                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            60655222                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              107909829                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        386228                       # Number of read requests accepted
-system.physmem.writeReqs                       294838                       # Number of write requests accepted
-system.physmem.readBursts                      386228                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     294838                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24699456                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19136                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18868032                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24718592                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18869632                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      299                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            163776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24545280                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24709056                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       163776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          163776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18890432                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18890432                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2559                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             383520                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                386079                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          295163                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               295163                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               405557                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             60781206                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                61186763                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          405557                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             405557                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          46778168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               46778168                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          46778168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              405557                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            60781206                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              107964931                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        386079                       # Number of read requests accepted
+system.physmem.writeReqs                       295163                       # Number of write requests accepted
+system.physmem.readBursts                      386079                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     295163                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24689408                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19648                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18889088                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24709056                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18890432                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      307                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         196128                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24062                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26430                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24903                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24577                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23181                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23704                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24550                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24303                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23663                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23568                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24789                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              23975                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23330                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22932                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              24089                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23873                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18604                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19922                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               19191                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18985                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18090                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18485                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               19138                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               19082                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18642                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17946                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18887                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17737                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17398                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16988                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17875                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17843                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         251728                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               24087                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26440                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24835                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24498                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23219                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23721                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24501                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24288                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23633                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23532                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24814                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              23996                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23302                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22925                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              24085                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23896                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18615                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19935                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               19196                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               19026                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18118                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18514                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               19142                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               19086                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18651                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17953                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18925                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17775                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17401                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              17016                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17907                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17882                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    403931308500                       # Total gap between requests
+system.physmem.totGap                    403830049500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  386228                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  386079                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 294838                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    380968                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4611                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       308                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 295163                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    380933                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4500                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       294                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        35                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17606                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17646                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17722                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17675                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17751                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17865                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17590                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17527                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17650                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17664                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17709                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17701                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17758                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17614                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
@@ -193,248 +193,248 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       146866                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      296.637860                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     175.325639                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.046473                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54140     36.86%     36.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        39981     27.22%     64.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13765      9.37%     73.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7667      5.22%     78.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5371      3.66%     82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3914      2.67%     85.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3025      2.06%     87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2731      1.86%     88.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16272     11.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         146866                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17494                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.060078                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      218.173610                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17485     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            4      0.02%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            3      0.02%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       146827                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      296.793805                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     175.429172                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     322.898216                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          54192     36.91%     36.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        39812     27.11%     64.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13750      9.36%     73.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7660      5.22%     78.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5440      3.71%     82.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4000      2.72%     85.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3009      2.05%     87.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2793      1.90%     88.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16171     11.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         146827                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17508                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.033813                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      216.830406                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17497     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            6      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::7168-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17494                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17494                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.852235                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.776145                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.682764                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17296     98.87%     98.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             143      0.82%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              28      0.16%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               5      0.03%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               3      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               3      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               1      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               3      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           17508                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17508                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.857551                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.779124                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.831180                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17335     99.01%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             121      0.69%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              25      0.14%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               8      0.05%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               2      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               2      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               2      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::108-111             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::216-219             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17494                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4291077750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11527246500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1929645000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11118.83                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           17508                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4276128000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11509353000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1928860000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11084.60                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29868.83                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          61.15                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          46.71                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       61.20                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       46.71                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29834.60                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          61.14                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          46.77                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       61.19                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       46.78                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.84                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.48                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      0.37                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     317989                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215873                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.40                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.22                       # Row buffer hit rate for writes
-system.physmem.avgGap                       593086.88                       # Average gap between requests
-system.physmem.pageHitRate                      78.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  567438480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  309614250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1526405400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                981499680                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26382567120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            62258546970                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           187743770250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             279769842150                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.623817                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   311776883750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13488020000                       # Time in different power states
+system.physmem.avgWrQLen                        21.79                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     318168                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215906                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.15                       # Row buffer hit rate for writes
+system.physmem.avgGap                       592785.02                       # Average gap between requests
+system.physmem.pageHitRate                      78.43                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  567876960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  309853500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1525477200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                982432800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            26375955840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            62051510430                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           187864648500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             279677755230                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.569390                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   311979208000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13484640000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     78662661250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     78362495750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  542467800                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  295989375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1483341600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                928473840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26382567120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            60448758210                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           189331310250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             279412908195                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              691.740141                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   314432491250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13488020000                       # Time in different power states
+system.physmem_1.actEnergy                  541779840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  295614000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1483021800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                929672640                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26375955840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            60320910060                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           189382719000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             279329673180                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              691.707431                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   314516116250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13484640000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     76007072500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     75825587500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               219314839                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         219314839                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           8530231                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            123981217                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               121825604                       # Number of BTB hits
+system.cpu.branchPred.lookups               219264229                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         219264229                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           8531047                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            124002696                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               121802201                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.261339                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                27068206                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1407908                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.225446                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                27063113                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1406921                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        807862648                       # number of cpu cycles simulated
+system.cpu.numCycles                        807660183                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          175941692                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1208657835                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   219314839                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          148893810                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     622000001                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                17769177                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        227                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                92380                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        735169                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles         1433                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 170789403                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2323822                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       4                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          807655519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.784658                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.367182                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          175911242                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1208663462                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   219264229                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          148865314                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     621862787                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                17775835                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        233                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                94904                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        745978                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles         1264                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           17                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 170762091                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2319100                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       3                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          807504342                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.785127                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.367664                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                417598750     51.71%     51.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 32531773      4.03%     55.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 31857083      3.94%     59.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 32716073      4.05%     63.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 26594170      3.29%     67.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 26933309      3.33%     70.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 35181908      4.36%     74.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 31423846      3.89%     78.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                172818607     21.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                417532473     51.71%     51.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 32497368      4.02%     55.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31891068      3.95%     59.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 32657877      4.04%     63.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 26554759      3.29%     67.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 26902865      3.33%     70.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 35168137      4.36%     74.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 31391832      3.89%     78.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                172907963     21.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            807655519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.271475                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.496118                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                120412218                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             371076736                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 225209960                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              82072017                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                8884588                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2132095724                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                8884588                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                152556291                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               150817488                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          41958                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 271423783                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             223931411                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2088526658                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                137354                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              138380994                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               24891978                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               50561951                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2190720490                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5278322969                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3357144423                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             60320                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            807504342                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.271481                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.496500                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                120449956                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             370877919                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 225251519                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              82037031                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                8887917                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2132109647                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                8887917                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                152555499                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               150771591                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          44475                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 271462113                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             223782747                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2088438662                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                138448                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              138151621                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               24868058                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               50731794                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2190645258                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5278038161                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3357041251                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             59967                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                576679636                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               3187                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2956                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 423114583                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            507122992                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           200812983                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         229080264                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         68423458                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2023133283                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               22942                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1788928106                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            421261                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       494167524                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    833180412                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          22390                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     807655519                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.214964                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.070282                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                576604404                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               3331                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           3057                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 422478077                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            507119798                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           200816388                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         229077730                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         68200212                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2023068034                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22911                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1788999576                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            413303                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       494102244                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    832764755                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          22359                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     807504342                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.215467                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.071001                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           238829466     29.57%     29.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           123732265     15.32%     44.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           119115162     14.75%     59.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           107661207     13.33%     72.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            89581047     11.09%     84.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            60232277      7.46%     91.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            42307619      5.24%     96.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            18921199      2.34%     99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             7275277      0.90%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           238908265     29.59%     29.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           123628552     15.31%     44.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           118817632     14.71%     59.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           107769877     13.35%     72.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            89573603     11.09%     84.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            60241832      7.46%     91.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            42310466      5.24%     96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            18973159      2.35%     99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             7280956      0.90%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       807655519                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       807504342                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                11512552     42.68%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               12355843     45.81%     88.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3105832     11.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                11498712     42.77%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               12295029     45.73%     88.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3093590     11.51%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2718297      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1183078959     66.13%     66.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               370517      0.02%     66.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3881151      0.22%     66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 134      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2718967      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1183065523     66.13%     66.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               369413      0.02%     66.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3881231      0.22%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 133      0.00%     66.52% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.52% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 67      0.00%     66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                 365      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 60      0.00%     66.52% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                 380      0.00%     66.52% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.52% # Type of FU issued
@@ -456,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.52% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            428492741     23.95%     90.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170385875      9.52%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            428545273     23.95%     90.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170418596      9.53%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1788928106                       # Type of FU issued
-system.cpu.iq.rate                           2.214396                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    26974227                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.015078                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4412876800                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2517572556                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1762303286                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               30419                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              69720                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         5693                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1813170766                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   13270                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        186079397                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1788999576                       # Type of FU issued
+system.cpu.iq.rate                           2.215040                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    26887331                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.015029                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4412774566                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2517442986                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1762358918                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               29562                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              69250                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         5611                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1813154984                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12956                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        186087729                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    123023075                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       212257                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       371984                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     51652797                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    123020037                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       213128                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       372787                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     51656202                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        22860                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1101                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        22930                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1078                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                8884588                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                97906785                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6199562                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2023156225                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            370486                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             507125232                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            200812983                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               7241                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1822287                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3474512                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         371984                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4845065                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4137242                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8982307                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1769932780                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             423113153                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          18995326                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                8887917                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                97798502                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6162253                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2023090945                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            375323                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             507122194                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            200816388                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               7129                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1832886                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3426694                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         372787                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4845812                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4140641                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8986453                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1769991187                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             423150453                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          19008389                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    590301691                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                168980249                       # Number of branches executed
-system.cpu.iew.exec_stores                  167188538                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.190883                       # Inst execution rate
-system.cpu.iew.wb_sent                     1766804374                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1762308979                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1339663552                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2049989844                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    590375275                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                168976940                       # Number of branches executed
+system.cpu.iew.exec_stores                  167224822                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.191505                       # Inst execution rate
+system.cpu.iew.wb_sent                     1766866321                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1762364529                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1339720871                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2049946578                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.181446                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.653498                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.182062                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.653539                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       494228972                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       494164798                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8612841                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    740434686                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.064988                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.575030                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           8615583                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    740300612                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.065362                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.575682                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    276267324     37.31%     37.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    172135150     23.25%     60.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     56000087      7.56%     68.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     86333753     11.66%     79.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     25859703      3.49%     83.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     26527369      3.58%     86.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9854605      1.33%     88.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      9004729      1.22%     89.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     78451966     10.60%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    276280439     37.32%     37.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    172026383     23.24%     60.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     56011691      7.57%     68.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     86227626     11.65%     79.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     25892196      3.50%     83.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26512378      3.58%     86.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9839162      1.33%     88.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8995484      1.22%     89.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     78515253     10.61%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    740434686                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    740300612                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -579,344 +579,350 @@ system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              78451966                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2685200393                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4113829657                       # The number of ROB writes
-system.cpu.timesIdled                            2326                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          207129                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              78515253                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2684938858                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4113685431                       # The number of ROB writes
+system.cpu.timesIdled                            1962                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          155841                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.977004                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.977004                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.023537                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.023537                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2722489562                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1435790744                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      5969                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      521                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 596647275                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                405463698                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               971582048                       # number of misc regfile reads
+system.cpu.cpi                               0.976760                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.976760                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.023793                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.023793                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2722687854                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1435809850                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      5827                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      561                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 596681162                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                405470892                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               971641846                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2530897                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.817920                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           381840179                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2534993                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.627705                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2530997                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.815869                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           381868965                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2535093                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            150.633119                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1673396500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.817920                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.815869                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.998002                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.998002                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          865                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3173                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3178                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         772772413                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        772772413                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    233184165                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       233184165                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148172813                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148172813                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     381356978                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        381356978                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    381356978                       # number of overall hits
-system.cpu.dcache.overall_hits::total       381356978                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2774343                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2774343                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       987389                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       987389                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3761732                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3761732                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3761732                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3761732                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  59119368500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  59119368500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  31296279995                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  31296279995                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  90415648495                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  90415648495                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  90415648495                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  90415648495                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    235958508                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    235958508                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         772828805                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        772828805                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    233213748                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       233213748                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148173817                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148173817                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     381387565                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        381387565                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    381387565                       # number of overall hits
+system.cpu.dcache.overall_hits::total       381387565                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2772906                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2772906                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       986385                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       986385                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3759291                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3759291                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3759291                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3759291                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  59174415500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  59174415500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  31292251995                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  31292251995                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  90466667495                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  90466667495                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  90466667495                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  90466667495                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    235986654                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    235986654                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    385118710                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    385118710                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    385118710                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    385118710                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011758                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011758                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006620                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006620                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009768                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009768                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009768                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009768                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24035.643287                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24035.643287                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        10106                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           15                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1086                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.305709                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    385146856                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    385146856                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    385146856                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    385146856                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011750                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011750                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006613                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006613                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009761                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009761                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009761                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009761                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21340.216906                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21340.216906                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31724.176660                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31724.176660                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24064.821663                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24064.821663                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24064.821663                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24064.821663                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         9788                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            9                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1047                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.348615                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets            9                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2330787                       # number of writebacks
-system.cpu.dcache.writebacks::total           2330787                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1009448                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1009448                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19379                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        19379                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1028827                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1028827                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1028827                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1028827                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764895                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764895                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       968010                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       968010                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2732905                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2732905                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2732905                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2732905                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33550858500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33550858500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  30073647496                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  30073647496                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63624505996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  63624505996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63624505996                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  63624505996                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007480                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007480                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006490                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006490                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007096                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.007096                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007096                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.007096                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2330532                       # number of writebacks
+system.cpu.dcache.writebacks::total           2330532                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1007920                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1007920                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19403                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        19403                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1027323                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1027323                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1027323                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1027323                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764986                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764986                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       966982                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       966982                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2731968                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2731968                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2731968                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2731968                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33558631000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33558631000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  30070164497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  30070164497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63628795497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  63628795497                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63628795497                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  63628795497                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007479                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007479                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006483                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006483                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007093                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.007093                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007093                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.007093                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19013.539484                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19013.539484                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31096.922690                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31096.922690                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23290.461490                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23290.461490                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23290.461490                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23290.461490                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              6655                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1037.678215                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           170577740                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              8265                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          20638.565033                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              6653                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1037.717066                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           170551460                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8264                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          20637.882381                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1037.678215                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.506679                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.506679                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1610                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          326                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1153                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.786133                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         341785100                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        341785100                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    170580521                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       170580521                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     170580521                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        170580521                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    170580521                       # number of overall hits
-system.cpu.icache.overall_hits::total       170580521                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       208882                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        208882                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       208882                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         208882                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       208882                       # number of overall misses
-system.cpu.icache.overall_misses::total        208882                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1312211500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1312211500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1312211500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1312211500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1312211500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1312211500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    170789403                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    170789403                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    170789403                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    170789403                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    170789403                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    170789403                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001223                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001223                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001223                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001223                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001223                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001223                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6282.070739                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6282.070739                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6282.070739                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6282.070739                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6282.070739                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6282.070739                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          889                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1037.717066                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.506698                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.506698                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1611                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          321                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1160                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.786621                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         341729418                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        341729418                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    170554639                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       170554639                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     170554639                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        170554639                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    170554639                       # number of overall hits
+system.cpu.icache.overall_hits::total       170554639                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       207451                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        207451                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       207451                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         207451                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       207451                       # number of overall misses
+system.cpu.icache.overall_misses::total        207451                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1211820000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1211820000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1211820000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1211820000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1211820000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1211820000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    170762090                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    170762090                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    170762090                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    170762090                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    170762090                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    170762090                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001215                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001215                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001215                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001215                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001215                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001215                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  5841.475818                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  5841.475818                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  5841.475818                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  5841.475818                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  5841.475818                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  5841.475818                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          674                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    74.083333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    74.888889                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2585                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2585                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2585                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2585                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2585                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2585                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       206297                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       206297                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       206297                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       206297                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       206297                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       206297                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    989635000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    989635000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    989635000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    989635000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    989635000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    989635000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001208                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001208                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001208                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001208                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001208                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001208                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4797.137137                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4797.137137                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4797.137137                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  4797.137137                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4797.137137                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  4797.137137                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         6653                       # number of writebacks
+system.cpu.icache.writebacks::total              6653                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2211                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2211                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2211                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2211                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2211                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2211                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       205240                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       205240                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       205240                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       205240                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       205240                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       205240                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    926829000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    926829000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    926829000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    926829000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    926829000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    926829000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001202                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001202                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001202                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001202                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001202                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001202                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4515.830248                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4515.830248                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4515.830248                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  4515.830248                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4515.830248                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  4515.830248                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           353544                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29619.458392                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3891749                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           385874                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.085543                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     189343942500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   242.518808                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8435.398201                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.639085                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007401                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.257428                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.903914                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32330                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13379                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18648                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.986633                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43295860                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43295860                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2330787                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2330787                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1834                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1834                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       563915                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       563915                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4843                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         4843                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1588207                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1588207                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         4843                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2152122                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2156965                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         4843                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2152122                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2156965                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       196078                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       196078                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206573                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206573                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3410                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3410                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176298                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       176298                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3410                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       382871                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        386281                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3410                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       382871                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       386281                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13890000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     13890000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16378927500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16378927500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    280136500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    280136500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14178823000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  14178823000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    280136500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30557750500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30837887000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    280136500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30557750500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30837887000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2330787                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2330787                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       197912                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       197912                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       770488                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       770488                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8253                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         8253                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1764505                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1764505                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         8253                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2534993                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2543246                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         8253                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2534993                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2543246                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990733                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990733                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268107                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.268107                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.413183                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.413183                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099914                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099914                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.413183                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.151034                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151885                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.413183                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.151034                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151885                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    70.839156                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    70.839156                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79288.810735                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79288.810735                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82151.466276                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82151.466276                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80425.319629                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80425.319629                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82151.466276                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79812.131240                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79832.782353                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82151.466276                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79812.131240                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79832.782353                       # average overall miss latency
+system.cpu.l2cache.tags.replacements           355338                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29622.648539                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3892669                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           387670                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.041192                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     189329679500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21024.249099                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   186.226961                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8412.172479                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.641609                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32332                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          225                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13400                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18619                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.986694                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         43294553                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        43294553                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2330532                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2330532                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         6263                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         6263                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1839                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1839                       # number of UpgradeReq hits
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+system.cpu.l2cache.ReadCleanReq_hits::total         5677                       # number of ReadCleanReq hits
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+system.cpu.l2cache.ReadSharedReq_hits::total      1587956                       # number of ReadSharedReq hits
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+system.cpu.l2cache.overall_hits::total        2157201                       # number of overall hits
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+system.cpu.l2cache.overall_misses::cpu.data       383569                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       386130                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13989000                       # number of UpgradeReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16413605500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16413605500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    209990000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    209990000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14188998500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  14188998500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    209990000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30602604000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30812594000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    209990000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30602604000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30812594000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2330532                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2330532                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         6263                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         6263                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       196875                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       196875                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       770497                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       770497                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8238                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         8238                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1764596                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1764596                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         8238                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2535093                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2543331                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         8238                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2535093                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2543331                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990659                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990659                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268566                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.268566                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.310876                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.310876                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.100102                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.100102                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.310876                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.151304                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151821                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.310876                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.151304                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151821                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    71.725220                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    71.725220                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79319.986565                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79319.986565                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81995.314330                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81995.314330                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80327.210711                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80327.210711                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81995.314330                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79783.830289                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79798.497915                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81995.314330                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79783.830289                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79798.497915                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -925,142 +931,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       294838                       # number of writebacks
-system.cpu.l2cache.writebacks::total           294838                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            2                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1958                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1958                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       196078                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       196078                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206573                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206573                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3408                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3408                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176298                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176298                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3408                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       382871                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       386279                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3408                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       382871                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       386279                       # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   4323708271                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   4323708271                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14313197500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14313197500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    245909500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    245909500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12415843000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12415843000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    245909500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26729040500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  26974950000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    245909500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26729040500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26974950000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks       295163                       # number of writebacks
+system.cpu.l2cache.writebacks::total           295163                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            8                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            8                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       195036                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       195036                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206929                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206929                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2560                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2560                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176640                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176640                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2560                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       383569                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       386129                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2560                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       383569                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       386129                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   4301153024                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   4301153024                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14344315500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14344315500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    184333500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    184333500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12422598500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12422598500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    184333500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26766914000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  26951247500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    184333500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26766914000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  26951247500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990733                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990733                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268107                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268107                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.412941                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.412941                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099914                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099914                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.412941                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151034                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151884                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.412941                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151034                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151884                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990659                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990659                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268566                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268566                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.310755                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.310755                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.100102                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.100102                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.310755                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151304                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151820                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.310755                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151304                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151820                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22053.123649                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22053.123649                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69319.986565                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69319.986565                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72005.273438                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72005.273438                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70327.210711                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70327.210711                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72005.273438                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69783.830289                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69798.558254                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72005.273438                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69783.830289                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69798.558254                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5476754                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2732107                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       213805                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3607                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3607                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5474858                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2731062                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       212394                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         3599                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3599                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       1970799                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2625625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       253914                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       197912                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       197912                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       770488                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       770488                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       206297                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1764505                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       220789                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7985563                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8206352                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       528000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311409920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          311937920                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      551588                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5830298                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.072755                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.259734                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1969834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2625695                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         6263                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       249937                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       196875                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       196875                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       770497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       770497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       205240                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1764596                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       219739                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7984230                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8203969                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       927936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311400000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312327936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      552340                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3292546                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.124310                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.329935                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5406114     92.72%     92.72% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             424184      7.28%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2883249     87.57%     87.57% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             409297     12.43%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5830298                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5097760193                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3292546                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5102581952                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     309447487                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     307865483                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3901446077                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3901080066                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             179703                       # Transaction distribution
-system.membus.trans_dist::Writeback            294838                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            57117                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           196128                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          196128                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206523                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206523                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        179705                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1516665                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1516665                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1516665                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43588096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43588096                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43588096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             179198                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       295163                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            56643                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           195085                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          195085                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206880                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206880                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        179199                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1514133                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1514133                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1514133                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43599424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43599424                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43599424                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            934311                       # Request fanout histogram
+system.membus.snoop_fanout::samples            932970                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  934311    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  932970    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              934311                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2245481708                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              932970                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2244779968                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2435298904                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2432276830                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index 22535a108..1b9df2638 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.647861                       # Number of seconds simulated
-sim_ticks                                1647861059500                       # Number of ticks simulated
-final_tick                               1647861059500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.650527                       # Number of seconds simulated
+sim_ticks                                1650526667500                       # Number of ticks simulated
+final_tick                               1650526667500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 657040                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1214941                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1309397988                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 327616                       # Number of bytes of host memory used
-host_seconds                                  1258.49                       # Real time elapsed on the host
+host_inst_rate                                 726731                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1343807                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1450624585                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 327760                       # Number of bytes of host memory used
+host_seconds                                  1137.80                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            120384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24254848                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24375232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       120384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          120384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18763136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18763136                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1881                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             378982                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                380863                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293174                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293174                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                73055                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             14718989                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14792043                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           73055                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              73055                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          11386358                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               11386358                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          11386358                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               73055                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            14718989                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               26178401                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            115776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24258944                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24374720                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       115776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          115776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18765248                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18765248                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1809                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             379046                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                380855                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293207                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293207                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                70145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             14697699                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14767844                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           70145                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              70145                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          11369249                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               11369249                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          11369249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               70145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            14697699                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               26137092                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                       3295722119                       # number of cpu cycles simulated
+system.cpu.numCycles                       3301053335                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   826877110                       # Number of instructions committed
@@ -60,7 +60,7 @@ system.cpu.num_mem_refs                     533262343                       # nu
 system.cpu.num_load_insts                   384102157                       # Number of load instructions
 system.cpu.num_store_insts                  149160186                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               3295722118.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               3301053334.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         149758583                       # Number of branches fetched
@@ -100,14 +100,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1528988702                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           2514362                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4086.415711                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4086.386622                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           530743930                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           2518458                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            210.741624                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        8211725500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4086.415711                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997660                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997660                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle        8246025500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4086.386622                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997653                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997653                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
@@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data      2518458                       # n
 system.cpu.dcache.demand_misses::total        2518458                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      2518458                       # number of overall misses
 system.cpu.dcache.overall_misses::total       2518458                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  29707934500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  29707934500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18949311500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18949311500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  48657246000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  48657246000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  48657246000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  48657246000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  30918235500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  30918235500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  20395021500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20395021500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  51313257000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  51313257000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  51313257000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  51313257000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    384102186                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    384102186                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
@@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.004723
 system.cpu.dcache.demand_miss_rate::total     0.004723                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.004723                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.004723                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19320.253107                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19320.253107                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17898.567165                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17898.567165                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25782.410966                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 25782.410966                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20374.871052                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20374.871052                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20374.871052                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20374.871052                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2323227                       # number of writebacks
-system.cpu.dcache.writebacks::total           2323227                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      2323200                       # number of writebacks
+system.cpu.dcache.writebacks::total           2323200                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1727414                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      1727414                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       791044                       # number of WriteReq MSHR misses
@@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      2518458
 system.cpu.dcache.demand_mshr_misses::total      2518458                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      2518458                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      2518458                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27980520500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27980520500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18158267500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  18158267500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46138788000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  46138788000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46138788000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  46138788000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29190821500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  29190821500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19603977500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19603977500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  48794799000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  48794799000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  48794799000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  48794799000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004497                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004497                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005303                       # mshr miss rate for WriteReq accesses
@@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.004723
 system.cpu.dcache.demand_mshr_miss_rate::total     0.004723                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.004723                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16898.567165                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16898.567165                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24782.410966                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24782.410966                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19374.871052                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19374.871052                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19374.871052                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19374.871052                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1253                       # number of replacements
-system.cpu.icache.tags.tagsinuse           881.348726                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           881.361122                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1068344251                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              2814                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          379653.251955                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   881.348726                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.430346                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.430346                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   881.361122                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.430352                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.430352                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1561                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
@@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst         2814                       # n
 system.cpu.icache.demand_misses::total           2814                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         2814                       # number of overall misses
 system.cpu.icache.overall_misses::total          2814                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    115655000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    115655000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    115655000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    115655000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    115655000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    115655000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    125252000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    125252000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    125252000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    125252000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    125252000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    125252000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1068347065                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1068347065                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1068347065                       # number of demand (read+write) accesses
@@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000003
 system.cpu.icache.demand_miss_rate::total     0.000003                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 41099.857854                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 41099.857854                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44510.305615                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 44510.305615                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 44510.305615                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 44510.305615                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 44510.305615                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 44510.305615                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -270,92 +270,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks         1253                       # number of writebacks
+system.cpu.icache.writebacks::total              1253                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         2814                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         2814                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         2814                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         2814                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         2814                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    112841000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    112841000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    112841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    112841000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    112841000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    112841000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    122438000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    122438000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    122438000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    122438000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    122438000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    122438000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43510.305615                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43510.305615                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43510.305615                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 43510.305615                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43510.305615                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 43510.305615                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           348182                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29285.938694                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3846845                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           380537                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.108991                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     755943397500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   139.116925                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8218.320163                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.638687                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004246                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.250803                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.893736                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32355                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           348438                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29288.473875                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3847001                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           380798                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.102472                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     756996028500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 20940.344841                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.252047                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8216.876987                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.639049                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004005                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.250759                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.893813                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32360                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8220                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        24069                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987396                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41466677                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41466677                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      2323227                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2323227                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       584717                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       584717                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          933                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          933                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1554759                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1554759                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          933                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2139476                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2140409                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          933                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2139476                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2140409                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206327                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206327                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1881                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1881                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       172655                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       172655                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1881                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       378982                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        380863                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1881                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       378982                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       380863                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10832173000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10832173000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     98817000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     98817000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   9064428500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   9064428500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     98817000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  19896601500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  19995418500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     98817000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  19896601500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  19995418500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      2323227                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2323227                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        24060                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987549                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         41466938                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41466938                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2323200                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2323200                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         1253                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         1253                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       584688                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       584688                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1005                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         1005                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1554724                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1554724                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         1005                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2139412                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2140417                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1005                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2139412                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2140417                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206356                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206356                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1809                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         1809                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       172690                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       172690                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1809                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       379046                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        380855                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1809                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       379046                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       380855                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12278187500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  12278187500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    107652500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    107652500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  10275095500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  10275095500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    107652500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  22553283000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  22660935500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    107652500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  22553283000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  22660935500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2323200                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2323200                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         1253                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         1253                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       791044                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       791044                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         2814                       # number of ReadCleanReq accesses(hits+misses)
@@ -368,30 +374,30 @@ system.cpu.l2cache.demand_accesses::total      2521272                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst         2814                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      2518458                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      2521272                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.260829                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.260829                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.668443                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.668443                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099950                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099950                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.668443                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.150482                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151060                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.668443                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.150482                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151060                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.026657                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.026657                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52534.290271                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52534.290271                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.237468                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.237468                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52534.290271                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.122697                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.291443                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52534.290271                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.122697                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.291443                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.260865                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.260865                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.642857                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.642857                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099970                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099970                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.642857                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.150507                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151057                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.642857                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.150507                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151057                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.026653                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.026653                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59509.397457                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59509.397457                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59509.397457                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.121357                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59500.165417                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59509.397457                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.121357                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59500.165417                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -400,60 +406,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       293174                       # number of writebacks
-system.cpu.l2cache.writebacks::total           293174                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          275                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          275                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206327                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206327                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1881                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1881                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       172655                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       172655                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1881                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       378982                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       380863                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1881                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       378982                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       380863                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8768903000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8768903000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     80007000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     80007000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   7337878500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   7337878500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     80007000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16106781500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  16186788500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     80007000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16106781500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  16186788500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks       293208                       # number of writebacks
+system.cpu.l2cache.writebacks::total           293208                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            6                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            6                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206356                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206356                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1809                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1809                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       172690                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       172690                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1809                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       379046                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       380855                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1809                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       379046                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       380855                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10214627500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10214627500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     89562500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     89562500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   8548195500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   8548195500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     89562500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  18762823000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  18852385500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     89562500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  18762823000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  18852385500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.260829                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.260829                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.668443                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.668443                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099950                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099950                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.668443                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150482                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151060                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.668443                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150482                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151060                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.260865                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.260865                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.642857                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.642857                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099970                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099970                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.642857                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150507                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151057                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.642857                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150507                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151057                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.026653                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.026653                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49509.397457                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49509.397457                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49509.397457                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.121357                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.165417                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49509.397457                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.121357                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.165417                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5036887                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2515615                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -462,8 +468,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops         1729                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1729                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp       1730228                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2616401                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       247396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2616408                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         1253                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       246392                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       791044                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       791044                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         2814                       # Transaction distribution
@@ -471,53 +478,53 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq      1727414
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         6881                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7551278                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           7558159                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       180096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    309867840                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          310047936                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      348182                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5385069                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000321                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.017916                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       260288                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    309866112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          310126400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      348438                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2869710                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000602                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.024538                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5383340     99.97%     99.97% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1729      0.03%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2867981     99.94%     99.94% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1729      0.06%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5385069                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4841670500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2869710                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4842896500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       4221000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    3777687000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             174536                       # Transaction distribution
-system.membus.trans_dist::Writeback            293174                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            53553                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206327                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206327                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        174536                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1108453                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1108453                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1108453                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43138368                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43138368                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43138368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             174499                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       293207                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            53507                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206356                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206356                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        174499                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1108424                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1108424                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1108424                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43139968                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43139968                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43139968                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            727623                       # Request fanout histogram
+system.membus.snoop_fanout::samples            727569                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  727623    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  727569    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              727623                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1900350576                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              727569                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1900428500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1904342076                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1904275000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index e60710ec5..55abb5639 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.225711                       # Nu
 sim_ticks                                225710988500                       # Number of ticks simulated
 final_tick                               225710988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 311102                       # Simulator instruction rate (inst/s)
-host_op_rate                                   311102                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              176136084                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304484                       # Number of bytes of host memory used
-host_seconds                                  1281.46                       # Real time elapsed on the host
+host_inst_rate                                 329346                       # Simulator instruction rate (inst/s)
+host_op_rate                                   329346                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              186465123                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304340                       # Number of bytes of host memory used
+host_seconds                                  1210.47                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -482,6 +482,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks         3187                       # number of writebacks
+system.cpu.icache.writebacks::total              3187                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5165                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         5165                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         5165                       # number of demand (read+write) MSHR misses
@@ -528,8 +530,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4439
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160828                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           114772                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          114772                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          654                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          654                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks          654                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          654                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         3187                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         3187                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           61                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1273                       # number of ReadCleanReq hits
@@ -566,8 +570,10 @@ system.cpu.l2cache.demand_miss_latency::total    593982000
 system.cpu.l2cache.overall_miss_latency::cpu.inst    291102500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data    302879500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total    593982000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          654                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          654                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          654                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          654                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         3187                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         3187                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3198                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3198                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5165                       # number of ReadCleanReq accesses(hits+misses)
@@ -668,8 +674,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp          6132                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         3304                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          654                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         3187                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          117                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3198                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3198                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         5165                       # Transaction distribution
@@ -677,22 +684,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq          967
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13517                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9101                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total             22618                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       330560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       534528                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             638976                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             842944                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        13288                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         9330                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              13288    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               9330    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          13288                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7298000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           9330                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       10485000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       7747500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 0e0bba79f..b6e4d84e4 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.067874                       # Number of seconds simulated
-sim_ticks                                 67874346000                       # Number of ticks simulated
-final_tick                                67874346000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.067897                       # Number of seconds simulated
+sim_ticks                                 67896839000                       # Number of ticks simulated
+final_tick                                67896839000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 238872                       # Simulator instruction rate (inst/s)
-host_op_rate                                   238872                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43169272                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305488                       # Number of bytes of host memory used
-host_seconds                                  1572.28                       # Real time elapsed on the host
+host_inst_rate                                 250075                       # Simulator instruction rate (inst/s)
+host_op_rate                                   250075                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45208847                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305364                       # Number of bytes of host memory used
+host_seconds                                  1501.85                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          220544                       # Nu
 system.physmem.num_reads::cpu.inst               3446                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3989                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7435                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3249298                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3761303                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 7010602                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3249298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3249298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3249298                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3761303                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7010602                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3248222                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3760057                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7008279                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3248222                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3248222                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3248222                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3760057                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7008279                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7435                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7435                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     67874250500                       # Total gap between requests
+system.physmem.totGap                     67896729500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4258                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1860                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       924                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4260                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1857                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       925                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                       329                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1352                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      350.437870                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     208.390396                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     346.239962                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            445     32.91%     32.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          293     21.67%     54.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          153     11.32%     65.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           95      7.03%     72.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           63      4.66%     77.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           39      2.88%     80.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           40      2.96%     83.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           30      2.22%     85.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          194     14.35%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1352                       # Bytes accessed per row activation
-system.physmem.totQLat                       65565000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 204971250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1351                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      351.928942                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     210.322228                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     345.388131                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            435     32.20%     32.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          296     21.91%     54.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          157     11.62%     65.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           94      6.96%     72.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           63      4.66%     77.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           44      3.26%     80.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           40      2.96%     83.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           30      2.22%     85.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          192     14.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1351                       # Bytes accessed per row activation
+system.physmem.totQLat                       64430000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 203836250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     37175000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8818.43                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        8665.77                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27568.43                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27415.77                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           7.01                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        7.01                       # Average system read bandwidth in MiByte/s
@@ -216,70 +216,70 @@ system.physmem.busUtilRead                       0.05                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6075                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6082                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.71                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.80                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9129018.22                       # Average gap between requests
-system.physmem.pageHitRate                      81.71                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5866560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3201000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  32260800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      9132041.63                       # Average gap between requests
+system.physmem.pageHitRate                      81.80                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5851440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3192750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  32416800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4433117520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2086073460                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            38893911750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              45454431090                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.698264                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    64700624500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2266420000                       # Time in different power states
+system.physmem_0.refreshEnergy             4434643200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2090127870                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            38904370500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              45470602560                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.706043                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    64718030250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2267200000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       905970500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       911143500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4354560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2376000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  25482600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4362120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2380125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  25529400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4433117520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1937209410                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            39024494250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              45427034340                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.294616                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    64919021500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2266420000                       # Time in different power states
+system.physmem_1.refreshEnergy             4434643200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1924310025                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            39049824750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              45441049620                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.270777                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    64961032000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2267200000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       687756000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       668141750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                50012521                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          28997086                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            979524                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24735831                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                22942844                       # Number of BTB hits
+system.cpu.branchPred.lookups                50014651                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          28998018                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            978942                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             24722016                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                22941909                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.751458                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9100143                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             92.799507                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9101024                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                303                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    102391599                       # DTB read hits
-system.cpu.dtb.read_misses                      62990                       # DTB read misses
+system.cpu.dtb.read_hits                    102396635                       # DTB read hits
+system.cpu.dtb.read_misses                      63118                       # DTB read misses
 system.cpu.dtb.read_acv                         49453                       # DTB read access violations
-system.cpu.dtb.read_accesses                102454589                       # DTB read accesses
-system.cpu.dtb.write_hits                    78819200                       # DTB write hits
+system.cpu.dtb.read_accesses                102459753                       # DTB read accesses
+system.cpu.dtb.write_hits                    78818401                       # DTB write hits
 system.cpu.dtb.write_misses                      1456                       # DTB write misses
 system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                78820656                       # DTB write accesses
-system.cpu.dtb.data_hits                    181210799                       # DTB hits
-system.cpu.dtb.data_misses                      64446                       # DTB misses
+system.cpu.dtb.write_accesses                78819857                       # DTB write accesses
+system.cpu.dtb.data_hits                    181215036                       # DTB hits
+system.cpu.dtb.data_misses                      64574                       # DTB misses
 system.cpu.dtb.data_acv                         49455                       # DTB access violations
-system.cpu.dtb.data_accesses                181275245                       # DTB accesses
-system.cpu.itb.fetch_hits                    49841893                       # ITB hits
+system.cpu.dtb.data_accesses                181279610                       # DTB accesses
+system.cpu.itb.fetch_hits                    49842949                       # ITB hits
 system.cpu.itb.fetch_misses                       342                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                49842235                       # ITB accesses
+system.cpu.itb.fetch_accesses                49843291                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,140 +293,140 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        135748695                       # number of cpu cycles simulated
+system.cpu.numCycles                        135793681                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           50498280                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      448284151                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    50012521                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           32042987                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      83907127                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2061462                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles           50500103                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      448292718                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    50014651                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           32042933                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      83951008                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2060866                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                          4                       # Number of cycles fetch has spent waiting for tlb
 system.cpu.fetch.MiscStallCycles                  172                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles         13448                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           46                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  49841893                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                439921                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          135449808                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.309596                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.352335                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  49842949                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                438776                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          135495214                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.308550                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.352263                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 56539159     41.74%     41.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4401809      3.25%     44.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  7053804      5.21%     50.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5366390      3.96%     54.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11526105      8.51%     62.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  7792927      5.75%     68.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5844960      4.32%     72.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1860483      1.37%     74.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35064171     25.89%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 56579471     41.76%     41.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4403688      3.25%     45.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  7055956      5.21%     50.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5366912      3.96%     54.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 11526073      8.51%     62.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  7794072      5.75%     68.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5845240      4.31%     72.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1860126      1.37%     74.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 35063676     25.88%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            135449808                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.368420                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.302309                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 43878250                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              15711242                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  70556820                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4276924                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1026572                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9420233                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total            135495214                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.368314                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.301278                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 43850651                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              15792236                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  70529676                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4296377                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1026274                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              9420515                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                  4199                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              443516613                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts              443538757                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                 13825                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1026572                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45656178                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5038667                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         519602                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  72948338                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              10260451                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              440529832                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                437774                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2529018                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2798103                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                3728351                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           287391913                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             579992044                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        412277767                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         167714276                       # Number of floating rename lookups
+system.cpu.rename.SquashCycles                1026274                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45639997                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5068254                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         519346                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  72928908                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10312435                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              440551913                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                438641                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2536044                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2850928                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                3712864                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           287405500                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             580024697                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        412290195                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         167734501                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27859584                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              37459                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                 27873171                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              37458                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            301                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  15899092                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            104653375                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            80643825                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12436283                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9680421                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  409213494                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts                  16037778                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            104660927                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            80646144                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12483488                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9717177                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  409234709                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 295                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 402403006                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            455901                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        33638980                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     16018200                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                 402404750                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            453779                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        33660195                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     16045960                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             80                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     135449808                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.970864                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.211480                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples     135495214                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.969882                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.211663                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            21699625     16.02%     16.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19301136     14.25%     30.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22441860     16.57%     46.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18632936     13.76%     60.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            19381094     14.31%     74.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            13936411     10.29%     85.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9566467      7.06%     92.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             6208123      4.58%     96.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4282156      3.16%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            21727779     16.04%     16.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19323046     14.26%     30.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22437590     16.56%     46.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18638995     13.76%     60.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19382000     14.30%     74.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            13933331     10.28%     85.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9554257      7.05%     92.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6216386      4.59%     96.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4281830      3.16%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       135449808                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       135495214                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  249921      1.26%      1.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                142099      0.71%      1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                 92744      0.47%      2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  4235      0.02%      2.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              3484759     17.51%     19.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1673016      8.41%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9313907     46.79%     75.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4943226     24.84%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  249431      1.25%      1.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                142108      0.71%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                 93369      0.47%      2.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  4363      0.02%      2.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              3491173     17.54%     19.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1672209      8.40%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9312767     46.78%     75.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4941825     24.82%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             151496219     37.65%     37.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2128363      0.53%     38.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             151497707     37.65%     37.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2128305      0.53%     38.19% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            37051349      9.21%     47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7361129      1.83%     49.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2793884      0.69%     49.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16753499      4.16%     54.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1596248      0.40%     54.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            37050665      9.21%     47.39% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7361267      1.83%     49.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2793686      0.69%     49.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16753119      4.16%     54.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1596202      0.40%     54.48% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.48% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.48% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.48% # Type of FU issued
@@ -448,84 +448,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.48% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.48% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.48% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            103848617     25.81%     80.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            79340117     19.72%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            103852879     25.81%     80.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            79337339     19.72%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              402403006                       # Type of FU issued
-system.cpu.iq.rate                           2.964323                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    19903907                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.049463                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          615743047                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         258422157                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    234653025                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           344872581                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          184503638                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    162319054                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              242850926                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               179422406                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         19947233                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              402404750                       # Type of FU issued
+system.cpu.iq.rate                           2.963354                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    19907245                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.049471                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          615781749                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         258431172                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    234656399                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           344883989                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          184537520                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    162320770                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              242844978                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               179433436                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         19957407                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      9898888                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       123887                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        73372                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7123096                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      9906440                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       125316                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        73841                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7125415                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       383831                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads       383693                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked          3808                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1026572                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3903842                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 90265                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           434136051                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             99585                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             104653375                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             80643825                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                1026274                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3908203                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                111577                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           434157595                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             99580                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             104660927                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             80646144                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                295                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   7679                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 82299                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          73372                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         826459                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       307772                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1134231                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             399253806                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             102504065                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3149200                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                   8166                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                103056                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          73841                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         825839                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       307783                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1133622                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             399257785                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             102509229                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3146965                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      24922262                       # number of nop insts executed
-system.cpu.iew.exec_refs                    181324750                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 46546315                       # Number of branches executed
-system.cpu.iew.exec_stores                   78820685                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.941124                       # Inst execution rate
-system.cpu.iew.wb_sent                      397727618                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     396972079                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 196558282                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 281889088                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      24922591                       # number of nop insts executed
+system.cpu.iew.exec_refs                    181329115                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 46548281                       # Number of branches executed
+system.cpu.iew.exec_stores                   78819886                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.940179                       # Inst execution rate
+system.cpu.iew.wb_sent                      397733168                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     396977169                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 196565794                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 281908418                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.924316                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.697289                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.923385                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.697268                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        35472304                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        35494113                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            975365                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    130528765                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     3.054228                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.231390                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            974783                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    130571429                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     3.053230                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.231493                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     46472448     35.60%     35.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     17656165     13.53%     49.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      9417491      7.21%     56.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8632138      6.61%     62.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6273043      4.81%     67.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4304526      3.30%     71.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      4966466      3.80%     74.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2588480      1.98%     76.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     30218008     23.15%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     46510589     35.62%     35.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     17663753     13.53%     49.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      9427402      7.22%     56.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8631802      6.61%     62.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6252911      4.79%     67.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4309640      3.30%     71.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4961322      3.80%     74.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2589236      1.98%     76.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     30224774     23.15%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    130528765                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    130571429                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
 system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -571,32 +571,32 @@ system.cpu.commit.op_class_0::MemWrite       73520729     18.44%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         398664583                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              30218008                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    534444667                       # The number of ROB reads
-system.cpu.rob.rob_writes                   873208037                       # The number of ROB writes
-system.cpu.timesIdled                            3160                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          298887                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              30224774                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    534502374                       # The number of ROB reads
+system.cpu.rob.rob_writes                   873254462                       # The number of ROB writes
+system.cpu.timesIdled                            3162                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          298467                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
 system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.361442                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.361442                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.766692                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.766692                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                399091287                       # number of integer regfile reads
-system.cpu.int_regfile_writes               169885620                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 156870882                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                104904950                       # number of floating regfile writes
+system.cpu.cpi                               0.361562                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.361562                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.765775                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.765775                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                399095542                       # number of integer regfile reads
+system.cpu.int_regfile_writes               169885767                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 156866113                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                104908933                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements               777                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3293.050932                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           155556653                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3293.060025                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           155551655                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4177                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37241.238449                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37240.041896                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3293.050932                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803968                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803968                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3293.060025                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803970                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803970                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3400                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
@@ -604,44 +604,44 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          212
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.830078                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         311160441                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        311160441                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82055589                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82055589                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501058                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501058                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         311150441                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        311150441                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     82050592                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        82050592                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501057                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501057                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data            6                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total            6                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     155556647                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        155556647                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    155556647                       # number of overall hits
-system.cpu.dcache.overall_hits::total       155556647                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1808                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1808                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19671                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19671                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21479                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21479                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21479                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21479                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    128709000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    128709000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1198982453                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1198982453                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1327691453                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1327691453                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1327691453                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1327691453                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     82057397                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     82057397                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     155551649                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        155551649                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    155551649                       # number of overall hits
+system.cpu.dcache.overall_hits::total       155551649                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1805                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1805                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19672                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19672                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21477                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21477                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21477                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21477                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    128536500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    128536500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1197114453                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1197114453                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1325650953                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1325650953                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1325650953                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1325650953                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     82052397                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     82052397                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    155578126                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    155578126                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    155578126                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    155578126                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    155573126                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    155573126                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    155573126                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    155573126                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000268                       # miss rate for WriteReq accesses
@@ -650,32 +650,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000138
 system.cpu.dcache.demand_miss_rate::total     0.000138                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000138                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000138                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71188.606195                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71188.606195                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60951.779421                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60951.779421                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61813.466782                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61813.466782                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61813.466782                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61813.466782                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        49798                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71211.357341                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71211.357341                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60853.723719                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60853.723719                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61724.214415                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61724.214415                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61724.214415                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61724.214415                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        49394                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets           86                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs               748                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.574866                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.034759                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets           86                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          656                       # number of writebacks
 system.cpu.dcache.writebacks::total               656                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          820                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          820                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16482                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16482                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        17302                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        17302                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        17302                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        17302                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          817                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          817                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16483                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16483                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17300                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17300                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17300                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17300                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          988                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          988                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3189                       # number of WriteReq MSHR misses
@@ -684,14 +684,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4177
 system.cpu.dcache.demand_mshr_misses::total         4177                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4177                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4177                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75199500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     75199500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    250368000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    250368000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    325567500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    325567500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    325567500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    325567500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     74845500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     74845500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    249448500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    249448500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    324294000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    324294000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    324294000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    324294000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -700,130 +700,134 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76112.854251                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76112.854251                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78509.877705                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78509.877705                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77942.901604                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77942.901604                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77942.901604                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77942.901604                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75754.554656                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75754.554656                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78221.542803                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78221.542803                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77638.017716                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77638.017716                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77638.017716                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77638.017716                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              2126                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1833.088267                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            49836296                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1833.091155                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            49837345                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              4054                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12293.116922                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          12293.375678                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1833.088267                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.895063                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.895063                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1833.091155                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.895064                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.895064                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          287                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1353                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          99687840                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         99687840                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     49836296                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        49836296                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      49836296                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         49836296                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     49836296                       # number of overall hits
-system.cpu.icache.overall_hits::total        49836296                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5597                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5597                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5597                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5597                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5597                       # number of overall misses
-system.cpu.icache.overall_misses::total          5597                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    364082499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    364082499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    364082499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    364082499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    364082499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    364082499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     49841893                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     49841893                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     49841893                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     49841893                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     49841893                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     49841893                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          99689952                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         99689952                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     49837345                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        49837345                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      49837345                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         49837345                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     49837345                       # number of overall hits
+system.cpu.icache.overall_hits::total        49837345                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5604                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5604                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5604                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5604                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5604                       # number of overall misses
+system.cpu.icache.overall_misses::total          5604                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    365347499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    365347499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    365347499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    365347499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    365347499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    365347499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     49842949                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     49842949                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     49842949                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     49842949                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     49842949                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     49842949                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000112                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000112                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000112                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000112                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000112                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000112                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65049.579954                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65049.579954                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65049.579954                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65049.579954                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65049.579954                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65049.579954                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          650                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65194.057637                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 65194.057637                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 65194.057637                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 65194.057637                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 65194.057637                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 65194.057637                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          644                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    92.857143                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           92                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1543                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1543                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1543                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1543                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1543                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1543                       # number of overall MSHR hits
+system.cpu.icache.writebacks::writebacks         2126                       # number of writebacks
+system.cpu.icache.writebacks::total              2126                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1550                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1550                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1550                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1550                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1550                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1550                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4054                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         4054                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         4054                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         4054                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         4054                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         4054                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    273657000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    273657000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    273657000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    273657000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    273657000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    273657000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    273942500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    273942500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    273942500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    273942500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    273942500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    273942500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000081                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000081                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000081                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67502.960039                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67502.960039                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67502.960039                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67502.960039                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67502.960039                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67502.960039                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67573.384312                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67573.384312                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67573.384312                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4002.026272                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         4002.038570                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               3073                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4841                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.634786                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   371.009955                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2970.733849                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   660.282469                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   371.011804                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2970.742908                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   660.283858                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011322                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090660                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.020150                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.122132                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.122133                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4841                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          147                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          136                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          528                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4030                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.147736                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses            97102                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses           97102                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          656                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          656                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks          656                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          656                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         2126                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         2126                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          608                       # number of ReadCleanReq hits
@@ -848,20 +852,22 @@ system.cpu.l2cache.demand_misses::total          7435                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3446                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3989                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7435                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    244858000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    244858000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    261180500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    261180500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     72283000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     72283000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    261180500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    317141000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    578321500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    261180500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    317141000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    578321500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          656                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          656                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    243935500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    243935500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    261376000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    261376000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     71927500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     71927500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    261376000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    315863000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    577239000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    261376000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    315863000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    577239000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          656                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          656                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         2126                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         2126                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3189                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3189                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4054                       # number of ReadCleanReq accesses(hits+misses)
@@ -886,18 +892,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.903292                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.850025                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.954992                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.903292                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78254.394375                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78254.394375                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75792.367963                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75792.367963                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        84050                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        84050                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75792.367963                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79503.885686                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77783.658373                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75792.367963                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79503.885686                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77783.658373                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77959.571748                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77959.571748                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75849.100406                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75849.100406                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83636.627907                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83636.627907                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75849.100406                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79183.504638                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77638.063215                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75849.100406                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79183.504638                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77638.063215                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -918,18 +924,18 @@ system.cpu.l2cache.demand_mshr_misses::total         7435
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3446                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3989                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7435                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    213568000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    213568000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    226720500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    226720500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63683000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63683000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    226720500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    277251000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    503971500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    226720500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    277251000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    503971500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    212645500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    212645500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    226916000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    226916000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63327500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63327500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    226916000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    275973000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    502889000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    226916000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    275973000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    502889000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981185                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981185                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for ReadCleanReq accesses
@@ -942,18 +948,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.903292
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.954992                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.903292                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68254.394375                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68254.394375                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65792.367963                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65792.367963                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        74050                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        74050                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65792.367963                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69503.885686                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67783.658373                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65792.367963                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69503.885686                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67783.658373                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67959.571748                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67959.571748                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65849.100406                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73636.627907                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73636.627907                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69183.504638                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67638.063215                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69183.504638                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67638.063215                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        11134                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         2903                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -962,8 +968,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp          5042                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          656                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         2247                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          656                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         2126                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          121                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3189                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3189                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         4054                       # Transaction distribution
@@ -971,22 +978,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq          988
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10234                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9131                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total             19365                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       259456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       395520                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             568768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             704832                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        11134                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         8231                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              11134    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               8231    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          11134                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        6223000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           8231                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        8349000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       6081000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
@@ -1011,9 +1018,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7435                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9180000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9238500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           39204250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           39203500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index b9717df42..8253a646b 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.567335                       # Number of seconds simulated
-sim_ticks                                567335097500                       # Number of ticks simulated
-final_tick                               567335097500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.567385                       # Number of seconds simulated
+sim_ticks                                567385356500                       # Number of ticks simulated
+final_tick                               567385356500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1348015                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1348015                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1918345002                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301916                       # Number of bytes of host memory used
-host_seconds                                   295.74                       # Real time elapsed on the host
+host_inst_rate                                1390819                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1390819                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1979434182                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 302276                       # Number of bytes of host memory used
+host_seconds                                   286.64                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          205120                       # Nu
 system.physmem.num_reads::cpu.inst               3205                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3969                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7174                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               361550                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               447735                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  809285                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          361550                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             361550                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              361550                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              447735                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 809285                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               361518                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               447696                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  809214                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          361518                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             361518                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              361518                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              447696                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 809214                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -63,7 +63,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                       1134670195                       # number of cpu cycles simulated
+system.cpu.numCycles                       1134770713                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664609                       # Number of instructions committed
@@ -82,7 +82,7 @@ system.cpu.num_mem_refs                     168275276                       # nu
 system.cpu.num_load_insts                    94754511                       # Number of load instructions
 system.cpu.num_store_insts                   73520765                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1134670195                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1134770713                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                          44587535                       # Number of branches fetched
@@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  398664665                       # Class of executed instruction
 system.cpu.dcache.tags.replacements               764                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3288.930558                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3288.807028                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168271068                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          40527.713873                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3288.930558                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.802962                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.802962                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3288.807028                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.802931                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.802931                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
@@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data         4152                       # n
 system.cpu.dcache.demand_misses::total           4152                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         4152                       # number of overall misses
 system.cpu.dcache.overall_misses::total          4152                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     47084000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     47084000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    173590000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    173590000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    220674000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    220674000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    220674000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    220674000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     52888500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     52888500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    195593000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    195593000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    248481500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    248481500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    248481500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    248481500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     94754490                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     94754490                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520730                       # number of WriteReq accesses(hits+misses)
@@ -179,14 +179,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53148.843931                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53148.843931                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59846.218690                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59846.218690                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4152
 system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     46134000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     46134000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    170388000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    170388000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    216522000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    216522000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    216522000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    216522000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51938500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     51938500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    192391000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    192391000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    244329500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    244329500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    244329500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    244329500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
@@ -221,28 +221,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48562.105263                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48562.105263                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53212.991880                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53212.991880                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52148.843931                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52148.843931                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52148.843931                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52148.843931                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1769                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1795.138955                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1795.084430                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           398660993                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              3673                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          108538.250204                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1795.138955                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.876533                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.876533                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1795.084430                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.876506                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.876506                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1904                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          251                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1375                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.929688                       # Percentage of cache occupancy per task id
@@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst         3673                       # n
 system.cpu.icache.demand_misses::total           3673                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         3673                       # number of overall misses
 system.cpu.icache.overall_misses::total          3673                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    182363500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    182363500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    182363500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    182363500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    182363500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    182363500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    204815000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    204815000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    204815000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    204815000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    204815000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    204815000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    398664666                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    398664666                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    398664666                       # number of demand (read+write) accesses
@@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000009
 system.cpu.icache.demand_miss_rate::total     0.000009                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000009                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000009                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49649.741356                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49649.741356                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49649.741356                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49649.741356                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49649.741356                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49649.741356                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55762.319630                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55762.319630                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -292,55 +292,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks         1769                       # number of writebacks
+system.cpu.icache.writebacks::total              1769                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3673                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         3673                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         3673                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         3673                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3673                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3673                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    178690500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    178690500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    178690500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    178690500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    178690500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    178690500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    201142000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    201142000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    201142000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    201142000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    201142000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    201142000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000009                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48649.741356                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48649.741356                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48649.741356                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48649.741356                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48649.741356                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48649.741356                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3772.485272                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         3772.330397                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               2561                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4566                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.560885                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   371.540218                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2770.469899                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   630.475155                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011339                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084548                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.019241                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.115127                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   371.516873                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2770.363420                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   630.450105                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011338                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084545                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.019240                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.115122                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4566                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           77                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          497                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3787                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.139343                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses            90632                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses           90632                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          649                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          649                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks          649                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          649                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         1769                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         1769                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          468                       # number of ReadCleanReq hits
@@ -365,20 +369,22 @@ system.cpu.l2cache.demand_misses::total          7174                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3205                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3969                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7174                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    164955000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    164955000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    168265000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    168265000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     43417500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     43417500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    168265000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    208372500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    376637500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    168265000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    208372500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    376637500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          649                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          649                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    186953000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    186953000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    190709000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    190709000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     49213500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     49213500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    190709000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    236166500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    426875500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    190709000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    236166500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    426875500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          649                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          649                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         1769                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         1769                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3202                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3202                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         3673                       # number of ReadCleanReq accesses(hits+misses)
@@ -403,18 +409,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.916805                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.872584                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955925                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.916805                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.780031                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.780031                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data        52500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total        52500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.780031                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.348481                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.780031                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.348481                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -435,18 +441,18 @@ system.cpu.l2cache.demand_mshr_misses::total         7174
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3205                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3969                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7174                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    133535000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    133535000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    136215000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    136215000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     35147500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     35147500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    136215000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    168682500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    304897500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    136215000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    168682500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    304897500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    155533000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    155533000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    158659000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    158659000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     40943500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     40943500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    158659000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    196476500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    355135500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    158659000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    196476500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    355135500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981262                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981262                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for ReadCleanReq accesses
@@ -459,18 +465,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.916805
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.916805                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.780031                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.780031                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data        42500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total        42500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.780031                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.348481                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        42500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        10358                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         2533                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -479,8 +485,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp          4623                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          649                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         1884                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          649                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         1769                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          115                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3202                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3202                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         3673                       # Transaction distribution
@@ -488,22 +495,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq          950
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         9115                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9068                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total             18183                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       235072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       348288                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       307264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             542336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             655552                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        10358                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         7825                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              10358    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               7825    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          10358                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        5828000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           7825                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7597000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       5509500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
@@ -528,9 +535,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7174                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7176500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             7196500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           35872500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           35870000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 5974a793e..54314baaf 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.215510                       # Number of seconds simulated
-sim_ticks                                215510486500                       # Number of ticks simulated
-final_tick                               215510486500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.215512                       # Number of seconds simulated
+sim_ticks                                215512229500                       # Number of ticks simulated
+final_tick                               215512229500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 166248                       # Simulator instruction rate (inst/s)
-host_op_rate                                   199599                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              131220473                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 326292                       # Number of bytes of host memory used
-host_seconds                                  1642.35                       # Real time elapsed on the host
+host_inst_rate                                 175368                       # Simulator instruction rate (inst/s)
+host_op_rate                                   210548                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              138419960                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 326400                       # Number of bytes of host memory used
+host_seconds                                  1556.94                       # Real time elapsed on the host
 sim_insts                                   273037857                       # Number of instructions simulated
 sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          218880                       # Nu
 system.physmem.num_reads::cpu.inst               3420                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4162                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7582                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1015635                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1235986                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2251621                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1015635                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1015635                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1015635                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1235986                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2251621                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1015627                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1235976                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2251603                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1015627                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1015627                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1015627                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1235976                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2251603                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7582                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7582                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    215510247500                       # Total gap between requests
+system.physmem.totGap                    215511990500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6628                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       893                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6627                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       894                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1514                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      319.408190                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.009179                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     331.260420                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            549     36.26%     36.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          346     22.85%     59.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          166     10.96%     70.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           79      5.22%     75.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           78      5.15%     80.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           48      3.17%     83.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           37      2.44%     86.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           27      1.78%     87.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          184     12.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1514                       # Bytes accessed per row activation
-system.physmem.totQLat                       52026250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 194188750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1510                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      320.169536                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.396997                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     331.756940                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            550     36.42%     36.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          336     22.25%     58.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          179     11.85%     70.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           73      4.83%     75.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           74      4.90%     80.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           52      3.44%     83.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           33      2.19%     85.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           29      1.92%     87.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          184     12.19%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1510                       # Bytes accessed per row activation
+system.physmem.totQLat                       54741000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 196903500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     37910000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6861.81                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7219.86                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25611.81                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25969.86                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.25                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.25                       # Average system read bandwidth in MiByte/s
@@ -216,47 +216,47 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6062                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6065                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.95                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.99                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28423931.35                       # Average gap between requests
-system.physmem.pageHitRate                      79.95                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5050080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2755500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  29952000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     28424161.24                       # Average gap between requests
+system.physmem.pageHitRate                      79.99                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5019840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2739000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  29905200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy            14075923680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5660638650                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           124339380000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             144113699910                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.715971                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   206848311250                       # Time in different power states
+system.physmem_0.actBackEnergy             5641560180                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           124356115500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             144111263400                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.704665                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   206876360250                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      7196280000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1464242250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1436474750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6388200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3485625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                    6373080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3477375                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                  28977000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy            14075923680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5785657605                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           124229714250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             144130146360                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.792285                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   206662748250                       # Time in different power states
+system.physmem_1.actBackEnergy             5809762620                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           124208569500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             144133083255                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.805913                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   206629350750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      7196280000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1649073000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1684213750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                32816918                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16892730                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                32816919                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16892731                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1463888                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             17497037                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                15468342                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             17497038                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                15468343                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             88.405494                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             88.405495                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 6575577                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -377,26 +377,26 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        431020973                       # number of cpu cycles simulated
+system.cpu.numCycles                        431024459                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   273037857                       # Number of instructions committed
 system.cpu.committedOps                     327812214                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                       3889164                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.578612                       # CPI: cycles per instruction
-system.cpu.ipc                               0.633468                       # IPC: instructions per cycle
-system.cpu.tickCycles                       427416493                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3604480                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.578625                       # CPI: cycles per instruction
+system.cpu.ipc                               0.633463                       # IPC: instructions per cycle
+system.cpu.tickCycles                       427416966                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3607493                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements              1354                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3085.814208                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3085.807941                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168714884                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          37400.772334                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3085.814208                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.753373                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.753373                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3085.807941                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.753371                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753371                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
@@ -430,14 +430,14 @@ system.cpu.dcache.demand_misses::cpu.data         7285                       # n
 system.cpu.dcache.demand_misses::total           7285                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         7290                       # number of overall misses
 system.cpu.dcache.overall_misses::total          7290                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    136254500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    136254500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    393515500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    393515500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    529770000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    529770000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    529770000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    529770000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    138607500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    138607500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    393622500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    393622500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    532230000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    532230000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    532230000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    532230000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     86584168                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     86584168                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
@@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000043
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72720.658888                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72670.781893                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67317.872754                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67317.872754                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75320.034443                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75320.034443                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73058.339053                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73058.339053                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73008.230453                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73008.230453                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4508
 system.cpu.dcache.demand_mshr_misses::total         4508                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4511                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    109975000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    109975000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    219249000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    219249000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    111882000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    111882000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    219521500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    219521500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       238000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       238000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329224000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    329224000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    329462000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    329462000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    331403500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    331403500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    331641500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    331641500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68304.029304                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68304.029304                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76488.327526                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76488.327526                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73514.529725                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73514.529725                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73518.399468                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73518.399468                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             36873                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1923.840697                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            72548791                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             38809                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1869.380582                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             36871                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1923.837997                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            72548794                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             38807                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1869.477002                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1923.840697                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.939375                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.939375                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1923.837997                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939374                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939374                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1936                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
@@ -547,42 +547,42 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4         1485
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945312                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         145214011                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        145214011                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     72548791                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        72548791                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      72548791                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         72548791                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     72548791                       # number of overall hits
-system.cpu.icache.overall_hits::total        72548791                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        38810                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         38810                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        38810                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          38810                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        38810                       # number of overall misses
-system.cpu.icache.overall_misses::total         38810                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    740838000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    740838000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    740838000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    740838000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    740838000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    740838000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     72587601                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     72587601                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     72587601                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     72587601                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     72587601                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     72587601                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     72548794                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        72548794                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      72548794                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         72548794                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     72548794                       # number of overall hits
+system.cpu.icache.overall_hits::total        72548794                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        38808                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         38808                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        38808                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          38808                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        38808                       # number of overall misses
+system.cpu.icache.overall_misses::total         38808                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    741346000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    741346000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    741346000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    741346000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    741346000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    741346000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     72587602                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     72587602                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     72587602                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     72587602                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     72587602                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     72587602                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000535                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000535                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000535                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000535                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000535                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000535                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19088.843082                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19088.843082                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19088.843082                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19088.843082                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19088.843082                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19088.843082                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19102.916924                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19102.916924                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19102.916924                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19102.916924                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19102.916924                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19102.916924                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,40 +591,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38810                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        38810                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        38810                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        38810                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        38810                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        38810                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    702029000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    702029000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    702029000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    702029000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    702029000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    702029000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks        36871                       # number of writebacks
+system.cpu.icache.writebacks::total             36871                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38808                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        38808                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        38808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        38808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        38808                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        38808                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    702539000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    702539000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    702539000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    702539000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    702539000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    702539000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000535                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000535                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000535                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18088.868848                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18102.942692                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18102.942692                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18102.942692                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4197.348676                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              57958                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4197.336283                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              57954                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             5644                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.268958                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.268249                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   353.816119                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3165.200424                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   678.332133                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   353.814210                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3165.192128                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   678.329945                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.010798                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096594                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.020701                       # Average percentage of cache occupancy
@@ -636,22 +638,24 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2           43
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1250                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4259                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172241                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           540762                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          540762                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks         1010                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total         1010                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses           540730                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          540730                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks         1010                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total         1010                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        21970                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        21970                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        35388                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        35388                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        35386                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        35386                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data          291                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total          291                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        35388                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        35386                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          307                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           35695                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        35388                       # number of overall hits
+system.cpu.l2cache.demand_hits::total           35693                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        35386                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          307                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          35695                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          35693                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         2854                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         2854                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3422                       # number of ReadCleanReq misses
@@ -664,56 +668,58 @@ system.cpu.l2cache.demand_misses::total          7626                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3422                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         4204                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7626                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    214741500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    214741500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    257334000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    257334000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    104502500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total    104502500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    257334000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    319244000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    576578000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    257334000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    319244000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    576578000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks         1010                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total         1010                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    215012500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    215012500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    257866500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    257866500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    106408000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total    106408000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    257866500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    321420500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    579287000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    257866500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    321420500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    579287000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks         1010                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total         1010                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        21970                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        21970                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         2870                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         2870                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        38810                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        38810                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        38808                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        38808                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data         1641                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total         1641                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        38810                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        38808                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         4511                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        43321                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        38810                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        43319                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        38808                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4511                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        43321                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        43319                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994425                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.994425                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.088173                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.088173                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.088178                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.088178                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.822669                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.822669                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088173                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088178                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.931944                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.176035                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088173                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088178                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.931944                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.176035                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75199.883109                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77409.259259                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77409.259259                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75199.883109                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75938.154139                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75606.871230                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75199.883109                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75938.154139                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75606.871230                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.176043                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75337.245971                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75337.245971                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75355.493863                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75355.493863                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78820.740741                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78820.740741                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75355.493863                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76455.875357                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75962.103331                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75355.493863                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76455.875357                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75962.103331                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -744,79 +750,80 @@ system.cpu.l2cache.demand_mshr_misses::total         7582
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3420                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         4162                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7582                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    186201500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    186201500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    222999500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    222999500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     88418500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     88418500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    222999500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    274620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    497619500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    222999500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    274620000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    497619500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    186472500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    186472500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    223532000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    223532000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     90324000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     90324000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    223532000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    276796500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    500328500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    223532000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    276796500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    500328500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.088122                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088122                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088126                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.797075                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088122                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.175019                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088122                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.175027                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.175019                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.175027                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65337.245971                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65337.245971                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65360.233918                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69055.045872                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69055.045872                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66505.646324                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65988.987075                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66505.646324                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65988.987075                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        81548                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests        38331                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        81544                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests        38329                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15017                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         40450                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback         1010                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        22200                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         40448                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty         1010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        21970                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          228                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        38810                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        38808                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq         1641                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        99591                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        99585                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10260                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            109851                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2483776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            109845                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3889728                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            2837120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            4243072                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        81548                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.369574                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.482692                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        43319                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.349062                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.476679                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              51410     63.04%     63.04% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              30138     36.96%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              28198     65.09%     65.09% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              15121     34.91%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          81548                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       41784000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          43319                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       78653000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      58214498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      58211498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6787458                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6787957                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp               4728                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
@@ -837,9 +844,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7582                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             8866500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             8861000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           40241250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           40239750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index b3c953357..8af356e7f 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,66 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.112728                       # Number of seconds simulated
-sim_ticks                                112728298500                       # Number of ticks simulated
-final_tick                               112728298500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.116576                       # Number of seconds simulated
+sim_ticks                                116576497500                       # Number of ticks simulated
+final_tick                               116576497500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 116763                       # Simulator instruction rate (inst/s)
-host_op_rate                                   140187                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               48207604                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 330392                       # Number of bytes of host memory used
-host_seconds                                  2338.39                       # Real time elapsed on the host
+host_inst_rate                                 122787                       # Simulator instruction rate (inst/s)
+host_op_rate                                   147419                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52425325                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 336136                       # Number of bytes of host memory used
+host_seconds                                  2223.67                       # Real time elapsed on the host
 sim_insts                                   273037220                       # Number of instructions simulated
 sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            187008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            112768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       169408                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               469184                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       187008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          187008                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2922                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1762                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         2647                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7331                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1658927                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1000352                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher      1502799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4162078                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1658927                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1658927                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1658927                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1000352                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher      1502799                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4162078                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7331                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            620608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           4625216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       169088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              5414912                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       620608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          620608                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               9697                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              72269                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         2642                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 84608                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              5323612                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39675373                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher      1450447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                46449431                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5323612                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5323612                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5323612                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            39675373                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher      1450447                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               46449431                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         84608                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7331                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       84608                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   469184                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                  5414912                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    469184                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                   5414912                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              1                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 589                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 789                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 601                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 520                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 444                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 345                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 153                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 255                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 219                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 290                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                315                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                411                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                547                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                678                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                620                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                555                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 955                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 811                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 833                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                2939                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10638                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               59815                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 159                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 253                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 227                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 304                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               3835                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                811                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               1140                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                693                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                643                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                552                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    112728140000                       # Total gap between requests
+system.physmem.totGap                    116576339000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7331                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   84608                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,20 +94,20 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4022                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       466                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       296                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       233                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       204                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       179                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       174                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       23                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       16                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     64943                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     17781                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       311                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       234                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       214                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       178                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       159                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       176                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        53                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       21                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1373                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      339.670794                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     197.560456                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     349.691004                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            480     34.96%     34.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          312     22.72%     57.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          141     10.27%     67.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           79      5.75%     73.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           55      4.01%     77.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           48      3.50%     81.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           23      1.68%     82.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           27      1.97%     84.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          208     15.15%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1373                       # Bytes accessed per row activation
-system.physmem.totQLat                       90206647                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 227662897                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     36655000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12304.82                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        22133                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      244.635973                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     206.851890                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     150.002141                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           2617     11.82%     11.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8410     38.00%     49.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7826     35.36%     85.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1287      5.81%     91.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1278      5.77%     96.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          443      2.00%     98.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           32      0.14%     98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           31      0.14%     99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          209      0.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          22133                       # Bytes accessed per row activation
+system.physmem.totQLat                      841966540                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2428366540                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    423040000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9951.38                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31054.82                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.16                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28701.38                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          46.45                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.16                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       46.45                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.36                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.36                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.50                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5948                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      62473                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.13                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   73.84                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15376911.74                       # Average gap between requests
-system.physmem.pageHitRate                      81.13                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    4815720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2627625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  28618200                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      1377840.62                       # Average gap between requests
+system.physmem.pageHitRate                      73.84                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  142967160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   78007875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 595896600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             7362423120                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3214163025                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            64813639500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              75426287190                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.136639                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   107820696894                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      3764020000                       # Time in different power states
+system.physmem_0.refreshEnergy             7614160320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            63983016135                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            13820144250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              86234192340                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              739.725124                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    22625694019                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      3892720000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1137632606                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     90057594731                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5511240                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3007125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  28126800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                   24358320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   13290750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  63999000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             7362423120                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3285750465                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            64750835250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              75435654000                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.219817                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   107714946135                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      3764020000                       # Time in different power states
+system.physmem_1.refreshEnergy             7614160320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11183516280                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            60135495000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              79034819670                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              677.968219                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    99984327847                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      3892720000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1243230865                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     12698960903                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                37743002                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20164593                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1746138                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18663724                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                17299181                       # Number of BTB hits
+system.cpu.branchPred.lookups                37744347                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          20165678                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1746151                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18664383                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                17300356                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.688796                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7223599                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3815                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.691818                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7223561                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3816                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,129 +381,130 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        225456598                       # number of cpu cycles simulated
+system.cpu.numCycles                        233152996                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12486047                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      334063522                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37743002                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24522780                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     210891035                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3510673                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1258                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles         2507                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  89094273                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 21774                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          225136183                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.799914                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.229503                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           12613908                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      334078036                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    37744347                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24523917                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     217730983                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3511013                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1155                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles             1                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles         2593                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  89097958                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 22048                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          232104146                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.745924                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.249191                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 51412756     22.84%     22.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42958324     19.08%     41.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 30027813     13.34%     55.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                100737290     44.75%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58364727     25.15%     25.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 42980177     18.52%     43.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 30021674     12.93%     56.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                100737568     43.40%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            225136183                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.167407                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.481720                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 27896248                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63927882                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 108602791                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              23088664                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1620598                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              6880038                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                135173                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              363542969                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               6170181                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1620598                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45231914                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                18002517                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         341926                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 113354912                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46584316                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              355763735                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               2890412                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               6625666                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 177937                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7803151                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               21129906                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents          2817742                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           403401676                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2534003745                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        350242817                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         194894499                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            232104146                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.161887                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.432870                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 28023980                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              70770838                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 108573375                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              23115192                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1620761                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6880073                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                135178                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              363549116                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               6170266                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1620761                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45363672                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                24814789                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         341990                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 113350212                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              46612722                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              355770088                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               2890615                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               6644499                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 177384                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7802434                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               21145232                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents          2810415                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           403411912                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2534053104                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        350245362                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         194900491                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             372230051                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 31171625                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              17016                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          17025                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  55451024                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             92416595                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            88498352                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1661185                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1846398                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  353252669                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               28026                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 346437634                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           2301476                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        25469093                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     73749076                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           5906                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     225136183                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.538791                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.099493                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 31181861                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              16825                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          16811                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  55467243                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             92417326                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            88498414                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1663819                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1859064                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  353254299                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               27832                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 346438253                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           2301561                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        25470529                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     73751649                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           5712                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     232104146                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.492598                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.113201                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            40701776     18.08%     18.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            78366146     34.81%     52.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            60939580     27.07%     79.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            34977344     15.54%     95.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9507598      4.22%     99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5              632530      0.28%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6               11209      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            47511470     20.47%     20.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            78618745     33.87%     54.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            60884809     26.23%     80.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            34936770     15.05%     95.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9533364      4.11%     99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5              607804      0.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6               11184      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       225136183                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       232104146                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9586225      7.69%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   7350      0.01%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd            255762      0.21%      7.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp            132929      0.11%      8.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt             93071      0.07%      8.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv             61949      0.05%      8.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           719141      0.58%      8.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult           303244      0.24%      8.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        683031      0.55%      9.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               53752847     43.14%     52.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              59000415     47.35%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9573854      7.69%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   7345      0.01%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd            255499      0.21%      7.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.90% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp            127544      0.10%      8.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt             93452      0.08%      8.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv             56991      0.05%      8.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           707524      0.57%      8.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult           297297      0.24%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        683417      0.55%      9.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               53764278     43.17%     52.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              58976477     47.35%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             110655046     31.94%     31.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2148359      0.62%     32.56% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             110655125     31.94%     31.94% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2148158      0.62%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.56% # Type of FU issued
@@ -522,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.56% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6798342      1.96%     34.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6798099      1.96%     34.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8667218      2.50%     37.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3332482      0.96%     37.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1592517      0.46%     38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20930304      6.04%     44.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8667622      2.50%     37.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3332487      0.96%     37.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1592703      0.46%     38.45% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20931016      6.04%     44.49% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult        7182327      2.07%     46.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc      7148965      2.06%     48.63% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     48.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             91923294     26.53%     75.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            85883494     24.79%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             91923310     26.53%     75.21% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            85883155     24.79%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              346437634                       # Type of FU issued
-system.cpu.iq.rate                           1.536605                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   124595964                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.359649                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          757212589                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         251740831                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    223259855                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           287696302                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          127019209                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    117423886                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              303336303                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               167697295                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5085757                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              346438253                       # Type of FU issued
+system.cpu.iq.rate                           1.485884                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   124543678                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.359497                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          764166784                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         251741027                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    223260031                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           287659107                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          127022045                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    117425060                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              303322253                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               167659678                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5063326                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6684320                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13571                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        10256                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6122735                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6685051                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        13552                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        10416                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6122797                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       155306                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        607778                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       155252                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        607596                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1620598                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2118913                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                332541                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           353281560                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                1620761                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2118966                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                346415                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           353282999                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              92416595                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             88498352                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              16993                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   8047                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                339026                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          10256                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1220653                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       439070                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1659723                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             342447875                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              90703562                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3989759                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              92417326                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             88498414                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              16799                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   8049                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                352915                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          10416                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1220605                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       439066                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1659671                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             342448265                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              90703428                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3989988                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           865                       # number of nop insts executed
-system.cpu.iew.exec_refs                    175290975                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31752712                       # Number of branches executed
-system.cpu.iew.exec_stores                   84587413                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.518908                       # Inst execution rate
-system.cpu.iew.wb_sent                      340942422                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     340683741                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 153622639                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 266573014                       # num instructions consuming a value
+system.cpu.iew.exec_nop                           868                       # number of nop insts executed
+system.cpu.iew.exec_refs                    175290651                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31753222                       # Number of branches executed
+system.cpu.iew.exec_stores                   84587223                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.468771                       # Inst execution rate
+system.cpu.iew.wb_sent                      340943350                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     340685091                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 153596503                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 266530182                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.511083                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.576287                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.461208                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.576282                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23082594                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        23083392                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1611400                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    221410973                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.480560                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.051639                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1611406                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    228378919                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.435387                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.036441                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     87667745     39.60%     39.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     70465931     31.83%     71.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20808534      9.40%     80.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13377083      6.04%     86.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8762034      3.96%     90.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4538069      2.05%     92.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3005918      1.36%     94.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2461295      1.11%     95.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10324364      4.66%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     94653053     41.45%     41.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     70419351     30.83%     72.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     20855772      9.13%     81.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13391170      5.86%     87.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8734239      3.82%     91.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4529616      1.98%     93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3006865      1.32%     94.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2429241      1.06%     95.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10359612      4.54%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    221410973                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    228378919                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            273037832                       # Number of instructions committed
 system.cpu.commit.committedOps              327812214                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -654,182 +655,182 @@ system.cpu.commit.op_class_0::MemWrite       82375617     25.13%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         327812214                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              10324364                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    561978894                       # The number of ROB reads
-system.cpu.rob.rob_writes                   705518745                       # The number of ROB writes
-system.cpu.timesIdled                           51182                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          320415                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              10359612                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    568912390                       # The number of ROB reads
+system.cpu.rob.rob_writes                   705520379                       # The number of ROB writes
+system.cpu.timesIdled                           58444                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1048850                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273037220                       # Number of Instructions Simulated
 system.cpu.committedOps                     327811602                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.825736                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.825736                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.211041                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.211041                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                331331297                       # number of integer regfile reads
-system.cpu.int_regfile_writes               136939218                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 187106677                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                132176732                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                1297128117                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 80240781                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1183123878                       # number of misc regfile reads
+system.cpu.cpi                               0.853924                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.853924                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.171065                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.171065                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                331328730                       # number of integer regfile reads
+system.cpu.int_regfile_writes               136938455                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 187108865                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                132177694                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                1297131127                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 80243114                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1183136277                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1533840                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.843429                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           163621677                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1534352                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            106.638944                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          82703000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.843429                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999694                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999694                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1533838                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.844582                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           163641356                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1534350                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            106.651909                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          84508000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.844582                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999696                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999696                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           91                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336594804                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336594804                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82588364                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82588364                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     80941030                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       80941030                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        70477                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         70477                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        10909                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        10909                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         336640002                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336640002                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     82608606                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        82608606                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     80940468                       # number of WriteReq hits
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+system.cpu.dcache.SoftPFReq_hits::cpu.data        70474                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         70474                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        10911                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        10911                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     163529394                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        163529394                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    163599871                       # number of overall hits
-system.cpu.dcache.overall_hits::total       163599871                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2796859                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2796859                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1111669                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1111669                       # number of WriteReq misses
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+system.cpu.dcache.ReadReq_misses::total       2799218                       # number of ReadReq misses
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+system.cpu.dcache.WriteReq_misses::total      1112231                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           18                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           18                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            5                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            5                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3908528                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3908528                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3908546                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3908546                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  22523988500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  22523988500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8974716998                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8974716998                       # number of WriteReq miss cycles
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+system.cpu.dcache.overall_misses::cpu.data      3911467                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3911467                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31000710000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31000710000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8973516996                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8973516996                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       189000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  31498705498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  31498705498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  31498705498                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  31498705498                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     85385223                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     85385223                       # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.overall_miss_latency::total  39974226996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     85407824                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     85407824                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        70495                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        70495                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10914                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        10914                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        70492                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        70492                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10916                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        10916                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167437922                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167437922                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167508417                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167508417                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032756                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032756                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013548                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013548                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    167460523                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167460523                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    167531015                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167531015                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032775                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032775                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013555                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013555                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000255                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.000255                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000458                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000458                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023343                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023343                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.023333                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.023333                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8053.315702                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  8053.315702                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8073.191749                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8073.191749                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023357                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023357                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.023348                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023348                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11074.775169                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11074.775169                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8068.033525                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8068.033525                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        37800                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        37800                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  8058.968875                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  8058.968875                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  8058.931761                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  8058.931761                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.800129                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10219.800129                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.753099                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10219.753099                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      1061983                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1061203                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          134750                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          134969                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.881135                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     7.862568                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       966339                       # number of writebacks
-system.cpu.dcache.writebacks::total            966339                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1483171                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1483171                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       891014                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       891014                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      1533838                       # number of writebacks
+system.cpu.dcache.writebacks::total           1533838                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1485532                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1485532                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       891576                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       891576                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            5                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            5                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2374185                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2374185                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2374185                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2374185                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1313688                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1313688                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      2377108                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2377108                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2377108                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2377108                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1313686                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1313686                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220655                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       220655                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           11                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           11                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1534343                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1534343                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1534354                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1534354                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10737741500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10737741500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1828416279                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1828416279                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       682500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       682500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12566157779                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12566157779                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12566840279                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12566840279                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015385                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015385                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1534341                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1534341                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1534352                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1534352                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15231288500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  15231288500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1828351773                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1828351773                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       681500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       681500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17059640273                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17059640273                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17060321773                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17060321773                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015381                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015381                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002689                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002689                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000156                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000156                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009164                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.009164                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009160                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.009160                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8173.737980                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8173.737980                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8286.312474                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8286.312474                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62045.454545                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62045.454545                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8189.927402                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8189.927402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8190.313499                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8190.313499                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009162                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.009162                       # mshr miss rate for demand accesses
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+system.cpu.dcache.overall_mshr_miss_rate::total     0.009159                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11594.314395                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11594.314395                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8286.020136                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8286.020136                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61954.545455                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61954.545455                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.545534                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.545534                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.909985                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.909985                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            715629                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.829471                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            88372474                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            716141                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            123.400942                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         326432500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.829471                       # Average occupied blocks per requestor
+system.cpu.icache.tags.replacements            715978                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.829667                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            88375700                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            716490                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            123.345336                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         330590500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.829667                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999667                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999667                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -839,208 +840,210 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          246
 system.cpu.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           69                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         178904656                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        178904656                       # Number of data accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8307.573670                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8307.573670                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8307.573670                       # average overall miss latency
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-system.cpu.icache.overall_avg_miss_latency::total  8307.573670                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        62233                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         178912379                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        178912379                       # Number of data accesses
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8980.401976                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8980.401976                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        66919                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2180                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2190                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    28.547248                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    30.556621                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    31.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         5641                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         5641                       # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716142                       # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008038                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7785.311370                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7785.311370                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7785.311370                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7785.311370                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7785.311370                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7785.311370                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       715978                       # number of writebacks
+system.cpu.icache.writebacks::total            715978                       # number of writebacks
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+system.cpu.icache.overall_mshr_miss_latency::total   6035132455                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008042                       # mshr miss rate for ReadReq accesses
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+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008042                       # mshr miss rate for demand accesses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8423.179712                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8423.179712                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8423.179712                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  8423.179712                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8423.179712                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  8423.179712                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       404899                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       404967                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit           62                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       404824                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       404865                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit           38                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        28121                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage        28167                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         5994.543426                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3840397                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             7305                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           525.721697                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         5610.545510                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3011470                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             6745                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           446.474426                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2575.183678                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2680.782296                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   613.575916                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   125.001536                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.157177                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.163622                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.037450                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.007629                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.365878                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          519                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         6786                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  5502.326452                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   108.219059                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.335835                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006605                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.342441                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          498                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1022::0           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::2          344                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          134                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          771                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          128                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5745                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.031677                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.414185                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         68224984                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        68224984                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       966339                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       966339                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3            2                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          906                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.tag_accesses         68984443                       # Number of tag accesses
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 system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       219861                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1312642                       # number of ReadSharedReq hits
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 system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
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-system.cpu.l2cache.ReadExReq_misses::cpu.data          792                       # number of ReadExReq misses
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23000                       # number of UpgradeReq miss cycles
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.500000                       # miss rate for UpgradeReq accesses
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+system.cpu.l2cache.demand_avg_miss_latency::total 70959.898848                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.371202                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70841.200619                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70959.898848                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1049,151 +1052,152 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           53                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total           53                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           34                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           34                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           87                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          100                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           87                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          100                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        30448                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        30448                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           44                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total           44                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           12                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           33                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           33                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           77                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           89                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           77                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           89                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        51607                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total        51607                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          739                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          739                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2922                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2922                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1023                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1023                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2922                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1762                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         4684                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2922                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1762                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        30448                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        35132                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    176616285                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    176616285                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        17000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        17000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     50771000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     50771000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    181268500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    181268500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     69264000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     69264000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    181268500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    120035000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    301303500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    181268500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    120035000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    176616285                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    477919785                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          728                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          728                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9697                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9697                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        71541                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        71541                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9697                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        72269                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        81966                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9697                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        72269                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        51607                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       133573                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    180856312                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    180856312                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        16500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        16500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     50141500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     50141500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    638751500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    638751500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4638052000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4638052000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    638751500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4688193500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5326945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    638751500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4688193500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    180856312                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5507801312                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003349                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003349                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004085                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004085                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000779                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000779                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004085                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.001148                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.002082                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004085                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.001148                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003299                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003299                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013544                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.054458                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.054458                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.047101                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.036424                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.047101                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.015617                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5800.587395                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  5800.587395                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        17000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        17000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68702.300406                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68702.300406                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62035.763176                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62035.763176                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67706.744868                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67706.744868                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62035.763176                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68124.290579                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64326.110162                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62035.763176                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68124.290579                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  5800.587395                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13603.546197                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.059358                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3504.491871                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3504.491871                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        16500                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        16500                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68875.686813                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68875.686813                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.042590                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.042590                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64830.684503                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64830.684503                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.042590                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64871.431734                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.690847                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.042590                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64871.431734                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3504.491871                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41234.391022                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4499965                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2249489                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       249352                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        27801                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        27801                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       2029841                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       966339                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      1033885                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        31840                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests      4500659                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2249836                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       249343                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       130203                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        52857                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        77346                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       2030188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       965413                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1035068                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        81238                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        52995                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       220653                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       220653                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       716142                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1313699                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2122562                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4377748                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6500310                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45775104                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    160044224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          205819328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       32746                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4531805                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.116184                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.320445                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       716491                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1313697                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2123993                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4377646                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6501639                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     90080128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    181970688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          272050816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      134761                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2385076                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.191571                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.468754                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            4005282     88.38%     88.38% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             526523     11.62%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2005511     84.09%     84.09% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             302219     12.67%     96.76% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              77346      3.24%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4531805                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     3216321500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1074578268                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2302086882                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        2385076                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4500145500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          3.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    1075017936                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2302043463                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               6592                       # Transaction distribution
+system.membus.trans_dist::ReadResp              83880                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               739                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              739                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          6592                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14664                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14664                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       469184                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  469184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               728                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              728                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         83880                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       169218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 169218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      5414912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 5414912                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7332                       # Request fanout histogram
+system.membus.snoop_fanout::samples             84609                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7332    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   84609    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7332                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9416916                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           38389399                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.membus.snoop_fanout::total               84609                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103435410                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          446650667                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index e29d83073..863619ff4 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.517243                       # Number of seconds simulated
-sim_ticks                                517243165500                       # Number of ticks simulated
-final_tick                               517243165500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.517291                       # Number of seconds simulated
+sim_ticks                                517291025500                       # Number of ticks simulated
+final_tick                               517291025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 702843                       # Simulator instruction rate (inst/s)
-host_op_rate                                   843789                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1332923086                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322968                       # Number of bytes of host memory used
-host_seconds                                   388.05                       # Real time elapsed on the host
+host_inst_rate                                 635145                       # Simulator instruction rate (inst/s)
+host_op_rate                                   762516                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1204648551                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 323584                       # Number of bytes of host memory used
+host_seconds                                   429.41                       # Real time elapsed on the host
 sim_insts                                   272739286                       # Number of instructions simulated
 sim_ops                                     327433744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          166912                       # Nu
 system.physmem.num_reads::cpu.inst               2608                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4224                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  6832                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               322695                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               522648                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  845343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          322695                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             322695                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              322695                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              522648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 845343                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               322666                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               522599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  845265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          322666                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             322666                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              322666                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              522599                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 845265                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -147,7 +147,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                       1034486331                       # number of cpu cycles simulated
+system.cpu.numCycles                       1034582051                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   272739286                       # Number of instructions committed
@@ -168,7 +168,7 @@ system.cpu.num_mem_refs                     168107847                       # nu
 system.cpu.num_load_insts                    85732248                       # Number of load instructions
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               1034486330.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               1034582050.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          30563503                       # Number of branches fetched
@@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  327812214                       # Class of executed instruction
 system.cpu.dcache.tags.replacements              1332                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3078.444355                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3078.335714                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4478                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          37597.056052                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3078.444355                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.751573                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.751573                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3078.335714                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.751547                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.751547                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
@@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data         4476                       # n
 system.cpu.dcache.demand_misses::total           4476                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         4479                       # number of overall misses
 system.cpu.dcache.overall_misses::total          4479                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     78469000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     78469000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    157423500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    157423500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    235892500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    235892500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    235892500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    235892500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     88052000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     88052000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    177422500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    177422500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    265474500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    265474500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    265474500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    265474500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     86235567                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
@@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000027                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52701.630920                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52666.331770                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59310.656836                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59270.931011                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4475
 system.cpu.dcache.demand_mshr_misses::total         4475                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     76826000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     76826000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    154551500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    154551500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       162000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       162000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    231377500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    231377500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    231539500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    231539500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     86402000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     86402000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    174550500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    174550500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       183000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       183000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    260952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    260952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    261135500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    261135500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -335,26 +335,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        61000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        61000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13796                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1766.007280                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1765.948116                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           348644750                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15603                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          22344.725373                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1766.007280                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.862308                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.862308                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1765.948116                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.862279                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.862279                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1807                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
@@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst        15603                       # n
 system.cpu.icache.demand_misses::total          15603                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15603                       # number of overall misses
 system.cpu.icache.overall_misses::total         15603                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    320168000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    320168000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    320168000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    320168000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    320168000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    320168000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    338446000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    338446000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    338446000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    338446000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    338446000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    338446000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    348660353                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    348660353                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    348660353                       # number of demand (read+write) accesses
@@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000045
 system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20519.643658                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20519.643658                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21691.085048                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21691.085048                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -408,44 +408,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks        13796                       # number of writebacks
+system.cpu.icache.writebacks::total             13796                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15603                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        15603                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        15603                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15603                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    304565000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    304565000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    304565000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    304565000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    304565000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    304565000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    322843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    322843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    322843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    322843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    322843000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    322843000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3487.764139                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         3487.622109                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              19775                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4882                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             4.050594                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   341.622938                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2407.426609                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   738.714591                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.010426                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073469                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.022544                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.106438                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   341.605293                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2407.328378                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   738.688437                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.010425                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073466                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.022543                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.106434                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4882                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           46                       # Occupied blocks per task id
@@ -455,8 +457,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3543
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148987                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           228106                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          228106                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          998                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          998                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks          998                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          998                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         6212                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         6212                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12995                       # number of ReadCleanReq hits
@@ -481,20 +485,22 @@ system.cpu.l2cache.demand_misses::total          6832                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2608                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         4224                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         6832                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    150075000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    150075000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    137027500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    137027500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     72007000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     72007000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    137027500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    222082000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    359109500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    137027500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    222082000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    359109500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          998                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          998                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    170070500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    170070500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    155292000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    155292000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     81591000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     81591000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    155292000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    251661500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    406953500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    155292000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    251661500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    406953500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          998                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          998                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         6212                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         6212                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         2872                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         2872                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15603                       # number of ReadCleanReq accesses(hits+misses)
@@ -519,18 +525,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.340222                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167147                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.943278                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.340222                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.268908                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.268908                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52541.219325                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52541.219325                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52636.695906                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52636.695906                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.219325                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.231061                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52562.865925                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.219325                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.231061                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52562.865925                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -551,18 +557,18 @@ system.cpu.l2cache.demand_mshr_misses::total         6832
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2608                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         4224                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         6832                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    121515000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    121515000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    110947500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    110947500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     58327000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     58327000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110947500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    179842000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    290789500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110947500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    179842000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    290789500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    141510500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    141510500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    129212000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    129212000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     67911000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     67911000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    129212000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    209421500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    338633500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    129212000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    209421500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    338633500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994429                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for ReadCleanReq accesses
@@ -575,18 +581,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.340222
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167147                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943278                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.340222                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42547.268908                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42547.268908                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42541.219325                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42636.695906                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42636.695906                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42576.231061                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42562.865925                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        35209                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        15221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -595,8 +601,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp         17209                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          998                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         6465                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          998                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         6212                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          253                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2872                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2872                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq        15603                       # Transaction distribution
@@ -604,22 +611,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq         1606
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        37418                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10207                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total             47625                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       998592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1396160                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       350464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1349056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1746624                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        35209                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.438041                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.496153                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        20081                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.386335                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.486921                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              19786     56.20%     56.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              15423     43.80%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              12323     61.37%     61.37% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               7758     38.63%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          35209                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       18602500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          20081                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       32398500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      23404500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
@@ -644,9 +651,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                6833                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7261500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             7281500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           34588500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           34160000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index dc4595f22..1ecb81d4d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.560940                       # Number of seconds simulated
-sim_ticks                                560939659000                       # Number of ticks simulated
-final_tick                               560939659000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.560955                       # Number of seconds simulated
+sim_ticks                                560955232000                       # Number of ticks simulated
+final_tick                               560955232000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 314051                       # Simulator instruction rate (inst/s)
-host_op_rate                                   314051                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              189670339                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308244                       # Number of bytes of host memory used
-host_seconds                                  2957.45                       # Real time elapsed on the host
+host_inst_rate                                 340981                       # Simulator instruction rate (inst/s)
+host_op_rate                                   340981                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              205940379                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308844                       # Number of bytes of host memory used
+host_seconds                                  2723.87                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            186816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18514112                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18700928                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       186816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          186816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            184896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18519872                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18704768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       184896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          184896                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2919                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289283                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292202                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2889                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289373                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292262                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               333041                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             33005532                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33338573                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          333041                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             333041                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7608148                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7608148                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7608148                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              333041                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            33005532                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40946722                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292202                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               329609                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             33014884                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                33344493                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          329609                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             329609                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7607937                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7607937                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7607937                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              329609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            33014884                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40952430                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292262                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292202                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292262                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18682112                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18816                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266368                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18700928                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18684608                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20160                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266752                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18704768                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      294                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      315                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18035                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18362                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18392                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18337                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18250                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18249                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18316                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18295                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18230                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18228                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18207                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18382                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18252                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18131                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18059                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18183                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         191173                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               18033                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18359                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18394                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18332                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18249                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18255                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18314                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18296                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18227                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18236                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18229                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18376                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18263                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18132                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18061                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18191                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4186                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4192                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    560939577000                       # Total gap between requests
+system.physmem.totGap                    560955208000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292202                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292262                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    291402                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       476                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    291448                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      940                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4047                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      933                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4051                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,43 +193,47 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       104019                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      220.607081                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     142.832345                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     268.107277                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          38319     36.84%     36.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43999     42.30%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8903      8.56%     87.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          723      0.70%     88.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       104067                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      220.533003                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     142.789866                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     268.043159                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          38344     36.85%     36.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        44004     42.28%     79.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8921      8.57%     87.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          721      0.69%     88.39% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::512-639         1372      1.32%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1141      1.10%     90.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          666      0.64%     91.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          599      0.58%     92.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8297      7.98%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         104019                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4049                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        70.696468                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.574169                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      760.359503                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4041     99.80%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            3      0.07%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383            3      0.07%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::640-767         1145      1.10%     90.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          668      0.64%     91.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          598      0.57%     92.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8294      7.97%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         104067                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4050                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        71.768889                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.564435                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      763.185509                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4041     99.78%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            4      0.10%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4049                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4049                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.463818                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.443063                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.844207                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3110     76.81%     76.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                939     23.19%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4049                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2923147000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8396422000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1459540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10013.93                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4050                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4050                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.461235                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.440549                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.842853                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3116     76.94%     76.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  1      0.02%     76.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                932     23.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4050                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2934449500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8408455750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459735000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10051.31                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28763.93                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28801.31                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          33.31                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           7.61                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       33.34                       # Average system read bandwidth in MiByte/s
@@ -239,71 +243,71 @@ system.physmem.busUtil                           0.32                       # Da
 system.physmem.busUtilRead                       0.26                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.30                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     202517                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     52027                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.38                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1563006.47                       # Average gap between requests
+system.physmem.avgWrQLen                        24.62                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     202530                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52011                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.37                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1562788.75                       # Average gap between requests
 system.physmem.pageHitRate                      70.98                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  392311080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  214058625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1140422400                       # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy                  392416920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  214116375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1140391200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            36637679520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           109190821365                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           240780947250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             388572678720                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.720364                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   399879041250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18730920000                       # Time in different power states
+system.physmem_0.refreshEnergy            36638696640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           109486358955                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           240531047250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             388619465820                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.784540                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   399461576500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18731440000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    142327335000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    142759852250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  394019640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  214990875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1136187000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215531280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            36637679520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           109681250220                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           240350746500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             388630405035                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              692.823275                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   399158044000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18730920000                       # Time in different power states
+system.physmem_1.actEnergy                  394276680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  215131125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1136522400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215570160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            36638696640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           109506441195                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           240513431250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             388620069450                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              692.785616                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   399429681750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     18731440000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    143048821000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    142792236250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               125747730                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          81143399                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12156451                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            103980487                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83512673                       # Number of BTB hits
+system.cpu.branchPred.lookups               125747709                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          81143389                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12156447                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            103980471                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                83512685                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.315716                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18691015                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             80.315740                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18691016                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               9451                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    237537770                       # DTB read hits
+system.cpu.dtb.read_hits                    237537764                       # DTB read hits
 system.cpu.dtb.read_misses                     198464                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                237736234                       # DTB read accesses
-system.cpu.dtb.write_hits                    98304947                       # DTB write hits
+system.cpu.dtb.read_accesses                237736228                       # DTB read accesses
+system.cpu.dtb.write_hits                    98304946                       # DTB write hits
 system.cpu.dtb.write_misses                      7177                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                98312124                       # DTB write accesses
-system.cpu.dtb.data_hits                    335842717                       # DTB hits
+system.cpu.dtb.write_accesses                98312123                       # DTB write accesses
+system.cpu.dtb.data_hits                    335842710                       # DTB hits
 system.cpu.dtb.data_misses                     205641                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                336048358                       # DTB accesses
-system.cpu.itb.fetch_hits                   316984864                       # ITB hits
+system.cpu.dtb.data_accesses                336048351                       # DTB accesses
+system.cpu.itb.fetch_hits                   316984906                       # ITB hits
 system.cpu.itb.fetch_misses                       120                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               316984984                       # ITB accesses
+system.cpu.itb.fetch_accesses               316985026                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -317,24 +321,24 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       1121879318                       # number of cpu cycles simulated
+system.cpu.numCycles                       1121910464                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928789150                       # Number of instructions committed
 system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      30861365                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      30861351                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.207895                       # CPI: cycles per instruction
-system.cpu.ipc                               0.827887                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1059707231                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        62172087                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.207928                       # CPI: cycles per instruction
+system.cpu.ipc                               0.827864                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1059707465                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        62202999                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            776530                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.727909                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           322866545                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4092.728000                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           322866540                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            780626                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            413.599528                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            413.599521                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         898816500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.727909                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.728000                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999201                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999201                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -344,40 +348,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          951
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         1242                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1642                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         648211884                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        648211884                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    224702500                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       224702500                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     98164045                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       98164045                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     322866545                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        322866545                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    322866545                       # number of overall hits
-system.cpu.dcache.overall_hits::total       322866545                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         648211872                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        648211872                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    224702494                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       224702494                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     98164046                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       98164046                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     322866540                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        322866540                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    322866540                       # number of overall hits
+system.cpu.dcache.overall_hits::total       322866540                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       711929                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        711929                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137155                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137155                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       849084                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         849084                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       849084                       # number of overall misses
-system.cpu.dcache.overall_misses::total        849084                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24888766500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24888766500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9955853000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9955853000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34844619500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34844619500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34844619500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34844619500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    225414429                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    225414429                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data       137154                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137154                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       849083                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         849083                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       849083                       # number of overall misses
+system.cpu.dcache.overall_misses::total        849083                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  24904735500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  24904735500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9954481000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9954481000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34859216500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34859216500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34859216500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34859216500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    225414423                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    225414423                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    323715629                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    323715629                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    323715629                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    323715629                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    323715623                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    323715623                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    323715623                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    323715623                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003158                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003158                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001395                       # miss rate for WriteReq accesses
@@ -386,14 +390,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002623
 system.cpu.dcache.demand_miss_rate::total     0.002623                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002623                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.618866                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.618866                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72588.334366                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72588.334366                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41037.894366                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41037.894366                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41037.894366                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41037.894366                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34982.049474                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34982.049474                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72578.860259                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72578.860259                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41055.134186                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41055.134186                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41055.134186                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41055.134186                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -402,16 +406,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88852                       # number of writebacks
-system.cpu.dcache.writebacks::total             88852                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        88497                       # number of writebacks
+system.cpu.dcache.writebacks::total             88497                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          314                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          314                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68144                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68144                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        68458                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        68458                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        68458                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        68458                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68143                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68143                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        68457                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        68457                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        68457                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        68457                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711615                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       711615                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69011                       # number of WriteReq MSHR misses
@@ -420,14 +424,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       780626
 system.cpu.dcache.demand_mshr_misses::total       780626                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       780626                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       780626                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24170053000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24170053000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4993475000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4993475000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29163528000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29163528000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29163528000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29163528000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24185998000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24185998000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4992658500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4992658500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29178656500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29178656500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29178656500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29178656500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003157                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003157                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
@@ -436,69 +440,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002411
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002411                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002411                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002411                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33965.069595                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33965.069595                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72357.667618                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72357.667618                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37359.155345                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37359.155345                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37359.155345                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37359.155345                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33987.476374                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33987.476374                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72345.836171                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72345.836171                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37378.535304                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 37378.535304                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37378.535304                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37378.535304                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             10565                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1685.376392                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           316972557                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             12306                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25757.561921                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             10567                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1685.376446                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           316972597                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12308                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          25753.379672                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1685.376392                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1685.376446                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.822938                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.822938                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1741                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1571                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1572                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.850098                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         633982034                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        633982034                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    316972557                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       316972557                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     316972557                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        316972557                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    316972557                       # number of overall hits
-system.cpu.icache.overall_hits::total       316972557                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12307                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12307                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12307                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12307                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12307                       # number of overall misses
-system.cpu.icache.overall_misses::total         12307                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    350414000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    350414000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    350414000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    350414000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    350414000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    350414000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    316984864                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    316984864                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    316984864                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    316984864                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    316984864                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    316984864                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         633982120                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        633982120                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    316972597                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       316972597                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     316972597                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        316972597                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    316972597                       # number of overall hits
+system.cpu.icache.overall_hits::total       316972597                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12309                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12309                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12309                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12309                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12309                       # number of overall misses
+system.cpu.icache.overall_misses::total         12309                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    349738000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    349738000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    349738000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    349738000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    349738000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    349738000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    316984906                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    316984906                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    316984906                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    316984906                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    316984906                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    316984906                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000039                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000039                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000039                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000039                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28472.739092                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28472.739092                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28472.739092                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28472.739092                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28472.739092                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28472.739092                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28413.193598                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28413.193598                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28413.193598                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28413.193598                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28413.193598                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28413.193598                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -507,129 +511,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12307                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12307                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        12307                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        12307                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        12307                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        12307                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    338108000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    338108000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    338108000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    338108000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    338108000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    338108000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks        10567                       # number of writebacks
+system.cpu.icache.writebacks::total             10567                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12309                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        12309                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        12309                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        12309                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        12309                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        12309                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    337430000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    337430000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    337430000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    337430000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    337430000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    337430000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27472.820346                       # average ReadReq mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 27413.274840                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           259423                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32592.990901                       # Cycle average of tags in use
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst    83.650991                       # Average occupied blocks per requestor
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -640,120 +650,121 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
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-system.cpu.l2cache.CleanEvict_mshr_misses::total          452                       # number of CleanEvict MSHR misses
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+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2890                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2890                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222728                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222728                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2890                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289373                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292263                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2890                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289373                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292263                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4197821500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4197821500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    191178500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    191178500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15757967000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15757967000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    191178500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19955788500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20146967000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    191178500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19955788500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20146967000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965716                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965716                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.237263                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.237263                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312863                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312863                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.237263                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370578                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.368509                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.237263                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370578                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.368509                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63000.045015                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63000.045015                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65717.636986                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65717.636986                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70706.606689                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70706.606689                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65717.636986                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68931.169478                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68899.056478                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.234788                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312989                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312989                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370694                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.368584                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370694                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.368584                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62987.793533                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62987.793533                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66151.730104                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70749.824899                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70749.824899                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68962.164749                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68934.374177                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68962.164749                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68934.374177                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1580028                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       787095                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1580032                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       787097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2077                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2077                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2079                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2079                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        723921                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       155535                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       890983                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        723923                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        10567                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       881285                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69011                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69011                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        12307                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        12309                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq       711615                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35178                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35184                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337782                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2372960                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       787584                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55646592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56434176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259423                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1839451                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001129                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.033584                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count::total           2372966                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1464000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55623872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           57087872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259935                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1052870                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001975                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.044393                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1837374     99.89%     99.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2077      0.11%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1050791     99.80%     99.80% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2079      0.20%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1839451                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      878866000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1052870                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      889080000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      18459000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      18462000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1170939000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1170939499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225557                       # Transaction distribution
-system.membus.trans_dist::Writeback             66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191114                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225617                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191173                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66645                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66645                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225557                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842201                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842201                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22968640                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22968640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225617                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842380                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842380                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22972480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22972480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            549999                       # Request fanout histogram
+system.membus.snoop_fanout::samples            550118                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  549999    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  550118    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              549999                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           918564500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              550118                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           918693000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1556125250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1556459000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 4dbf3fd00..ba9bff2cb 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.276406                       # Number of seconds simulated
-sim_ticks                                276406029500                       # Number of ticks simulated
-final_tick                               276406029500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.276414                       # Number of seconds simulated
+sim_ticks                                276414065500                       # Number of ticks simulated
+final_tick                               276414065500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 172081                       # Simulator instruction rate (inst/s)
-host_op_rate                                   172081                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               56464121                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308248                       # Number of bytes of host memory used
-host_seconds                                  4895.25                       # Real time elapsed on the host
+host_inst_rate                                 180346                       # Simulator instruction rate (inst/s)
+host_op_rate                                   180346                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59177560                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308352                       # Number of bytes of host memory used
+host_seconds                                  4670.93                       # Real time elapsed on the host
 sim_insts                                   842382029                       # Number of instructions simulated
 sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            173952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18519360                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18693312                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       173952                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          173952                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            172736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18523584                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18696320                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       172736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          172736                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2718                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289365                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292083                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2699                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289431                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292130                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               629335                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             67000564                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                67629900                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          629335                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             629335                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          15440011                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               15440011                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          15440011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              629335                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            67000564                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               83069910                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292083                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               624918                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             67013898                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                67638816                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          624918                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             624918                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          15439562                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               15439562                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          15439562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              624918                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            67013898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               83078377                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292130                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292083                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292130                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18672064                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21248                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266752                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18693312                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18675136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21184                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266432                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18696320                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      332                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      331                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18010                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18319                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18376                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18330                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18231                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18221                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18322                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18297                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18226                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18218                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18207                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18389                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18249                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18121                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         191079                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               18006                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18321                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18379                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18333                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18240                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18219                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18314                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18303                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18232                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18223                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18219                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18380                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18258                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18122                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              18052                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18183                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18198                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4192                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4187                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    276405940000                       # Total gap between requests
+system.physmem.totGap                    276414034500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292083                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292130                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,11 +97,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    216501                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     47240                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     27808                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       172                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    215201                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     47067                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29332                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       170                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      908                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4017                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4068                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4057                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4059                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      899                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      899                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4062                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4531                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       23                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -193,121 +193,120 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        99437                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      230.668262                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     148.414135                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     279.665008                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          34391     34.59%     34.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        42842     43.08%     77.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        10220     10.28%     87.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          417      0.42%     88.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          400      0.40%     88.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          621      0.62%     89.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          466      0.47%     89.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1450      1.46%     91.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8630      8.68%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          99437                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4053                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.663212                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.607328                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      761.755251                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4044     99.78%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        99419                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      230.737062                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     148.797862                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     278.058381                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          34339     34.54%     34.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        42571     42.82%     77.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9880      9.94%     87.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          767      0.77%     88.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1066      1.07%     89.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          606      0.61%     89.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          182      0.18%     89.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1419      1.43%     91.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8589      8.64%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          99419                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4054                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        70.841638                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.476950                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      763.295063                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4046     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            4      0.10%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            3      0.07%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383            2      0.05%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4053                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4053                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.449050                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.428679                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.836709                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3145     77.60%     77.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                905     22.33%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  2      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4053                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3647206250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9117537500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1458755000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12501.09                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4054                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4054                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.443759                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.423618                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.831866                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3155     77.82%     77.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  1      0.02%     77.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                896     22.10%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  2      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4054                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3656274250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9127505500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1458995000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12530.11                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31251.09                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          67.55                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          15.44                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       67.63                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31280.11                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          67.56                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          15.43                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       67.64                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                       15.44                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.65                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.53                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.12                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.13                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     206989                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51984                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.37                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     207034                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52000                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   70.95                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.96                       # Row buffer hit rate for writes
-system.physmem.avgGap                       770435.16                       # Average gap between requests
-system.physmem.pageHitRate                      72.25                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  373947840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  204039000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1139408400                       # Energy for read commands per rank (pJ)
+system.physmem.writeRowHitRate                  77.98                       # Row buffer hit rate for writes
+system.physmem.avgGap                       770356.80                       # Average gap between requests
+system.physmem.pageHitRate                      72.26                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  374197320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  204175125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1139463000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            18053371440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80174383695                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            95514202500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             195675791355                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              707.933114                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   158383013500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      9229740000                       # Time in different power states
+system.physmem_0.refreshEnergy            18053880000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80208829935                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            95488658250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             195685642110                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              707.948810                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   158328598000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      9230000000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    108791696000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    108853550750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  377742960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  206109750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1135890600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215570160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            18053371440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80329865445                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            95377815000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             195696365355                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              708.007549                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   158148138750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      9229740000                       # Time in different power states
+system.physmem_1.actEnergy                  377342280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  205891125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1136187000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215537760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            18053880000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80561309670                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            95179465500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             195729613335                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              708.107889                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   157816922000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      9230000000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    109026483750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    109365226750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               192576076                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         126054565                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          11561227                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            137875170                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               126274438                       # Number of BTB hits
+system.cpu.branchPred.lookups               192576024                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         126054494                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          11561226                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            137875105                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               126274367                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.586062                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                28678363                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                136                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             91.586053                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                28678385                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                133                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    242441387                       # DTB read hits
-system.cpu.dtb.read_misses                     312131                       # DTB read misses
+system.cpu.dtb.read_hits                    242441427                       # DTB read hits
+system.cpu.dtb.read_misses                     312020                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                242753518                       # DTB read accesses
-system.cpu.dtb.write_hits                   135445935                       # DTB write hits
+system.cpu.dtb.read_accesses                242753447                       # DTB read accesses
+system.cpu.dtb.write_hits                   135445847                       # DTB write hits
 system.cpu.dtb.write_misses                     31631                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               135477566                       # DTB write accesses
-system.cpu.dtb.data_hits                    377887322                       # DTB hits
-system.cpu.dtb.data_misses                     343762                       # DTB misses
+system.cpu.dtb.write_accesses               135477478                       # DTB write accesses
+system.cpu.dtb.data_hits                    377887274                       # DTB hits
+system.cpu.dtb.data_misses                     343651                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                378231084                       # DTB accesses
-system.cpu.itb.fetch_hits                   194828154                       # ITB hits
-system.cpu.itb.fetch_misses                       242                       # ITB misses
+system.cpu.dtb.data_accesses                378230925                       # DTB accesses
+system.cpu.itb.fetch_hits                   194827904                       # ITB hits
+system.cpu.itb.fetch_misses                       239                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               194828396                       # ITB accesses
+system.cpu.itb.fetch_accesses               194828143                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -321,98 +320,98 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                        552812060                       # number of cpu cycles simulated
+system.cpu.numCycles                        552828132                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          198850471                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1637321626                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   192576076                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          154952801                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     341917067                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                23591046                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles          198849781                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1637321417                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   192576024                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          154952752                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     341932468                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                23591048                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          6993                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles          6961                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 194828154                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               7885913                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          552570202                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.963102                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.176487                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                 194827904                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               7885927                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          552584882                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.963022                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.176483                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                236054473     42.72%     42.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29638362      5.36%     48.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 21702458      3.93%     52.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 35773228      6.47%     58.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 67707960     12.25%     70.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 21595876      3.91%     74.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 19328628      3.50%     78.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3978060      0.72%     78.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                116791157     21.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                236070631     42.72%     42.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29638226      5.36%     48.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 21699661      3.93%     52.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 35773155      6.47%     58.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 67709217     12.25%     70.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 21596173      3.91%     74.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 19328814      3.50%     78.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3978253      0.72%     78.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                116790752     21.14%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            552570202                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.348357                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.961805                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                166802287                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              90542864                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 271199395                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              12236841                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               11788815                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             15468328                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total            552584882                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.348347                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.961719                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                166809048                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              90546856                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 271205722                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              12234440                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               11788816                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             15468258                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                  6932                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1567838176                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 24969                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               11788815                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                173688859                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                60716441                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          13717                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276533617                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              29828753                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1529250735                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  8190                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2401406                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               20516503                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7198838                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1021411513                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1760089033                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1720202399                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          39886633                       # Number of floating rename lookups
+system.cpu.decode.DecodedInsts             1567837184                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 24953                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               11788816                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                173694356                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                60697364                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          13758                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 276538556                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              29852032                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1529249378                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  8057                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2407484                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               20532473                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7206116                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1021410389                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1760087391                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1720201095                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          39886295                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             638967158                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                382444355                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1364                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             84                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   9081858                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            369185264                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           173801333                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          40211283                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11128775                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1296786218                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  72                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1011356527                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           8787388                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       454404260                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    422537101                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             35                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     552570202                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.830277                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.913640                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                382443231                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1367                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             87                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   9068503                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            369184759                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           173801249                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          40216404                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11112363                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1296784829                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  74                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1011355981                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           8787623                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       454402873                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    422535596                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             37                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     552584882                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.830227                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.913668                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           197270443     35.70%     35.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            90785192     16.43%     52.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            90547416     16.39%     68.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            58763251     10.63%     79.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            57064914     10.33%     89.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            29634790      5.36%     94.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            16885134      3.06%     97.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             7510156      1.36%     99.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4108906      0.74%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           197292642     35.70%     35.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            90775823     16.43%     52.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            90545836     16.39%     68.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            58767814     10.64%     79.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            57065281     10.33%     89.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            29635375      5.36%     94.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            16880319      3.05%     97.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             7509205      1.36%     99.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4112587      0.74%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       552570202                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       552584882                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2519726     10.56%     10.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2519786     10.56%     10.56% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     10.56% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.56% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.56% # attempts to use FU when none available
@@ -441,16 +440,16 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.56% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.56% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.56% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               15983640     67.00%     77.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               5352814     22.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               15987276     67.00%     77.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               5353537     22.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              1276      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             577739239     57.13%     57.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             577738940     57.13%     57.13% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                 7929      0.00%     57.13% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            13232477      1.31%     58.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             3826542      0.38%     58.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            13232476      1.31%     58.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             3826543      0.38%     58.81% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt             3339799      0.33%     59.14% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.14% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.14% # Type of FU issued
@@ -475,84 +474,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.14% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.14% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            274563645     27.15%     86.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           138645616     13.71%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            274563490     27.15%     86.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           138645524     13.71%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1011356527                       # Type of FU issued
-system.cpu.iq.rate                           1.829476                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    23856180                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023588                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2536915249                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1709850818                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    936642710                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            71011575                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           41384719                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     34526976                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              998747828                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                36463603                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         49725855                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1011355981                       # Type of FU issued
+system.cpu.iq.rate                           1.829422                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    23860599                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023593                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2536933524                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1709848613                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    936642568                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            71011542                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           41384153                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     34526963                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              998751721                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                36463583                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         49725864                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    131674667                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses      1209013                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        45363                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     75500133                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    131674162                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses      1208593                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        45366                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     75500049                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads         2715                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4018                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked          4217                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               11788815                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                59738270                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                197040                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1470367053                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             17961                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             369185264                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            173801333                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 72                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  15881                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                192528                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          45363                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       11555967                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        14465                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             11570432                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             973002630                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             242753693                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          38353897                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               11788816                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                59730385                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                188341                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1470365584                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             17995                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             369184759                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            173801249                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 74                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  15707                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                184002                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          45366                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       11555966                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        14467                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11570433                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             973002254                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             242753622                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          38353727                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     173580763                       # number of nop insts executed
-system.cpu.iew.exec_refs                    378231547                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                128483828                       # Number of branches executed
-system.cpu.iew.exec_stores                  135477854                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.760097                       # Inst execution rate
-system.cpu.iew.wb_sent                      971735885                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     971169686                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 554962956                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 830927766                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     173580681                       # number of nop insts executed
+system.cpu.iew.exec_refs                    378231388                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                128483769                       # Number of branches executed
+system.cpu.iew.exec_stores                  135477766                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.760045                       # Inst execution rate
+system.cpu.iew.wb_sent                      971735602                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     971169531                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 554965093                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 830941176                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.756781                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.667884                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.756730                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.667875                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       534548617                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       534547076                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          11554520                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    481206030                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.929709                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.612045                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          11554519                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    481220935                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.929649                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.612057                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    204042568     42.40%     42.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    101511322     21.10%     63.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     52351761     10.88%     74.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     25424969      5.28%     79.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     20905527      4.34%     84.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      8991227      1.87%     85.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10032438      2.08%     87.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      6244738      1.30%     89.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     51701480     10.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    204061483     42.40%     42.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    101508829     21.09%     63.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     52351815     10.88%     74.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     25424424      5.28%     79.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     20903892      4.34%     84.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8988981      1.87%     85.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10032197      2.08%     87.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      6246270      1.30%     89.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     51703044     10.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    481206030                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    481220935                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            928587628                       # Number of instructions committed
 system.cpu.commit.committedOps              928587628                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -598,137 +597,137 @@ system.cpu.commit.op_class_0::MemWrite       98301200     10.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              51701480                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1890019657                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2997637733                       # The number of ROB writes
-system.cpu.timesIdled                            3185                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          241858                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              51703044                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1890031457                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2997634424                       # The number of ROB writes
+system.cpu.timesIdled                            3187                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          243250                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   842382029                       # Number of Instructions Simulated
 system.cpu.committedOps                     842382029                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.656249                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.656249                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.523813                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.523813                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1234257247                       # number of integer regfile reads
-system.cpu.int_regfile_writes               703449538                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  36844878                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 24462480                       # number of floating regfile writes
+system.cpu.cpi                               0.656268                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.656268                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.523768                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.523768                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1234256884                       # number of integer regfile reads
+system.cpu.int_regfile_writes               703449505                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  36844868                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 24462479                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            777154                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.899235                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           288564425                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            781250                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            369.362464                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         369553500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.899235                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999243                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999243                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            777152                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.896824                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           288563683                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            781248                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            369.362460                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         369982500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.896824                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999242                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999242                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          968                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2490                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2491                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4          256                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         582801760                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        582801760                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    191156368                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       191156368                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     97408043                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       97408043                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         582801420                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        582801420                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    191154367                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       191154367                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     97409302                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       97409302                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           14                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           14                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     288564411                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        288564411                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    288564411                       # number of overall hits
-system.cpu.dcache.overall_hits::total       288564411                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1552672                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1552672                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       893157                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       893157                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     288563669                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        288563669                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    288563669                       # number of overall hits
+system.cpu.dcache.overall_hits::total       288563669                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1554504                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1554504                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       891898                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       891898                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2445829                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2445829                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2445829                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2445829                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  83271101000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  83271101000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  62352545333                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  62352545333                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      2446402                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2446402                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2446402                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2446402                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  83607056000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  83607056000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  61973215333                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  61973215333                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        82500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        82500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145623646333                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145623646333                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145623646333                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145623646333                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    192709040                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    192709040                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 145580271333                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 145580271333                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 145580271333                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 145580271333                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    192708871                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    192708871                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data           15                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           15                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    291010240                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    291010240                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    291010240                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    291010240                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008057                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.008057                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009086                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009086                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    291010071                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    291010071                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    291010071                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    291010071                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008067                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.008067                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009073                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009073                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.066667                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.066667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008405                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008405                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008405                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008405                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53630.838323                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53630.838323                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69811.405311                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69811.405311                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008407                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008407                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008407                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008407                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53783.750959                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53783.750959                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69484.644357                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69484.644357                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        82500                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        82500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59539.586101                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59539.586101                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59539.586101                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59539.586101                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        22515                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        72899                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               341                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59507.910529                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59507.910529                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59507.910529                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59507.910529                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        23437                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        62248                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               339                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets             517                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.026393                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   141.003868                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    69.135693                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   120.402321                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88880                       # number of writebacks
-system.cpu.dcache.writebacks::total             88880                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       840227                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       840227                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       824352                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       824352                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        88616                       # number of writebacks
+system.cpu.dcache.writebacks::total             88616                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842060                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       842060                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       823094                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       823094                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1664579                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1664579                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1664579                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1664579                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712445                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712445                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68805                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        68805                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       781250                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       781250                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       781250                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       781250                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24193547500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24193547500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5688085497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5688085497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29881632997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29881632997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29881632997                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29881632997                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data      1665154                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1665154                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1665154                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1665154                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712444                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712444                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68804                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        68804                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       781248                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       781248                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       781248                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       781248                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24228621500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24228621500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5666649497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5666649497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29895270997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29895270997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29895270997                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29895270997                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003697                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003697                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000700                       # mshr miss rate for WriteReq accesses
@@ -737,69 +736,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002685
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002685                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002685                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33958.477497                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33958.477497                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82669.653325                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82669.653325                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38248.490236                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 38248.490236                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38248.490236                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 38248.490236                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34007.755697                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34007.755697                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82359.303195                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82359.303195                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38266.044837                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38266.044837                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38266.044837                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38266.044837                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              4598                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1641.391736                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           194819915                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6300                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          30923.796032                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4602                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1641.296070                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           194819661                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6304                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          30904.134042                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1641.391736                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801461                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801461                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1641.296070                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801414                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801414                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1702                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           81                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1537                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1535                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.831055                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         389662608                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        389662608                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    194819915                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       194819915                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     194819915                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        194819915                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    194819915                       # number of overall hits
-system.cpu.icache.overall_hits::total       194819915                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8239                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8239                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8239                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8239                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8239                       # number of overall misses
-system.cpu.icache.overall_misses::total          8239                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    351244499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    351244499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    351244499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    351244499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    351244499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    351244499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    194828154                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    194828154                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    194828154                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    194828154                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total    194828154                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         389662112                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        389662112                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    194819661                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       194819661                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total       194819661                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8243                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::total          8243                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    351192999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    351192999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    351192999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    351192999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    351192999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    351192999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    194827904                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    194827904                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    194827904                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    194827904                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    194827904                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    194827904                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000042                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000042                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42631.933366                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42631.933366                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42631.933366                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42631.933366                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42631.933366                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42631.933366                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42604.998059                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42604.998059                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42604.998059                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42604.998059                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42604.998059                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42604.998059                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          510                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
@@ -808,135 +807,141 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs    46.363636
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks         4602                       # number of writebacks
+system.cpu.icache.writebacks::total              4602                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1938                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total         1938                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst         1938                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_hits::total         1938                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst         1938                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total         1938                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6301                       # number of ReadReq MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000032                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 41448.341374                       # average overall mshr miss latency
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 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           259305                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32630.134515                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1207948                       # Total number of references to valid blocks.
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-system.cpu.l2cache.tags.avg_refs             4.136199                       # Average number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2512.609153                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    65.430826                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30052.094536                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32738                       # Occupied blocks per task id
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-system.cpu.l2cache.tags.data_accesses        12915272                       # Number of data accesses
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-system.cpu.l2cache.Writeback_hits::total        88880                       # number of Writeback hits
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81376.241660                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81356.477060                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -947,120 +952,121 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          394                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          394                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66627                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66627                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2719                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2719                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222738                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222738                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2719                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       289365                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292084                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2719                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       289365                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292084                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4895483000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4895483000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    186901500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    186901500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15750212000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15750212000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    186901500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20645695000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20832596500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    186901500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20645695000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20832596500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66626                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66626                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2700                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2700                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222805                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222805                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2700                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289431                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292131                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2700                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289431                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292131                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4874043500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4874043500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    186952000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    186952000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15784453500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15784453500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    186952000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20658497000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20845449000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    186952000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20658497000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20845449000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.968345                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.968345                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.431519                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312639                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312639                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370387                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.370876                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370387                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.370876                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73475.963198                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73475.963198                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68739.058477                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70711.831838                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70711.831838                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71348.279854                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71323.990701                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.428232                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312733                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312733                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370473                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.370935                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370473                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.370935                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73155.277219                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73155.277219                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69241.481481                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70844.251700                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70844.251700                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71376.241660                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71356.511291                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71376.241660                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71356.511291                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1569303                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       781752                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1569307                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       781754                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1986                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1986                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1989                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1989                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        718745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       155563                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       885494                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        68805                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        68805                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         6301                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       712445                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17199                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2339654                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2356853                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       403200                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55688320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56091520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259305                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1828608                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001086                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.032938                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        718748                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155299                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         4602                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       881602                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        68804                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        68804                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         6305                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       712444                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17211                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2339648                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2356859                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       697984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55671296                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56369280                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259749                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1047302                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001899                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.043538                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1826622     99.89%     99.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1986      0.11%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1045313     99.81%     99.81% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1989      0.19%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1828608                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      873531500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1047302                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      877871500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       9450000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       9456000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1171875499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1171872499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225456                       # Transaction distribution
-system.membus.trans_dist::Writeback             66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191030                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66627                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66627                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225456                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       841879                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 841879                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22961024                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22961024                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             225504                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191079                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66626                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66626                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        225504                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842022                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842022                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22964032                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22964032                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            549796                       # Request fanout histogram
+system.membus.snoop_fanout::samples            549892                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  549796    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  549892    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              549796                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           880960000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              549892                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           880924000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1551840500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1551641250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index f1fff22ed..5e6b1a1be 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.286279                       # Number of seconds simulated
-sim_ticks                                1286278511500                       # Number of ticks simulated
-final_tick                               1286278511500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.288319                       # Number of seconds simulated
+sim_ticks                                1288319411500                       # Number of ticks simulated
+final_tick                               1288319411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1389844                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1389844                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1925210162                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305148                       # Number of bytes of host memory used
-host_seconds                                   668.12                       # Real time elapsed on the host
+host_inst_rate                                1465054                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1465054                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2032611527                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306300                       # Number of bytes of host memory used
+host_seconds                                   633.82                       # Real time elapsed on the host
 sim_insts                                   928587629                       # Number of instructions simulated
 sim_ops                                     928587629                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            137792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18509184                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18646976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       137792                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          137792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            137024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18511872                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18648896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       137024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          137024                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2153                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289206                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291359                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2141                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289248                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291389                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               107125                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             14389717                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14496842                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          107125                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             107125                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3317876                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3317876                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3317876                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              107125                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            14389717                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17814717                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               106359                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             14369008                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14475367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          106359                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             106359                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3312619                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3312619                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3312619                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              106359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            14369008                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17787986                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -70,7 +70,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       2572557023                       # number of cpu cycles simulated
+system.cpu.numCycles                       2576638823                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928587629                       # Number of instructions committed
@@ -89,7 +89,7 @@ system.cpu.num_mem_refs                     336013318                       # nu
 system.cpu.num_load_insts                   237705247                       # Number of load instructions
 system.cpu.num_store_insts                   98308071                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 2572557023                       # Number of busy cycles
+system.cpu.num_busy_cycles                 2576638823                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         123111018                       # Number of branches fetched
@@ -129,19 +129,19 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  928789150                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            776432                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.261358                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4094.180330                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           335031269                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            780528                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            429.236708                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1046537500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.261358                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999576                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999576                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle        1104319500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4094.180330                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999556                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999556                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          153                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          468                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          993                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          467                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          995                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         2427                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         672404122                       # Number of tag accesses
@@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data       780528                       # n
 system.cpu.dcache.demand_misses::total         780528                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       780528                       # number of overall misses
 system.cpu.dcache.overall_misses::total        780528                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18597166000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18597166000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3696410000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3696410000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22293576000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22293576000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22293576000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22293576000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  20157098000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  20157098000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4162936000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4162936000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  24320034000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24320034000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  24320034000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24320034000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    237510597                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    237510597                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
@@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002324
 system.cpu.dcache.demand_miss_rate::total     0.002324                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002324                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002324                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26137.456185                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26137.456185                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.292115                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.292115                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28562.173298                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28562.173298                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28562.173298                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28562.173298                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31158.438903                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31158.438903                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        89031                       # number of writebacks
-system.cpu.dcache.writebacks::total             89031                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        88866                       # number of writebacks
+system.cpu.dcache.writebacks::total             88866                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711514                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       711514                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69014                       # number of WriteReq MSHR misses
@@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       780528
 system.cpu.dcache.demand_mshr_misses::total       780528                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       780528                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       780528                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17885652000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17885652000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3627396000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3627396000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21513048000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21513048000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21513048000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  21513048000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  19445584000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  19445584000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4093922000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4093922000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23539506000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23539506000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23539506000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  23539506000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002996                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002996                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
@@ -228,24 +228,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002324
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002324                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002324                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002324                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25137.456185                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25137.456185                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52560.292115                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52560.292115                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27562.173298                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27562.173298                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27562.173298                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27562.173298                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              4618                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1474.486224                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1474.418872                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           928782983                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              6168                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          150580.898671                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1474.486224                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.719964                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.719964                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1474.418872                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.719931                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.719931                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1550                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           72                       # Occupied blocks per task id
@@ -266,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst         6168                       # n
 system.cpu.icache.demand_misses::total           6168                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         6168                       # number of overall misses
 system.cpu.icache.overall_misses::total          6168                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    170684500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    170684500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    170684500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    170684500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    170684500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    170684500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    185126500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    185126500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    185126500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    185126500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    185126500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    185126500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    928789151                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    928789151                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    928789151                       # number of demand (read+write) accesses
@@ -284,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000007
 system.cpu.icache.demand_miss_rate::total     0.000007                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000007                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000007                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27672.584306                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 27672.584306                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 27672.584306                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 27672.584306                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 27672.584306                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 27672.584306                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 30014.023995                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 30014.023995                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -298,93 +298,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks         4618                       # number of writebacks
+system.cpu.icache.writebacks::total              4618                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6168                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         6168                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         6168                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         6168                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         6168                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         6168                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    164516500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    164516500                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000007                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000007                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000007                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26672.584306                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26672.584306                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26672.584306                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26672.584306                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26672.584306                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 26672.584306                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           258580                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32657.927159                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1207050                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           291314                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.143467                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           258847                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32654.651136                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1207020                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           291581                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.139570                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2486.879631                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    49.811890                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30121.235638                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.075894                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001520                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.919227                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996641                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2500.518191                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.076310                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32734                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          117                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1144                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31198                       # Occupied blocks per task id
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31154                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998962                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         12902296                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        12902296                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks        89031                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        89031                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         12902563                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        12902563                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks        88866                       # number of WritebackDirty hits
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 system.cpu.l2cache.ReadExReq_hits::cpu.data         2366                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    113105000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    113105000                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data  15183375000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data  15183375000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  15296480000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks        89031                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        89031                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.demand_miss_latency::cpu.inst    127415500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  17210268500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  17337684000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    127415500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  17210268500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  17337684000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        88866                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        88866                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         4618                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         4618                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69014                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69014                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6168                       # number of ReadCleanReq accesses(hits+misses)
@@ -399,28 +405,28 @@ system.cpu.l2cache.overall_accesses::cpu.data       780528
 system.cpu.l2cache.overall_accesses::total       786696                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965717                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.965717                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.349060                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.349060                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312795                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312795                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.349060                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.370526                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.370358                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.349060                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.370526                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.370358                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.180050                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.180050                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52533.673943                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52533.673943                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.215674                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.215674                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52533.673943                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.207465                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.454765                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52533.673943                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.207465                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.454765                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.347114                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.347114                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312854                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312854                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.347114                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.370580                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.370396                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.347114                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.370580                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.370396                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -431,58 +437,58 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          238                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          238                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66648                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66648                       # number of ReadExReq MSHR misses
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     91575000                       # number of ReadCleanReq MSHR miss cycles
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-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   9458763000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   9458763000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     91575000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12291315000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  12382890000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     91575000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12291315000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  12382890000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2141                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2141                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222600                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222600                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2141                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289248                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       291389                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2141                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289248                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       291389                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3299077000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3299077000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    106005500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    106005500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  11018711500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  11018711500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    106005500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14317788500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  14423794000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    106005500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14317788500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14423794000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965717                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965717                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.349060                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312795                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312795                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370526                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.370358                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.349060                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370526                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.370358                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.180050                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.180050                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42533.673943                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42533.673943                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.215674                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.215674                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42533.673943                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.207465                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.454765                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.347114                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.347114                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312854                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312854                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.347114                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370580                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.370396                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.347114                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370580                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.370396                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1567746                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       781050                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -491,8 +497,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops         1718                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1718                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        717682                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       155714                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       883916                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155549                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         4618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       879730                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69014                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69014                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         6168                       # Transaction distribution
@@ -500,51 +507,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq       711514
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        16954                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337488                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           2354442                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       394752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55651776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56046528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      258580                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1826326                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000941                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.030656                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       690304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55641216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56331520                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      258847                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1045543                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001643                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.040503                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1824608     99.91%     99.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1718      0.09%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1043825     99.84%     99.84% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1718      0.16%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1826326                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      872904000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1045543                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      877357000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       9252000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1170792000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             224711                       # Transaction distribution
-system.membus.trans_dist::Writeback             66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           190417                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224741                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190447                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66648                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66648                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        224711                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839818                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 839818                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22914688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22914688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        224741                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839908                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 839908                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22916608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22916608                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            548514                       # Request fanout histogram
+system.membus.snoop_fanout::samples            548519                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  548514    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  548519    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              548514                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           815261292                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              548519                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           815264000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1456808792                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1456945000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index ca22b895a..c95abda26 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.542258                       # Number of seconds simulated
-sim_ticks                                542257676500                       # Number of ticks simulated
-final_tick                               542257676500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.542265                       # Number of seconds simulated
+sim_ticks                                542265386500                       # Number of ticks simulated
+final_tick                               542265386500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 169610                       # Simulator instruction rate (inst/s)
-host_op_rate                                   208813                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              143560034                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 325880                       # Number of bytes of host memory used
-host_seconds                                  3777.22                       # Real time elapsed on the host
+host_inst_rate                                 179877                       # Simulator instruction rate (inst/s)
+host_op_rate                                   221452                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              152251725                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 325476                       # Number of bytes of host memory used
+host_seconds                                  3561.64                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            164608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18470592                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18635200                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       164608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          164608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            163584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18474304                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18637888                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       163584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          163584                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2572                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288603                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291175                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2556                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288661                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291217                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               303560                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             34062389                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                34365950                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          303560                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             303560                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7801221                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7801221                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7801221                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              303560                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            34062389                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42167171                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        291175                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               301668                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             34068750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                34370418                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          301668                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             301668                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7801110                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7801110                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7801110                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              301668                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            34068750                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42171528                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        291217                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      291175                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      291217                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18614336                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20864                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228480                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18635200                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18617600                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20288                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228800                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18637888                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      326                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      317                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18282                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18135                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         190686                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               18283                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18129                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               18220                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18173                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18273                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18400                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18176                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17989                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18184                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18283                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18405                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18181                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17993                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               18030                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18057                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18104                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18195                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18214                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18267                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18058                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18107                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18199                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18220                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18271                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18257                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18260                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4098                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4099                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                4222                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4092                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4097                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    542257582000                       # Total gap between requests
+system.physmem.totGap                    542265360500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  291175                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  291217                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,8 +97,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290458                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       377                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290512                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       374                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      894                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4016                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4019                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     4018                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4019                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                     4018                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4017                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4018                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,43 +193,42 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       111013                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      205.748588                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     133.953680                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     256.656452                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          45849     41.30%     41.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43580     39.26%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9433      8.50%     89.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1634      1.47%     90.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          691      0.62%     91.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          667      0.60%     91.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          515      0.46%     92.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          550      0.50%     92.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8094      7.29%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         111013                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4017                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.510331                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.246707                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.588684                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4015     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       111115                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      205.591972                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.871353                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     256.553383                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          45879     41.29%     41.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43676     39.31%     80.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9414      8.47%     89.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1626      1.46%     90.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          693      0.62%     91.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          670      0.60%     91.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          515      0.46%     92.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          551      0.50%     92.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8091      7.28%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         111115                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4018                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.511200                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.259636                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      506.474106                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4016     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4017                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4017                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.447598                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.427351                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.833980                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3118     77.62%     77.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  1      0.02%     77.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                897     22.33%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4017                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2868100000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8321518750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1454245000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9861.13                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4018                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4018                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.444749                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.424614                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.831636                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3124     77.75%     77.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  1      0.02%     77.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                893     22.22%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4018                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2873170250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8327545250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1454500000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9876.83                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28611.13                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28626.83                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          34.33                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           7.80                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       34.37                       # Average system read bandwidth in MiByte/s
@@ -239,49 +238,49 @@ system.physmem.busUtil                           0.33                       # Da
 system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.15                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194250                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51642                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   66.79                       # Row buffer hit rate for reads
+system.physmem.avgWrQLen                        23.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     194203                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51643                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   66.76                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  78.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1517768.15                       # Average gap between requests
-system.physmem.pageHitRate                      68.89                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  419905080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  229114875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1135859400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                215518320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            35417135520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           107383469355                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           231154143750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             375955146300                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              693.324021                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   383844481500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18106920000                       # Time in different power states
+system.physmem.avgGap                      1517611.52                       # Average gap between requests
+system.physmem.pageHitRate                      68.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  420789600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  229597500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1136101200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                215537760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            35417644080                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           107646010785                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           230928516000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             375994196925                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              693.386081                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   383467912500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18107180000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    140298894750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    140682990000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  419254920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  228760125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1132255800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212615280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            35417135520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           107988829875                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           230623125750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             376021977270                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              693.447269                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   382962347750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18106920000                       # Time in different power states
+system.physmem_1.actEnergy                  419141520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  228698250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1132419600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212628240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            35417644080                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           107856715275                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           230743687500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             376010934465                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              693.416947                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   383162755000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     18107180000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    141184235750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    140991278500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               154805770                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         105138293                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups               154805774                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         105138294                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          12875884                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90693367                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups             90693368                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                83089320                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.615653                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19277594                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             91.615652                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19277596                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               1316                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -401,24 +400,24 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       1084515353                       # number of cpu cycles simulated
+system.cpu.numCycles                       1084530773                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655085                       # Number of instructions committed
 system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                      23906784                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.692823                       # CPI: cycles per instruction
-system.cpu.ipc                               0.590729                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1025899498                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        58615855                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.692847                       # CPI: cycles per instruction
+system.cpu.ipc                               0.590721                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1025899528                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        58631245                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            778339                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.484054                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4092.484104                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           378456435                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            782435                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            483.690575                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         792553500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.484054                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.484104                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999142                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999142                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -454,14 +453,14 @@ system.cpu.dcache.demand_misses::cpu.data       851588                       # n
 system.cpu.dcache.demand_misses::total         851588                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       851729                       # number of overall misses
 system.cpu.dcache.overall_misses::total        851729                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24762143500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24762143500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10105570000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10105570000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34867713500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34867713500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34867713500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34867713500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  24770851500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  24770851500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10105356000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10105356000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34876207500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34876207500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34876207500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34876207500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    250341582                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    250341582                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
@@ -486,14 +485,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002245
 system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002246                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002246                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40944.345740                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40937.567583                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34699.095501                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34699.095501                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73380.359010                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73380.359010                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40954.320047                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40954.320047                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40947.540239                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40947.540239                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -502,8 +501,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88920                       # number of writebacks
-system.cpu.dcache.writebacks::total             88920                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        88693                       # number of writebacks
+system.cpu.dcache.writebacks::total             88693                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          902                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          902                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
@@ -522,16 +521,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       782296
 system.cpu.dcache.demand_mshr_misses::total       782296                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       782435                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       782435                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24033231500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24033231500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5067791500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5067791500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1855000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1855000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29101023000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29101023000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29102878000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29102878000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24041947500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24041947500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5067670500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5067670500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1788000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1788000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29109618000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29109618000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29111406000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29111406000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
@@ -542,24 +541,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002063
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002063                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33720.651104                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33720.651104                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73103.351029                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73103.351029                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37210.490658                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 37210.490658                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37206.165368                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37206.165368                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             23591                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1713.095615                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           291576499                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1713.095631                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           291576507                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             25342                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11505.662497                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11505.662813                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1713.095615                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1713.095631                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.836472                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.836472                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
@@ -567,44 +566,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           58
 system.cpu.icache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1600                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         583229026                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        583229026                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    291576499                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       291576499                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     291576499                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        291576499                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    291576499                       # number of overall hits
-system.cpu.icache.overall_hits::total       291576499                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         583229042                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        583229042                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    291576507                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       291576507                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     291576507                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        291576507                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    291576507                       # number of overall hits
+system.cpu.icache.overall_hits::total       291576507                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        25343                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         25343                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        25343                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          25343                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        25343                       # number of overall misses
 system.cpu.icache.overall_misses::total         25343                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    499290500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    499290500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    499290500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    499290500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    499290500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    499290500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    291601842                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    291601842                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    291601842                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    291601842                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    291601842                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    291601842                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    498728500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    498728500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    498728500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    498728500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    498728500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    498728500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    291601850                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    291601850                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    291601850                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    291601850                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    291601850                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    291601850                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19701.317918                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19701.317918                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19679.142169                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19679.142169                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19679.142169                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19679.142169                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19679.142169                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19679.142169                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -613,93 +612,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks        23591                       # number of writebacks
+system.cpu.icache.writebacks::total             23591                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25343                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        25343                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        25343                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total        25343                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        25343                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        25343                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    473948500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    473948500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    473948500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    473948500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    473948500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    473948500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    473386500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    473386500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    473386500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    473386500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    473386500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    473386500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18679.181628                       # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18679.181628                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18679.181628                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18679.181628                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18679.181628                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           258395                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32574.709394                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1245326                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           291139                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.277428                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           258813                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32576.208282                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1245284                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           291557                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.271151                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2589.156414                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    89.726448                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.079015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002738                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.912348                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994101                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.occ_blocks::cpu.data 29886.983669                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.079452                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2812                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29412                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29319                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13211317                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13211317                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks        88920                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        88920                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         13211735                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13211735                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks        88693                       # number of WritebackDirty hits
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 system.cpu.l2cache.ReadExReq_hits::cpu.data         3231                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        22765                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        22765                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490574                       # number of ReadSharedReq hits
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-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4929880500                       # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    195624000                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17812302500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  17812302500                       # number of ReadSharedReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data  22742183000                       # number of demand (read+write) miss cycles
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-system.cpu.l2cache.overall_miss_latency::cpu.data  22742183000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  22937807000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks        88920                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        88920                       # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    194891500                       # number of ReadCleanReq miss cycles
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+system.cpu.l2cache.ReadSharedReq_miss_latency::total  17821559500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    194891500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  22751319000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  22946210500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    194891500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  22751319000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  22946210500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        88693                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        88693                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        22257                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        22257                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69322                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69322                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        25343                       # number of ReadCleanReq accesses(hits+misses)
@@ -714,28 +719,28 @@ system.cpu.l2cache.overall_accesses::cpu.data       782435
 system.cpu.l2cache.overall_accesses::total       807778                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953391                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.101724                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.101724                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312067                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312067                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.101724                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.368887                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.360505                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.101724                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.368887                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.360505                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.101093                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.101093                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312148                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312148                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.101093                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.368961                       # miss rate for demand accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.data     0.368961                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.360557                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74590.481306                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74590.481306                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76070.062451                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76070.062451                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80061.993198                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80061.993198                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76070.062451                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78809.368592                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78785.272103                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76070.062451                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78809.368592                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78785.272103                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -756,58 +761,54 @@ system.cpu.l2cache.demand_mshr_hits::total           32                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           27                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           32                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          376                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          376                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66091                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2573                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2573                       # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.overall_mshr_miss_latency::total  20023978000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4268849500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    169007000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    169007000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15594098500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15594098500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    169007000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19862948000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20031955000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    169007000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19862948000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20031955000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.101527                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.101527                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312029                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312029                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101527                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368852                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.360465                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101527                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368852                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.360465                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.100896                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312110                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312110                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368926                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.360517                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368926                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.360517                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64590.481306                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64590.481306                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66095.815409                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70063.793413                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70063.793413                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68810.639470                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68786.802327                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68810.639470                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68786.802327                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1609708                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       801990                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -816,8 +817,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops         2028                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2013                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           15                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        738455                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       155018                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       901956                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       154791                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        22257                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       880344                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq        25343                       # Transaction distribution
@@ -825,51 +827,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq       713113
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        72942                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2341192                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           2414134                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1621888                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55766720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           57388608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      258395                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1868103                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.004713                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.068609                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3046336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55752192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           58798528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      258813                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1066591                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.005113                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.071523                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1859313     99.53%     99.53% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               8775      0.47%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1061152     99.49%     99.49% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               5424      0.51%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                 15      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1868103                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      893774000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1066591                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      917138000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      38015495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1173665973                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225084                       # Transaction distribution
-system.membus.trans_dist::Writeback             66098                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           190644                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225126                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190686                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225084                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839092                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 839092                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22865472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22865472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225126                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 839218                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22868160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22868160                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            547917                       # Request fanout histogram
+system.membus.snoop_fanout::samples            548001                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  547917    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  548001    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              547917                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           917954000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              548001                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           918049500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1554429500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1554665000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 8ea31b650..52d6cf15b 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,83 +1,83 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.410968                       # Number of seconds simulated
-sim_ticks                                410968419000                       # Number of ticks simulated
-final_tick                               410968419000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.452586                       # Number of seconds simulated
+sim_ticks                                452585997000                       # Number of ticks simulated
+final_tick                               452585997000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  85599                       # Simulator instruction rate (inst/s)
-host_op_rate                                   105384                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54910730                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322152                       # Number of bytes of host memory used
-host_seconds                                  7484.30                       # Real time elapsed on the host
+host_inst_rate                                  89374                       # Simulator instruction rate (inst/s)
+host_op_rate                                   110031                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63138171                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 323296                       # Number of bytes of host memory used
+host_seconds                                  7168.18                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            226432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7007424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     12927040                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             20160896                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       226432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          226432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4244672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4244672                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3538                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             109491                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       201985                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                315014                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66323                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66323                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               550972                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             17051004                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     31455069                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                49057044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          550972                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             550972                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          10328463                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               10328463                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          10328463                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              550972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            17051004                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     31455069                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               59385507                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        315014                       # Number of read requests accepted
-system.physmem.writeReqs                        66323                       # Number of write requests accepted
-system.physmem.readBursts                      315014                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66323                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 20141440                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19456                       # Total number of bytes read from write queue
+system.physmem.bytes_read::cpu.inst            234368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          47997568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     12828032                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             61059968                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       234368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          234368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4243520                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4243520                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3662                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             749962                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       200438                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                954062                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66305                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66305                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               517842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            106051818                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     28343855                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               134913516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          517842                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             517842                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           9376163                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                9376163                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           9376163                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              517842                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           106051818                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     28343855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              144289678                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        954063                       # Number of read requests accepted
+system.physmem.writeReqs                        66305                       # Number of write requests accepted
+system.physmem.readBursts                      954063                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66305                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 61041664                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     18368                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                   4238400                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  20160896                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4244672                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      304                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      67                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             16                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               19880                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               19436                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               19769                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               19866                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               19687                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               20154                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               19548                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               19410                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               19409                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               19464                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              19401                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              19757                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              19512                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              19953                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              19499                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              19965                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4261                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4104                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4143                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4151                       # Per bank write bursts
+system.physmem.bytesReadSys                  61060032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4243520                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      287                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      63                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         227627                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               19636                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               19225                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              656809                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               20104                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               19566                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               20746                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               19449                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               19830                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               19282                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               19792                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              19287                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              19476                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              19427                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              20933                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              19357                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              20857                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4254                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4108                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4140                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4154                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                4243                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4228                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4230                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4095                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -86,35 +86,35 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4153                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    410968364500                       # Total gap between requests
+system.physmem.totGap                    452585986500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  315014                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  954063                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66323                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    121710                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    120019                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14305                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      6741                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6431                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7602                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8833                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      9380                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      8107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      3875                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2934                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     2149                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1601                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     1023                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66305                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    760072                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    121484                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     14330                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      6788                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6461                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7610                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      8751                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      9237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      8035                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      3854                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2788                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1992                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1474                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      900                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,48 +148,48 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      578                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2657                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3782                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4425                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4657                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5221                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5014                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       79                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      609                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1785                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3331                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4467                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5020                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       81                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       77                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       67                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       54                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::51                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       39                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
@@ -197,112 +197,110 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       136515                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      178.576479                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     128.708862                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     198.239774                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54117     39.64%     39.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        57190     41.89%     81.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        14847     10.88%     92.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1353      0.99%     93.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1460      1.07%     94.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1428      1.05%     95.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1211      0.89%     96.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1099      0.81%     97.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3810      2.79%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         136515                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4034                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        69.350768                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.698276                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      557.584511                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4013     99.48%     99.48% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            9      0.22%     99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            4      0.10%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-5119            3      0.07%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7168-8191            1      0.02%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::11264-12287            2      0.05%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4034                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4034                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.416708                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.380496                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.197000                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3413     84.61%     84.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 10      0.25%     84.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                440     10.91%     95.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 77      1.91%     97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 36      0.89%     98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 18      0.45%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 14      0.35%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.25%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  4      0.10%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  2      0.05%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  3      0.07%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  4      0.10%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4034                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8815753021                       # Total ticks spent queuing
-system.physmem.totMemAccLat               14716565521                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1573550000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       28012.31                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       205647                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      317.429381                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     201.568290                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     286.974442                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          59802     29.08%     29.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        62661     30.47%     59.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        15924      7.74%     67.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3207      1.56%     68.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3374      1.64%     70.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        48035     23.36%     93.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7705      3.75%     97.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1172      0.57%     98.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3767      1.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         205647                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4029                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       234.045421                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       40.559432                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     3989.674296                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           4017     99.70%     99.70% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-16383            7      0.17%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-32767            2      0.05%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::90112-98303            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::212992-221183            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4029                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4029                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.437081                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.396271                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.276876                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3401     84.41%     84.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  9      0.22%     84.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                462     11.47%     96.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 50      1.24%     97.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 36      0.89%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 16      0.40%     98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 18      0.45%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 10      0.25%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  6      0.15%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  6      0.15%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  4      0.10%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  4      0.10%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  3      0.07%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  2      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  2      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4029                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    15106541272                       # Total ticks spent queuing
+system.physmem.totMemAccLat               32989841272                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4768880000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15838.67                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46762.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          49.01                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          10.31                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       49.06                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       10.33                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  34588.67                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         134.87                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           9.36                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      134.91                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        9.38                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.46                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.08                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.55                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.40                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     218109                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     26303                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.30                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1077703.88                       # Average gap between requests
-system.physmem.pageHitRate                      64.16                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  518041440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  282661500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1230403200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216432000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26842305360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            96374724480                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           162040566750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             287505134730                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              699.583184                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   268934392735                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13723060000                       # Time in different power states
+system.physmem.busUtil                           1.13                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.05                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.93                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     788463                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     25883                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.07                       # Row buffer hit rate for writes
+system.physmem.avgGap                       443551.72                       # Average gap between requests
+system.physmem.pageHitRate                      79.84                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1032091200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  563145000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6203792400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                216412560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            29560558560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           305512170480                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             3557164500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             346645334700                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              765.925147                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE     4194914578                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     15112760000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    128308892015                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    433276166672                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  513943920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  280425750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1224030600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212706000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26842305360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96023770920                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           162348426750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             287445609300                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              699.438325                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   269449023468                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13723060000                       # Time in different power states
+system.physmem_1.actEnergy                  522539640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  285115875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1235348400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212725440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            29560558560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            96876011835                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           186571355250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             315263655000                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              696.586172                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   309737229647                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     15112760000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    127794271282                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    127733879103                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               234596987                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         161823961                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15514568                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            122849584                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               109536151                       # Number of BTB hits
+system.cpu.branchPred.lookups               234612390                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         162472835                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15514556                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            121579993                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               107625887                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             89.162818                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25674290                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1300140                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             88.522696                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25035644                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1300133                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -421,129 +419,129 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                        821936839                       # number of cpu cycles simulated
+system.cpu.numCycles                        905171995                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           85359069                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1200718249                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   234596987                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          135210441                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     720713354                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                31063509                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 2336                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles           86003110                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1202048869                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   234612390                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          132661531                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     803279049                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                31064713                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1868                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         3414                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 371348285                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                652804                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          821609958                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.824964                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.165392                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3204                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 370083974                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                652982                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          904819618                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.657214                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.229926                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                139667844     17.00%     17.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                223418217     27.19%     44.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 99581089     12.12%     56.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                358942808     43.69%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                222849160     24.63%     24.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                224059075     24.76%     49.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 98313082     10.87%     60.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                359598301     39.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            821609958                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.285420                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.460840                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                121271680                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             161528221                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 484660379                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              38631604                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               15518074                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             25181978                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 13827                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1248136929                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              39965779                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               15518074                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                178276857                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                80769172                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         209944                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 464321622                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              82514289                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1190649625                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              25545503                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              24955076                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2266892                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               41524383                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1701930                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1225389846                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5812446196                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1358179405                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          40876479                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            904819618                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.259191                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.327978                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                121904104                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             244100755                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 484657410                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              38638668                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               15518681                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             24546049                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13811                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1248144086                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              39968857                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               15518681                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                178914873                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               163328471                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         207028                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 464319861                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              82530704                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1190654266                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              24276153                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              24946873                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2269725                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               41528835                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1707155                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1226040359                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5813734095                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1358184137                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          40876447                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                350611616                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               7266                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                351262129                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               7265                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 108773290                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            366116518                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           236097454                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1660812                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5332652                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1168559259                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               12361                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1017121345                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          18467813                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       379846662                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1032147150                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            207                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     821609958                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.237961                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.084868                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                 108789591                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            367388897                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           236094901                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1672944                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5307285                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1169836169                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               12331                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1017123135                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          19093941                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       381123542                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1038508983                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            177                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     904819618                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.124117                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.093910                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           263952395     32.13%     32.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           227112360     27.64%     59.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           217754382     26.50%     86.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            96663071     11.77%     98.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            16127742      1.96%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                   8      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           347160042     38.37%     38.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           227103662     25.10%     63.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           217769500     24.07%     87.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            96665190     10.68%     98.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            16121217      1.78%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                   7      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       821609958                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       904819618                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                63877670     18.90%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  18143      0.01%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              157438093     46.58%     65.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite             116037067     34.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                63881232     18.86%     18.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  18143      0.01%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.06% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              158064095     46.67%     65.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite             116064822     34.27%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             456371832     44.87%     44.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              5195828      0.51%     45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             456367780     44.87%     44.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              5195678      0.51%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
@@ -565,90 +563,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.38% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.06%     45.44% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         2550148      0.25%     46.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         2550147      0.25%     46.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       11478997      1.13%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            322111232     31.67%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           215588105     21.20%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       11478995      1.13%     47.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            322109040     31.67%     78.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           215596292     21.20%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1017121345                       # Type of FU issued
-system.cpu.iq.rate                           1.237469                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   338007862                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.332318                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3150451328                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1504870795                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    934275536                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            61876995                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           43565857                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total             1017123135                       # Type of FU issued
+system.cpu.iq.rate                           1.123679                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   338665181                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.332964                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3234948583                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1507425320                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    934275773                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            61876427                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           43565693                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses     26152450                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1321318894                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                33810313                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          9960669                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses             1321978571                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                33809745                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          9959468                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    113875580                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1094                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18373                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    107116958                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    115147959                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1090                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18974                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    107114405                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2065804                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         20149                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2065764                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         19863                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               15518074                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                35327155                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 46316                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1168577176                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               15518681                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                35329232                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 27153                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1169854056                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             366116518                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            236097454                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6621                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    106                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 49932                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18373                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15437332                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3784565                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19221897                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             974752675                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             303297711                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          42368670                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             367388897                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            236094901                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6591                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     89                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 29598                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18974                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       15437212                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3784515                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19221727                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             974753111                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             303296723                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          42370024                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                          5556                       # number of nop insts executed
-system.cpu.iew.exec_refs                    497765117                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                150613949                       # Number of branches executed
-system.cpu.iew.exec_stores                  194467406                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.185922                       # Inst execution rate
-system.cpu.iew.wb_sent                      963726327                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     960427986                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 536047777                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 893284950                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    497769972                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                150611064                       # Number of branches executed
+system.cpu.iew.exec_stores                  194473249                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.076871                       # Inst execution rate
+system.cpu.iew.wb_sent                      963726707                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     960428223                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 536045857                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 893287669                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.168494                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.600086                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.061045                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.600082                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       357420302                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       357425551                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15500888                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    770788105                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.023277                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.776928                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15500881                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    853996264                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.923576                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.715161                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    432159906     56.07%     56.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    174391468     22.63%     78.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     72936790      9.46%     88.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     32897876      4.27%     92.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8538896      1.11%     93.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14258442      1.85%     95.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7269703      0.94%     96.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      5974810      0.78%     97.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22360214      2.90%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    515355287     60.35%     60.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    174404345     20.42%     80.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     72937486      8.54%     89.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     32899801      3.85%     93.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8539084      1.00%     94.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14259189      1.67%     95.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7267219      0.85%     96.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      5975069      0.70%     97.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22358784      2.62%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    770788105                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    853996264                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
 system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -694,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              22360214                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1894569512                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2343126520                       # The number of ROB writes
-system.cpu.timesIdled                          647387                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          326881                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              22358784                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1977784350                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2343138350                       # The number of ROB writes
+system.cpu.timesIdled                          648611                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          352377                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
 system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.282975                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.282975                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.779439                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.779439                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                995803218                       # number of integer regfile reads
-system.cpu.int_regfile_writes               567908989                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  31889842                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 22959495                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                3794442903                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                384898512                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               715818410                       # number of misc regfile reads
+system.cpu.cpi                               1.412898                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.412898                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.707765                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.707765                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                995811618                       # number of integer regfile reads
+system.cpu.int_regfile_writes               567906414                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  31889839                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 22959494                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                3794441379                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                384896518                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               715823215                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2756184                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.933181                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           414216914                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2756696                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.258467                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         257783000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.933181                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999869                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2756185                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.937157                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           414216587                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2756697                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            150.258294                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         267553000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.937157                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999877                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999877                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         839346712                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        839346712                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    286294274                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       286294274                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127907939                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127907939                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         839347973                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        839347973                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    286293800                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       286293800                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127906811                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127906811                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         3157                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          3157                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     414202213                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414202213                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414205370                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414205370                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      3033975                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       3033975                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1043538                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1043538                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     414200611                       # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::cpu.data    414203768                       # number of overall hits
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+system.cpu.dcache.ReadReq_misses::cpu.data      3035079                       # number of ReadReq misses
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+system.cpu.dcache.WriteReq_misses::cpu.data      1044666                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1044666                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          646                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          646                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      4077513                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4077513                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4078159                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4078159                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  35335718000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  35335718000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10020788350                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10020788350                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      4079745                       # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::cpu.data      4080391                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4080391                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  76869214000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  76869214000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10006334850                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10006334850                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       187500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       187500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  45356506350                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  45356506350                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  45356506350                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  45356506350                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    289328249                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    289328249                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  86875548850                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  86875548850                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  86875548850                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  86875548850                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    289328879                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    289328879                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data         3803                       # number of SoftPFReq accesses(hits+misses)
@@ -776,309 +774,305 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740
 system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418279726                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418279726                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418283529                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418283529                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010486                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.010486                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008092                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.008092                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    418280356                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    418280356                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    418284159                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    418284159                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010490                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.010490                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008101                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.008101                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169866                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.169866                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009748                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009748                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009750                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009750                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11646.674083                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11646.674083                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9602.705747                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  9602.705747                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009754                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009754                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009755                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009755                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25326.923615                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25326.923615                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9578.501502                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  9578.501502                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        62500                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        62500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 11123.571243                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 11123.571243                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 11121.809216                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 11121.809216                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21294.357576                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21294.357576                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21290.986293                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21290.986293                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       355417                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       352038                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            4792                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            4878                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    74.168823                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    72.168512                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       735485                       # number of writebacks
-system.cpu.dcache.writebacks::total            735485                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       998769                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       998769                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       322672                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       322672                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2756185                       # number of writebacks
+system.cpu.dcache.writebacks::total           2756185                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       999872                       # number of ReadReq MSHR hits
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 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1321441                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1321441                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1321441                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1321441                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035206                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2035206                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720866                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       720866                       # number of WriteReq MSHR misses
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+system.cpu.dcache.demand_mshr_hits::total      1323515                       # number of demand (read+write) MSHR hits
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 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2756072                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2756072                       # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total      2756713                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24128110500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24128110500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5958496350                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5958496350                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5922000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5922000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  30086606850                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  30086606850                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  30092528850                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  30092528850                       # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total  65569114500                       # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5957184350                       # number of WriteReq MSHR miss cycles
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+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5576500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  71526298850                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  71526298850                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  71531875350                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  71531875350                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005590                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005590                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005591                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005591                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168551                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168551                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11855.365255                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11855.365255                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8265.747518                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8265.747518                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9238.689548                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9238.689548                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10916.480720                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 10916.480720                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10916.090594                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 10916.090594                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32217.417933                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32217.417933                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8262.128046                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8262.128046                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8699.687988                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8699.687988                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25950.772922                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25950.772922                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25946.761872                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25946.761872                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           5169351                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.555311                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           366173734                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           5169861                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.828545                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         247765500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.555311                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997178                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997178                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           5169363                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.872217                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           364909729                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           5169873                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             70.583886                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         257528500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.872217                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997797                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997797                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          121                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          327                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          328                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         747866384                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        747866384                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    366173762                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       366173762                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     366173762                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        366173762                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    366173762                       # number of overall hits
-system.cpu.icache.overall_hits::total       366173762                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      5174491                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       5174491                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      5174491                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        5174491                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      5174491                       # number of overall misses
-system.cpu.icache.overall_misses::total       5174491                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  41645043922                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  41645043922                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  41645043922                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  41645043922                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  41645043922                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  41645043922                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    371348253                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    371348253                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    371348253                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    371348253                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    371348253                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    371348253                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013934                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013934                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013934                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013934                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013934                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013934                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8048.143078                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8048.143078                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8048.143078                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8048.143078                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8048.143078                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8048.143078                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        82369                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          103                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3794                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         745337941                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        745337941                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    364909744                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       364909744                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     364909744                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        364909744                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    364909744                       # number of overall hits
+system.cpu.icache.overall_hits::total       364909744                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      5174203                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       5174203                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      5174203                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        5174203                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      5174203                       # number of overall misses
+system.cpu.icache.overall_misses::total       5174203                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  41972246420                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  41972246420                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  41972246420                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  41972246420                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  41972246420                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  41972246420                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    370083947                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::cpu.inst    370083947                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    370083947                       # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total    370083947                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013981                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.013981                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.013981                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.013981                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.013981                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.013981                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8111.828318                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8111.828318                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8111.828318                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8111.828318                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8111.828318                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8111.828318                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        80154                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          135                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3667                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.710332                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    20.600000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.858195                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           27                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4612                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4612                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4612                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4612                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4612                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4612                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5169879                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      5169879                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      5169879                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      5169879                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      5169879                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      5169879                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  39015177435                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  39015177435                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  39015177435                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  39015177435                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  39015177435                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  39015177435                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013922                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013922                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013922                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013922                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013922                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013922                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7546.632607                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7546.632607                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7546.632607                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7546.632607                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7546.632607                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7546.632607                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks      5169363                       # number of writebacks
+system.cpu.icache.writebacks::total           5169363                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4154                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4154                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4154                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4154                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4154                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4154                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5170049                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst      5170049                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::cpu.inst      5170049                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      5170049                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  39346514434                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  39346514434                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  39346514434                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  39346514434                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  39346514434                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  39346514434                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013970                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013970                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013970                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.013970                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013970                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.013970                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7610.472248                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7610.472248                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7610.472248                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7610.472248                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7610.472248                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7610.472248                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      1349974                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      1355118                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         4500                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      1350388                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      1355069                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         4095                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4790050                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           298717                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16361.529179                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14361886                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           315081                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            45.581568                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      18036523000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   748.333626                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   127.076161                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8786.065763                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6700.053629                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.045675                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007756                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.536259                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.408939                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998628                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.603210                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        244360860                       # Number of tag accesses
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-system.cpu.l2cache.Writeback_hits::total       735485                       # number of Writeback hits
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data       720849                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       720849                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.demand_miss_rate::cpu.data     0.040473                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::total     0.014523                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1437.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1437.500000                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82338.033844                       # average ReadExReq miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74024.527770                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75434.154681                       # average ReadSharedReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75587.737853                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75539.572439                       # average overall miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::total 72295.048953                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73721.206332                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72288.098870                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72295.048953                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1087,159 +1081,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66323                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66323                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1105                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1105                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            9                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          975                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          975                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            9                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         2080                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         2089                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            9                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         2080                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         2089                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         8868                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         8868                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202062                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       202062                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1377                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1377                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3538                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3538                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       108114                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       108114                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3538                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       109491                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       113029                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3538                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       109491                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202062                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       315091                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  17000279164                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  17000279164                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       275000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       275000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    139099000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    139099000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    240756500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    240756500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   7531984000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   7531984000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    240756500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7671083000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   7911839500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    240756500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7671083000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  17000279164                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  24912118664                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.writebacks::writebacks        66305                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66305                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1019                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1019                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          872                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          872                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         1891                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         1892                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         1891                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         1892                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       200528                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       200528                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          174                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          174                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1366                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1366                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3663                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3663                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       748596                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       748596                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3663                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       749962                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       753625                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3663                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       749962                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       200528                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       954153                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  16518025996                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  16518025996                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2993500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2993500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    133767000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    133767000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    248088000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    248088000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  49620654000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  49620654000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    248088000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  49754421000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  50002509000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    248088000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  49754421000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  16518025996                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  66520534996                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.941176                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.941176                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001910                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001910                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.000684                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.053105                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.053105                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039718                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014260                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039718                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001895                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001895                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.000709                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.000709                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.367707                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.367707                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000709                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.272051                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.095076                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000709                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.272051                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.039751                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84133.974542                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17187.500000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17187.500000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 101015.976761                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 101015.976761                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68048.756360                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68048.756360                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69667.055145                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69667.055145                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68048.756360                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70061.310975                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69998.314592                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68048.756360                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70061.310975                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79063.250502                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.120374                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82372.666141                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17204.022989                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17204.022989                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97926.061493                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97926.061493                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67728.091728                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67728.091728                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66284.957440                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66284.957440                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67728.091728                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66342.589358                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66349.323603                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67728.091728                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66342.589358                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69716.843102                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     15852127                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      7925581                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       644320                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         9549                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         9495                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           54                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7205725                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       801808                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6778141                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       245737                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests     15852468                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      7925752                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       644350                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       760150                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       116849                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops       643301                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       7205895                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       801566                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      6546111                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       987513                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       243924                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          174                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          174                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       720849                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       720849                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      5169879                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2035847                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     15508216                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7626183                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          23134399                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330871168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223499584                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          554370752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      544470                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     16396581                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.079179                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.270031                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      5170049                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2035848                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     15508407                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7626630                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          23135037                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    661654912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311653440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          973308352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1297915                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      9224662                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.222014                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.558747                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           15098363     92.08%     92.08% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            1298164      7.92%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                 54      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            7819958     84.77%     84.77% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             761403      8.25%     93.03% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             643301      6.97%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       16396581                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     8661548500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    7754847439                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4135063977                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             313637                       # Transaction distribution
-system.membus.trans_dist::Writeback             66323                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           231789                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1377                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1377                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        313637                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       928172                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 928172                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24405568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                24405568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::total        9224662                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    15851782000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          3.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    7755313513                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    4135165933                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             952696                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66305                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           227453                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              174                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             174                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1366                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1366                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        952697                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2202231                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                2202231                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65303488                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                65303488                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            613142                       # Request fanout histogram
+system.membus.snoop_fanout::samples           1247995                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  613142    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1247995    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              613142                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           975944720                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1649749525                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
+system.membus.snoop_fanout::total             1247995                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1752388071                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         5021031104                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 24851d5c1..dd5f11d63 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.043724                       # Number of seconds simulated
-sim_ticks                                1043723537500                       # Number of ticks simulated
-final_tick                               1043723537500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.045756                       # Number of seconds simulated
+sim_ticks                                1045756396500                       # Number of ticks simulated
+final_tick                               1045756396500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 832063                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1022241                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1358287943                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323064                       # Number of bytes of host memory used
-host_seconds                                   768.41                       # Real time elapsed on the host
+host_inst_rate                                 734670                       # Simulator instruction rate (inst/s)
+host_op_rate                                   902587                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1201635964                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 323928                       # Number of bytes of host memory used
+host_seconds                                   870.28                       # Real time elapsed on the host
 sim_insts                                   639366787                       # Number of instructions simulated
 sim_ops                                     785501035                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            113216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18469760                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18582976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       113216                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          113216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            112576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18470976                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18583552                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       112576                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          112576                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1769                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288590                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                290359                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               1759                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288609                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                290368                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               108473                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             17696027                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                17804500                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108473                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108473                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4053058                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4053058                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4053058                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108473                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            17696027                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               21857558                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               107650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             17662790                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                17770441                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          107650                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             107650                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4045179                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4045179                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4045179                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              107650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            17662790                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               21815620                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -154,7 +154,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       2087447075                       # number of cpu cycles simulated
+system.cpu.numCycles                       2091512793                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   639366787                       # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs                     381221435                       # nu
 system.cpu.num_load_insts                   252240938                       # Number of load instructions
 system.cpu.num_store_insts                  128980497                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               2087447074.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               2091512792.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         137364860                       # Number of branches fetched
@@ -215,19 +215,19 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  788730744                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            778046                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4093.640237                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4093.549761                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           378510311                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            782142                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            483.940654                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         996538500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4093.640237                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999424                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999424                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle        1041808500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4093.549761                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999402                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999402                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          591                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1036                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1037                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         2319                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         759367050                       # Number of tag accesses
@@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data       782004                       # n
 system.cpu.dcache.demand_misses::total         782004                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       782143                       # number of overall misses
 system.cpu.dcache.overall_misses::total        782143                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18611031000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18611031000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3677169000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3677169000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22288200000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22288200000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22288200000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22288200000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  20169396000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  20169396000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4139811500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4139811500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  24309207500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  24309207500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  24309207500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  24309207500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    250325879                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    250325879                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
@@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_miss_rate::total     0.002062                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002062                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002062                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28501.388740                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28496.323562                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31085.784088                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31080.259620                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        89072                       # number of writebacks
-system.cpu.dcache.writebacks::total             89072                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        88995                       # number of writebacks
+system.cpu.dcache.writebacks::total             88995                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
@@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       782003
 system.cpu.dcache.demand_mshr_misses::total       782003                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       782142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       782142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17898311000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17898311000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3607846000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3607846000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1752000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1752000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21506157000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  21506157000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21507909000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  21507909000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  19456669000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  19456669000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4070488500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4070488500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1766000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1766000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23527157500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23527157500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23528923500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  23528923500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
@@ -342,26 +342,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              8769                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1391.464458                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1391.385132                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           643367692                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             10208                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          63025.831897                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1391.464458                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.679426                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.679426                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1391.385132                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.679387                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.679387                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1439                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
@@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst        10208                       # n
 system.cpu.icache.demand_misses::total          10208                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        10208                       # number of overall misses
 system.cpu.icache.overall_misses::total         10208                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    207225000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    207225000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    207225000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    207225000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    207225000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    207225000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    219076500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    219076500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    219076500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    219076500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    219076500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    219076500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    643377900                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    643377900                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    643377900                       # number of demand (read+write) accesses
@@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000016
 system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20300.254702                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20300.254702                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21461.255878                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21461.255878                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -413,93 +413,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks         8769                       # number of writebacks
+system.cpu.icache.writebacks::total              8769                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10208                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        10208                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        10208                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total        10208                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        10208                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        10208                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    197017000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    197017000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    197017000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    197017000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    197017000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    197017000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    208868500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    208868500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    208868500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    208868500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    208868500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    208868500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           257579                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32626.728627                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1218059                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           290322                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.195545                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           257772                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32622.591915                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1218050                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           290515                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.192727                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2506.605810                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    48.754609                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.076496                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001488                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.917705                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995689                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2525.639317                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    45.833351                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.077076                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001399                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.917087                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995562                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32743                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1441                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        30967                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          148                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1440                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        30923                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999237                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         12984085                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        12984085                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks        89072                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        89072                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         12984278                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        12984278                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks        88995                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total        88995                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         8752                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         8752                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         3230                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         3230                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8439                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         8439                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490322                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       490322                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8439                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       493552                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          501991                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8439                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       493552                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         501991                       # number of overall hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8449                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         8449                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490303                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       490303                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         8449                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       493533                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          501982                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8449                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       493533                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         501982                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66093                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66093                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1769                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1769                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222497                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222497                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1769                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       288590                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        290359                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1769                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       288590                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       290359                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3469946000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   3469946000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     93021000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     93021000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  11681407500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  11681407500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     93021000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  15151353500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  15244374500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     93021000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  15151353500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  15244374500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks        89072                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        89072                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1759                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         1759                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222516                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222516                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1759                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       288609                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        290368                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1759                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       288609                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       290368                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3932586500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3932586500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    104759500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    104759500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  13239976500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  13239976500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    104759500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  17172563000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  17277322500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    104759500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  17172563000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  17277322500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        88995                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        88995                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         8752                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         8752                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69323                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69323                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        10208                       # number of ReadCleanReq accesses(hits+misses)
@@ -514,28 +520,28 @@ system.cpu.l2cache.overall_accesses::cpu.data       782142
 system.cpu.l2cache.overall_accesses::total       792350                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953407                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.953407                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.173295                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.173295                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312137                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312137                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.173295                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.368974                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.366453                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.173295                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.368974                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.366453                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.172316                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.172316                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312163                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312163                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.172316                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.368998                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.366464                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.172316                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.368998                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.366464                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -546,58 +552,54 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          184                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          184                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66093                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1769                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1769                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222497                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222497                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1769                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       288590                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       290359                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1769                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       288590                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       290359                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2809016000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2809016000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     75331000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     75331000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   9456437500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   9456437500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     75331000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12265453500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  12340784500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     75331000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12265453500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  12340784500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1759                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1759                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222516                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222516                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1759                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       288609                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       290368                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1759                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       288609                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       290368                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3271656500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3271656500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     87169500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     87169500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  11014816500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  11014816500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     87169500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14286473000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  14373642500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     87169500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14286473000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14373642500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953407                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953407                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.173295                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312137                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312137                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368974                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.366453                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.173295                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368974                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.366453                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.172316                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.172316                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312163                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312163                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.172316                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368998                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.366464                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.172316                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368998                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.366464                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      1579165                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       786845                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -606,8 +608,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops         1580                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1573                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            7                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        723027                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       155170                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       888114                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155093                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         8752                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       879632                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69323                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69323                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq        10208                       # Transaction distribution
@@ -615,51 +618,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq       712819
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        29168                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2341237                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total           2370405                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       653312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55757696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56411008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      257579                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1836744                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.002089                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.045741                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1213440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55752768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56966208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      257772                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1050122                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.002597                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.051024                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1832914     99.79%     99.79% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3823      0.21%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1047402     99.74%     99.74% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2713      0.26%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  7      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1836744                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      878654500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1050122                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      887346500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      15312000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1173213000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             224266                       # Transaction distribution
-system.membus.trans_dist::Writeback             66098                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           190085                       # Transaction distribution
+system.membus.trans_dist::ReadResp             224275                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190094                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66093                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66093                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        224266                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       836901                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 836901                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22813248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22813248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        224275                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       836928                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 836928                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22813824                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22813824                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            546599                       # Request fanout histogram
+system.membus.snoop_fanout::samples            546561                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  546599    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  546561    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              546599                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           811365948                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              546561                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           811325000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1452169448                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1451840000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 15844baba..e086bc978 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.059549                       # Number of seconds simulated
-sim_ticks                                 59549031000                       # Number of ticks simulated
-final_tick                                59549031000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.059474                       # Number of seconds simulated
+sim_ticks                                 59473862000                       # Number of ticks simulated
+final_tick                                59473862000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 320796                       # Simulator instruction rate (inst/s)
-host_op_rate                                   320796                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              216005540                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 307628                       # Number of bytes of host memory used
-host_seconds                                   275.68                       # Real time elapsed on the host
+host_inst_rate                                 342067                       # Simulator instruction rate (inst/s)
+host_op_rate                                   342067                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              230037089                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307480                       # Number of bytes of host memory used
+host_seconds                                   258.54                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            500352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10147264                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10647616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       500352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          500352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7320640                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7320640                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               7818                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158551                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166369                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114385                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114385                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8402353                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            170401832                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               178804186                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8402353                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8402353                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         122934662                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              122934662                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         122934662                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8402353                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           170401832                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              301738848                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166369                       # Number of read requests accepted
-system.physmem.writeReqs                       114385                       # Number of write requests accepted
-system.physmem.readBursts                      166369                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114385                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10647296                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7318592                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10647616                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7320640                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            432448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10149376                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10581824                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       432448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          432448                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7325760                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7325760                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6757                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158584                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                165341                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114465                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114465                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              7271228                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            170652715                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               177923942                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         7271228                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            7271228                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         123176127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              123176127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         123176127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             7271228                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           170652715                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              301100070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        165341                       # Number of read requests accepted
+system.physmem.writeReqs                       114465                       # Number of write requests accepted
+system.physmem.readBursts                      165341                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114465                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10581376                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7323904                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10581824                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7325760                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10447                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10506                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10283                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10092                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10413                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10414                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9828                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10274                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10580                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10645                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10558                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10261                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10296                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10620                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10515                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10632                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7162                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7273                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7295                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7000                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          14983                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10312                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10359                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10206                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10057                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10348                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10339                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9776                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10207                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10534                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10607                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10498                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10274                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10561                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10464                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10564                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7163                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7274                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7296                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7002                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7181                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7187                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6833                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7084                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7224                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6994                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7113                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6992                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6991                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7295                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7099                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7225                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7000                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7115                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7034                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6992                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7299                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7308                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     59549007000                       # Total gap between requests
+system.physmem.totGap                     59473838000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166369                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  165341                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114385                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    164750                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1588                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114465                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163748                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1560                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      749                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7031                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7084                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,122 +193,120 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        54768                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      328.014023                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     195.067660                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.383666                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19491     35.59%     35.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11850     21.64%     57.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5663     10.34%     67.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3680      6.72%     74.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2902      5.30%     79.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2048      3.74%     83.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1635      2.99%     86.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1469      2.68%     88.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6030     11.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          54768                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7038                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.634839                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      336.413145                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7035     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        54714                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      327.237051                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.297949                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.344141                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19597     35.82%     35.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11811     21.59%     57.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5572     10.18%     67.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3684      6.73%     74.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2893      5.29%     79.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2049      3.74%     83.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1621      2.96%     86.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1502      2.75%     89.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5985     10.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          54714                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7041                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.479761                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      336.363256                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7038     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7038                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7038                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.247940                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.232365                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.745442                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6264     89.00%     89.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 17      0.24%     89.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                601      8.54%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                122      1.73%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 23      0.33%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  6      0.09%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  2      0.03%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7041                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7041                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.252805                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.237164                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.745060                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6251     88.78%     88.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 16      0.23%     89.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                606      8.61%     97.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                134      1.90%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 28      0.40%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  4      0.06%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7038                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2001235750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5120560750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    831820000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12029.26                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7041                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1980163000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5080175500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    826670000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11976.74                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30779.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         178.80                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         122.90                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      178.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      122.93                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30726.74                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         177.92                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         123.14                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      177.92                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      123.18                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.36                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.40                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           2.35                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.39                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.96                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144462                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81475                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   86.83                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.23                       # Row buffer hit rate for writes
-system.physmem.avgGap                       212103.86                       # Average gap between requests
-system.physmem.pageHitRate                      80.48                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  199614240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  108916500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 641355000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                368899920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3888958320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            12587581890                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            24683289750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              42478615620                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              713.426150                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    40913813750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1988220000                       # Time in different power states
+system.physmem.avgWrQLen                        23.98                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     143867                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81182                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.02                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  70.92                       # Row buffer hit rate for writes
+system.physmem.avgGap                       212553.83                       # Average gap between requests
+system.physmem.pageHitRate                      80.43                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  199175760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  108677250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 636448800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                369204480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3884381280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            12421725570                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            24786732000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              42406345140                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              713.051581                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    41087166750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1985880000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16639693750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     16398707250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  214137000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  116840625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 655777200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                371764080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3888958320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            13157757450                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24183135750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              42588370425                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              715.269477                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40075806250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1988220000                       # Time in different power states
+system.physmem_1.actEnergy                  214341120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  116952000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 652938000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                372237120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3884381280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13062187260                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24224923500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              42527960280                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              715.096508                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40147172500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1985880000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     17478332750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     17338598750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14666095                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9488989                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            386100                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9897774                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6385513                       # Number of BTB hits
+system.cpu.branchPred.lookups                14666171                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9489023                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            386095                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9897790                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6385525                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             64.514637                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1708089                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              84886                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             64.514654                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1708105                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              84877                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20569916                       # DTB read hits
-system.cpu.dtb.read_misses                      97322                       # DTB read misses
+system.cpu.dtb.read_hits                     20569903                       # DTB read hits
+system.cpu.dtb.read_misses                      97320                       # DTB read misses
 system.cpu.dtb.read_acv                            10                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20667238                       # DTB read accesses
-system.cpu.dtb.write_hits                    14665322                       # DTB write hits
+system.cpu.dtb.read_accesses                 20667223                       # DTB read accesses
+system.cpu.dtb.write_hits                    14665328                       # DTB write hits
 system.cpu.dtb.write_misses                      9407                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14674729                       # DTB write accesses
-system.cpu.dtb.data_hits                     35235238                       # DTB hits
-system.cpu.dtb.data_misses                     106729                       # DTB misses
+system.cpu.dtb.write_accesses                14674735                       # DTB write accesses
+system.cpu.dtb.data_hits                     35235231                       # DTB hits
+system.cpu.dtb.data_misses                     106727                       # DTB misses
 system.cpu.dtb.data_acv                            10                       # DTB access violations
-system.cpu.dtb.data_accesses                 35341967                       # DTB accesses
-system.cpu.itb.fetch_hits                    25606453                       # ITB hits
-system.cpu.itb.fetch_misses                      5227                       # ITB misses
+system.cpu.dtb.data_accesses                 35341958                       # DTB accesses
+system.cpu.itb.fetch_hits                    25606544                       # ITB hits
+system.cpu.itb.fetch_misses                      5228                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25611680                       # ITB accesses
+system.cpu.itb.fetch_accesses                25611772                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -322,65 +320,65 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        119098062                       # number of cpu cycles simulated
+system.cpu.numCycles                        118947724                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88438073                       # Number of instructions committed
 system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1106110                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1106117                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.346683                       # CPI: cycles per instruction
-system.cpu.ipc                               0.742565                       # IPC: instructions per cycle
-system.cpu.tickCycles                        91473495                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        27624567                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.344983                       # CPI: cycles per instruction
+system.cpu.ipc                               0.743504                       # IPC: instructions per cycle
+system.cpu.tickCycles                        91473408                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        27474316                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            200766                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.715334                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34616231                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4070.683377                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34616213                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            204862                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            168.973411                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            168.973324                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         687575500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.715334                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993827                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993827                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.683377                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993819                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993819                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          686                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3360                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          687                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3361                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70176386                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70176386                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20282965                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20282965                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     14333266                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333266                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      34616231                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34616231                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34616231                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34616231                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses          70176360                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70176360                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20282952                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20282952                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     14333261                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333261                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34616213                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34616213                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34616213                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34616213                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data        89420                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total         89420                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       280111                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280111                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       369531                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         369531                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       369531                       # number of overall misses
-system.cpu.dcache.overall_misses::total        369531                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4765724000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4765724000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21723340000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21723340000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  26489064000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  26489064000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  26489064000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  26489064000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20372385                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20372385                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data       280116                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280116                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       369536                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         369536                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       369536                       # number of overall misses
+system.cpu.dcache.overall_misses::total        369536                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4768019500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4768019500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21708920500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21708920500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  26476940000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  26476940000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  26476940000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  26476940000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20372372                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20372372                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     34985762                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34985762                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     34985762                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34985762                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     34985749                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34985749                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34985749                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34985749                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004389                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.004389                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019168                       # miss rate for WriteReq accesses
@@ -389,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.010562
 system.cpu.dcache.demand_miss_rate::total     0.010562                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.010562                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.010562                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53295.951689                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53295.951689                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77552.613071                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77552.613071                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71682.927819                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71682.927819                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71682.927819                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71682.927819                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53321.622679                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53321.622679                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77499.751889                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77499.751889                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 71649.149203                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 71649.149203                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 71649.149203                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 71649.149203                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -405,16 +403,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168453                       # number of writebacks
-system.cpu.dcache.writebacks::total            168453                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks       168423                       # number of writebacks
+system.cpu.dcache.writebacks::total            168423                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28115                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total        28115                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136554                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136554                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       164669                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       164669                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       164669                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       164669                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136559                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136559                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       164674                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       164674                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       164674                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       164674                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61305                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        61305                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143557                       # number of WriteReq MSHR misses
@@ -423,14 +421,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       204862
 system.cpu.dcache.demand_mshr_misses::total       204862                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       204862                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       204862                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2678183500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2678183500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10981560500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10981560500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13659744000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13659744000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13659744000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13659744000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2680071500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2680071500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10970928000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10970928000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13650999500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13650999500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13650999500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13650999500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009824                       # mshr miss rate for WriteReq accesses
@@ -439,69 +437,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005856
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005856                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43686.216459                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43686.216459                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76496.168769                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76496.168769                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66677.783093                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66677.783093                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66677.783093                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66677.783093                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43717.013294                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43717.013294                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76422.104112                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76422.104112                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66635.098261                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66635.098261                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66635.098261                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66635.098261                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            152851                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1932.369225                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25451553                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            154899                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            164.310635                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42309465500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1932.369225                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.943540                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.943540                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            152856                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1932.301021                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25451639                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            154904                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            164.305886                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       42254913500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1932.301021                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.943506                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.943506                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          159                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3         1041                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          798                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51367805                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51367805                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25451553                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25451553                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25451553                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25451553                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25451553                       # number of overall hits
-system.cpu.icache.overall_hits::total        25451553                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       154900                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        154900                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       154900                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         154900                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       154900                       # number of overall misses
-system.cpu.icache.overall_misses::total        154900                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2550963000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2550963000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2550963000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2550963000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2550963000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2550963000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25606453                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25606453                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25606453                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total     25606453                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          51367992                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51367992                       # Number of data accesses
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+system.cpu.icache.ReadReq_misses::cpu.inst       154905                       # number of ReadReq misses
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2479923000                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::cpu.inst   2479923000                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total   2479923000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25606544                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     25606544                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25606544                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25606544                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006049                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.006049                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.006049                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.006049                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.006049                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.006049                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16468.450613                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16468.450613                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16468.450613                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16468.450613                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16468.450613                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16468.450613                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16009.315387                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16009.315387                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16009.315387                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16009.315387                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16009.315387                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16009.315387                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -510,129 +508,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154900                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       154900                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       154900                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       154900                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       154900                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       154900                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2396064000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2396064000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2396064000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2396064000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2396064000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2396064000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks       152856                       # number of writebacks
+system.cpu.icache.writebacks::total            152856                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154905                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst       154905                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       154905                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       154905                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       154905                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2325019000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2325019000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2325019000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2325019000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2325019000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2325019000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006049                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.006049                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.006049                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15468.457069                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15468.457069                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15468.457069                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15468.457069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15468.457069                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15468.457069                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15009.321842                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15009.321842                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15009.321842                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132445                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30425.579826                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             402950                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164521                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.449231                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           133370                       # number of replacements
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 25961.899693                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2481.819774                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1981.860360                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.tag_accesses          6015111                       # Number of tag accesses
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-system.cpu.l2cache.Writeback_hits::writebacks       168453                       # number of Writeback hits
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-system.cpu.l2cache.Writeback_accesses::total       168453                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.occ_blocks::writebacks 26353.973497                       # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.979919                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          6016150                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         6016150                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       168423                       # number of WritebackDirty hits
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data       143558                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       143558                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       154900                       # number of ReadCleanReq accesses(hits+misses)
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 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        61304                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total        61304                       # number of ReadSharedReq accesses(hits+misses)
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 system.cpu.l2cache.demand_accesses::cpu.data       204862                       # number of demand (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data       204862                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       359762                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911701                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911701                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.050478                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.050478                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.451341                       # miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81241.748292                       # average ReadExReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::total 81054.147382                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81159.898535                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79448.505475                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79448.505475                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80675.968377                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80675.968377                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79448.505475                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81075.366998                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81008.872519                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79448.505475                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81075.366998                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81008.872519                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -641,122 +645,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114385                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114385                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2091                       # number of CleanEvict MSHR misses
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+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27701                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27701                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         6758                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158584                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       165342                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         6758                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158584                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       165342                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9313621000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9313621000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    469343000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    469343000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1957795000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1957795000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    469343000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11271416000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11740759000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    469343000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11271416000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11740759000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911701                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911701                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.050478                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.050478                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.451341                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451341                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.050478                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773941                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.462445                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.050478                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773941                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.462445                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71241.748292                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71241.748292                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69204.949482                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69204.949482                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70689.670751                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70689.670751                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69204.949482                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71145.404318                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71054.207489                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911708                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911708                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043627                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.451863                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451863                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.774102                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.459581                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.774102                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.459581                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71159.898535                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71159.898535                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69449.985203                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70675.968377                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70675.968377                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71075.366998                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71008.932999                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71075.366998                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71008.932999                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       713379                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       353617                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       713389                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       353622                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         4025                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4025                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         4036                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4036                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        216203                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       282838                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       203224                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        216208                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       282888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       152856                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        51248                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       143558                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       143558                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       154900                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       154905                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq        61304                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       462650                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       462665                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       610490                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1073140                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9913536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23892160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           33805696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      132445                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       845824                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.004759                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.068819                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count::total           1073155                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     19696640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23890240                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           43586880                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      133370                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       493137                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.008184                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.090096                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             841799     99.52%     99.52% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4025      0.48%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             489101     99.18%     99.18% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               4036      0.82%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         845824                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      525142500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     232349997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         493137                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      677973500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     232357497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     307296493                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     307299487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              35487                       # Transaction distribution
-system.membus.trans_dist::Writeback            114385                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            16125                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130882                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130882                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         35487                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       463248                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 463248                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17968256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17968256                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              34458                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       114465                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14983                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130883                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130883                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34458                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       460130                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 460130                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17907584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17907584                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            296879                       # Request fanout histogram
+system.membus.snoop_fanout::samples            294789                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  296879    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  294789    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              296879                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           824874000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              294789                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           822943500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          878418750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          872924250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index bea1e6fc8..b43434371 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,106 +1,106 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.022357                       # Number of seconds simulated
-sim_ticks                                 22356634500                       # Number of ticks simulated
-final_tick                                22356634500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022297                       # Number of seconds simulated
+sim_ticks                                 22296591500                       # Number of ticks simulated
+final_tick                                22296591500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 213363                       # Simulator instruction rate (inst/s)
-host_op_rate                                   213363                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59931818                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308400                       # Number of bytes of host memory used
-host_seconds                                   373.03                       # Real time elapsed on the host
+host_inst_rate                                 221726                       # Simulator instruction rate (inst/s)
+host_op_rate                                   221726                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               62113736                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308500                       # Number of bytes of host memory used
+host_seconds                                   358.96                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            471552                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10150720                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10622272                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       471552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          471552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7318272                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7318272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               7368                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158605                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                165973                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114348                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114348                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             21092262                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            454036139                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               475128401                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        21092262                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           21092262                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         327342293                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              327342293                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         327342293                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            21092262                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           454036139                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              802470694                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        165973                       # Number of read requests accepted
-system.physmem.writeReqs                       114348                       # Number of write requests accepted
-system.physmem.readBursts                      165973                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114348                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10621952                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7316672                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10622272                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7318272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            409984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10153216                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10563200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       409984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          409984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7322432                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7322432                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6406                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158644                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                165050                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114413                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114413                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             18387743                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            455370768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               473758511                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        18387743                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           18387743                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         328410376                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              328410376                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         328410376                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            18387743                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           455370768                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              802168888                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        165050                       # Number of read requests accepted
+system.physmem.writeReqs                       114413                       # Number of write requests accepted
+system.physmem.readBursts                      165050                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114413                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10562816                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7320896                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10563200                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7322432                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10420                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10451                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10285                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10056                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10402                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10375                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9822                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10280                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10559                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10640                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10517                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10263                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10582                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10475                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10613                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7161                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          14730                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10292                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10329                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10209                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10020                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10344                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10314                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9779                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10195                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10531                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10599                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10453                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10204                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10247                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10532                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10447                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10549                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7163                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7267                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7294                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6998                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7000                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7171                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6835                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7095                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7219                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6995                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7101                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6988                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6991                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7292                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7180                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6836                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7102                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7001                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7100                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7020                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6992                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7297                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     22356603500                       # Total gap between requests
+system.physmem.totGap                     22296560500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  165973                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  165050                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114348                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     52267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     43039                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     38487                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     32162                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114413                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     51457                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     43023                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     38384                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     32167                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      835                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      860                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4827                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6088                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6570                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6911                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7548                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7865                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8321                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     9778                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      838                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      874                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1898                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3531                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4839                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7742                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8364                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     9639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8083                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      175                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
@@ -193,125 +193,124 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        52288                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      343.051408                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     202.164629                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.365120                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          18284     34.97%     34.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10551     20.18%     55.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5984     11.44%     66.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2964      5.67%     72.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2982      5.70%     77.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1592      3.04%     81.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1956      3.74%     84.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          963      1.84%     86.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7012     13.41%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          52288                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6989                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.745743                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      338.273336                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           6986     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        52310                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      341.858612                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     200.924906                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.625607                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18434     35.24%     35.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10645     20.35%     55.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5863     11.21%     66.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2906      5.56%     72.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2975      5.69%     78.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1493      2.85%     80.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2022      3.87%     84.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          988      1.89%     86.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6984     13.35%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          52310                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6990                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.610300                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      338.218951                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6987     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6989                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6989                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.357562                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.328073                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.050353                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6097     87.24%     87.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 30      0.43%     87.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                474      6.78%     94.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                201      2.88%     97.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 97      1.39%     98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 49      0.70%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 24      0.34%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  8      0.11%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  5      0.07%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6989                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5746744750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8858644750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    829840000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34625.62                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6990                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6990                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.364664                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.334270                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.064891                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6098     87.24%     87.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 26      0.37%     87.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                456      6.52%     94.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                208      2.98%     97.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                103      1.47%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 57      0.82%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 21      0.30%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 10      0.14%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  8      0.11%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6990                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5731685000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8826260000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    825220000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       34728.22                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  53375.62                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         475.11                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         327.27                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      475.13                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      327.34                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53478.22                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         473.74                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         328.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      473.76                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      328.41                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           6.27                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.71                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      2.56                       # Data bus utilization in percentage for writes
+system.physmem.busUtilRead                       3.70                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      2.57                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.93                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.55                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145973                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     82020                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.95                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                        79753.58                       # Average gap between requests
-system.physmem.pageHitRate                      81.33                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  190882440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  104152125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 640161600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                368899920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1460075760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             6647542920                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             7581572250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              16993287015                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              760.170138                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    12528806000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       746460000                       # Time in different power states
+system.physmem.avgWrQLen                        24.49                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145441                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81669                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   88.12                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.38                       # Row buffer hit rate for writes
+system.physmem.avgGap                        79783.59                       # Average gap between requests
+system.physmem.pageHitRate                      81.27                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  190375920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  103875750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 635356800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                369036000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             6553881090                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             7626357750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              16934890590                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              759.674656                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    12601715000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       744380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9079331500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      8946212500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  204271200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  111457500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 654100200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                371699280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1460075760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             6857633520                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             7397282250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              17056519710                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              762.998761                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    12224344750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       746460000                       # Time in different power states
+system.physmem_1.actEnergy                  204815520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  111754500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 651565200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                371893680                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             6747677955                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             7456388250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              17000102385                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              762.598381                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    12320846000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       744380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9383970250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9227273000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16500558                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10689411                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            329507                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9043813                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7288978                       # Number of BTB hits
+system.cpu.branchPred.lookups                16493971                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10685365                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            327092                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8977635                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7282355                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.596293                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1974529                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               2931                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             81.116630                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1973286                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               2952                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22520885                       # DTB read hits
-system.cpu.dtb.read_misses                     225850                       # DTB read misses
-system.cpu.dtb.read_acv                            12                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22746735                       # DTB read accesses
-system.cpu.dtb.write_hits                    15825785                       # DTB write hits
-system.cpu.dtb.write_misses                     44675                       # DTB write misses
-system.cpu.dtb.write_acv                            5                       # DTB write access violations
-system.cpu.dtb.write_accesses                15870460                       # DTB write accesses
-system.cpu.dtb.data_hits                     38346670                       # DTB hits
-system.cpu.dtb.data_misses                     270525                       # DTB misses
-system.cpu.dtb.data_acv                            17                       # DTB access violations
-system.cpu.dtb.data_accesses                 38617195                       # DTB accesses
-system.cpu.itb.fetch_hits                    13761847                       # ITB hits
-system.cpu.itb.fetch_misses                     29330                       # ITB misses
+system.cpu.dtb.read_hits                     22518673                       # DTB read hits
+system.cpu.dtb.read_misses                     225961                       # DTB read misses
+system.cpu.dtb.read_acv                            15                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22744634                       # DTB read accesses
+system.cpu.dtb.write_hits                    15824450                       # DTB write hits
+system.cpu.dtb.write_misses                     44763                       # DTB write misses
+system.cpu.dtb.write_acv                            4                       # DTB write access violations
+system.cpu.dtb.write_accesses                15869213                       # DTB write accesses
+system.cpu.dtb.data_hits                     38343123                       # DTB hits
+system.cpu.dtb.data_misses                     270724                       # DTB misses
+system.cpu.dtb.data_acv                            19                       # DTB access violations
+system.cpu.dtb.data_accesses                 38613847                       # DTB accesses
+system.cpu.itb.fetch_hits                    13750650                       # ITB hits
+system.cpu.itb.fetch_misses                     29320                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                13791177                       # ITB accesses
+system.cpu.itb.fetch_accesses                13779970                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -325,141 +324,141 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         44713274                       # number of cpu cycles simulated
+system.cpu.numCycles                         44593188                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15584768                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      105191572                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16500558                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9263507                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      27593237                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                  896542                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        162                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 4764                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        325871                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          110                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13761847                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                191924                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles           15564341                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      105145283                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16493971                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9255641                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      27572822                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  891924                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        262                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 4803                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        325760                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           89                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13750650                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                190232                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples           43957183                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.393046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.127676                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples           43914039                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.394343                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.128103                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24416716     55.55%     55.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1522401      3.46%     59.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1379227      3.14%     62.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1505485      3.42%     65.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4199085      9.55%     75.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1828470      4.16%     79.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   669319      1.52%     80.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1052182      2.39%     83.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7384298     16.80%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24384273     55.53%     55.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1520929      3.46%     58.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1376099      3.13%     62.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1504413      3.43%     65.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4198532      9.56%     75.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1828676      4.16%     79.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   668520      1.52%     80.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1050487      2.39%     83.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7382110     16.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43957183                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.369030                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.352580                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 14931500                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9767964                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18310970                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                595597                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 351152                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3708003                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 98860                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              103215952                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                311866                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 351152                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15279451                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4431592                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          96231                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18542963                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5255794                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102192828                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  5698                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  95463                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 341437                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4753642                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            61435412                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             123253139                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        122935807                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            317331                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43914039                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.369876                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.357878                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 14911775                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9756593                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18301996                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                594945                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 348730                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3706760                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 98994                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              103174683                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                312811                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 348730                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15258388                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4434115                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          96788                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18534618                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5241400                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102158813                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  5649                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  94745                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 345515                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4735615                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            61411273                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             123213365                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        122896091                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            317273                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8888531                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5692                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5745                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   2361848                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23156457                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16385404                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1258348                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           502815                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   90834629                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5552                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  88691609                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             70456                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11248424                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4497706                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            969                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43957183                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.017682                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.245665                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  8864392                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5712                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5765                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   2362727                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23149705                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16384887                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1256801                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           494099                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   90814957                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5561                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  88678954                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             70817                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11228761                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4483589                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            978                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43914039                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.019376                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.246135                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17476881     39.76%     39.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             5730177     13.04%     52.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5107740     11.62%     64.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4380373      9.97%     74.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4328154      9.85%     84.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2635103      5.99%     90.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1947598      4.43%     94.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1378142      3.14%     97.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              973015      2.21%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17441953     39.72%     39.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             5726957     13.04%     52.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5104887     11.62%     64.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4381256      9.98%     74.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4320313      9.84%     84.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2639459      6.01%     90.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1947949      4.44%     94.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1377906      3.14%     97.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              973359      2.22%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43957183                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43914039                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  243362      9.64%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1165216     46.16%     55.81% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1115524     44.19%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  242855      9.63%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1163309     46.14%     55.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1115010     44.23%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49430492     55.73%     55.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                43978      0.05%     55.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49423838     55.73%     55.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43986      0.05%     55.78% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121147      0.14%     55.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  93      0.00%     55.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              120628      0.14%     56.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 63      0.00%     56.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               39084      0.04%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121174      0.14%     55.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  92      0.00%     55.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              120676      0.14%     56.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 62      0.00%     56.06% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               39089      0.04%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.10% # Type of FU issued
@@ -481,84 +480,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.10% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             22917985     25.84%     81.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            16018139     18.06%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22912706     25.84%     81.94% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            16017331     18.06%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               88691609                       # Type of FU issued
-system.cpu.iq.rate                           1.983563                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2524102                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.028459                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          223325364                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         101690449                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     86898361                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              609595                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             418176                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       299341                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90910760                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  304951                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1670602                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               88678954                       # Type of FU issued
+system.cpu.iq.rate                           1.988621                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2521174                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.028430                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          223254204                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         101651163                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86893480                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              609734                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             418232                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       299390                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90895107                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  305021                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1671418                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2879819                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5660                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20258                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1772027                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2873067                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5610                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        20361                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1771510                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3047                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        205936                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3045                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        204833                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 351152                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1286887                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2706445                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100341607                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            125884                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23156457                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16385404                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5552                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3769                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               2705021                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20258                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         121859                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       151192                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               273051                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              87981340                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22747403                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            710269                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 348730                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1277507                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2721681                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100319642                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            124919                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23149705                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16384887                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5561                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3725                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               2720217                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          20361                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         118662                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       150973                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               269635                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              87973235                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22745315                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            705719                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9501426                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38618193                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15127263                       # Number of branches executed
-system.cpu.iew.exec_stores                   15870790                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.967678                       # Inst execution rate
-system.cpu.iew.wb_sent                       87600358                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87197702                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33849535                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  44277575                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9499124                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38614853                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15126858                       # Number of branches executed
+system.cpu.iew.exec_stores                   15869538                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.972795                       # Inst execution rate
+system.cpu.iew.wb_sent                       87594856                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87192870                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33852684                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  44279326                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.950152                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.764485                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.955296                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.764526                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8791000                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         8765402                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            232388                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     42666920                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.070472                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.884283                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            229860                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     42628268                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.072350                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.885151                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     21190783     49.67%     49.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      6285871     14.73%     64.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      2905995      6.81%     71.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1744112      4.09%     75.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1680276      3.94%     79.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1128586      2.65%     81.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1203447      2.82%     84.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       797041      1.87%     86.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5730809     13.43%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     21157300     49.63%     49.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      6282680     14.74%     64.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2903206      6.81%     71.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1743375      4.09%     75.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1680050      3.94%     79.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1128930      2.65%     81.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1204133      2.82%     84.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       796945      1.87%     86.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5731649     13.45%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     42666920                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     42628268                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -604,333 +603,339 @@ system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5730809                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    132750441                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195556891                       # The number of ROB writes
-system.cpu.timesIdled                           46372                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          756091                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               5731649                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    132685351                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195501271                       # The number of ROB writes
+system.cpu.timesIdled                           46319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          679149                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.561783                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.561783                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.780048                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.780048                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                116466074                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57713698                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    255059                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   240376                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38265                       # number of misc regfile reads
+system.cpu.cpi                               0.560274                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.560274                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.784841                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.784841                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                116453986                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57709287                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    255067                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   240450                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38270                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            201297                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.745765                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            33997888                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205393                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.526031                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         229746500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.745765                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993834                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993834                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            201399                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.676822                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            33995451                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205495                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.432011                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         229821500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.676822                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993818                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993818                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2788                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1232                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2778                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1242                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70843209                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70843209                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20436554                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20436554                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13561278                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13561278                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           56                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           56                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      33997832                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         33997832                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     33997832                       # number of overall hits
-system.cpu.dcache.overall_hits::total        33997832                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       268921                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        268921                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1052099                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1052099                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1321020                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1321020                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1321020                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1321020                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  17355062000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  17355062000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  89131929604                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  89131929604                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 106486991604                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 106486991604                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 106486991604                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 106486991604                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20705475                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20705475                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70838999                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70838999                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20434147                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20434147                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13561246                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13561246                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           58                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           58                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      33995393                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         33995393                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     33995393                       # number of overall hits
+system.cpu.dcache.overall_hits::total        33995393                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       269170                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        269170                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1052131                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1052131                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1321301                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1321301                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1321301                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1321301                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  17282869000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  17282869000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  89120990413                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  89120990413                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 106403859413                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 106403859413                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 106403859413                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 106403859413                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20703317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20703317                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           56                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           56                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35318852                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35318852                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35318852                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35318852                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012988                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012988                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071996                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071996                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037403                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037403                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037403                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037403                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64535.912034                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 64535.912034                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84718.196295                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 84718.196295                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 80609.674043                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 80609.674043                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 80609.674043                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 80609.674043                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      6869550                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           58                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           58                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35316694                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35316694                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35316694                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35316694                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013001                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.013001                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071998                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.071998                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037413                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037413                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037413                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037413                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64208.006093                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 64208.006093                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84705.222461                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 84705.222461                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 80529.613928                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 80529.613928                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 80529.613928                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 80529.613928                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      6870751                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          275                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             88969                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             89149                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.212849                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.070421                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168788                       # number of writebacks
-system.cpu.dcache.writebacks::total            168788                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       206925                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       206925                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908702                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       908702                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1115627                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1115627                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1115627                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1115627                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61996                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61996                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143397                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143397                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205393                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205393                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205393                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205393                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3212836500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3212836500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14233206202                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  14233206202                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17446042702                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17446042702                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17446042702                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17446042702                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002994                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002994                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005815                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005815                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005815                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005815                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51823.286986                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51823.286986                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99257.349889                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99257.349889                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84939.811493                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84939.811493                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84939.811493                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84939.811493                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       168802                       # number of writebacks
+system.cpu.dcache.writebacks::total            168802                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207068                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       207068                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908738                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       908738                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1115806                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1115806                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1115806                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1115806                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62102                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62102                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143393                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143393                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205495                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205495                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205495                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205495                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3198491500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3198491500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14240616218                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14240616218                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17439107718                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17439107718                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17439107718                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17439107718                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003000                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003000                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009812                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009812                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005819                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005819                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005819                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005819                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51503.840456                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51503.840456                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99311.794983                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99311.794983                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84863.902859                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 84863.902859                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84863.902859                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 84863.902859                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             91498                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1915.935564                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13655300                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             93546                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            145.974173                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       18815415500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1915.935564                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.935515                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.935515                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             91476                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1915.700741                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13644579                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             93524                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            145.893878                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       18771424500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1915.700741                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.935401                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.935401                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1476                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1477                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          380                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27617236                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27617236                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13655300                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13655300                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13655300                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13655300                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13655300                       # number of overall hits
-system.cpu.icache.overall_hits::total        13655300                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       106545                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        106545                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       106545                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         106545                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       106545                       # number of overall misses
-system.cpu.icache.overall_misses::total        106545                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2015171999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2015171999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2015171999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2015171999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2015171999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2015171999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13761845                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13761845                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13761845                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13761845                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13761845                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13761845                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007742                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007742                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007742                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007742                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007742                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007742                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18913.811056                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18913.811056                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18913.811056                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18913.811056                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18913.811056                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18913.811056                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1468                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          27594820                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27594820                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13644579                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13644579                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        13644579                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       106069                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        106069                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       106069                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         106069                       # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total        106069                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1942429499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1942429499                       # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::total   1942429499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13750648                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::cpu.inst     13750648                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13750648                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007714                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007714                       # miss rate for ReadReq accesses
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+system.cpu.icache.overall_miss_rate::total     0.007714                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18312.885942                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18312.885942                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18312.885942                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18312.885942                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18312.885942                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18312.885942                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1399                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                19                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    77.263158                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    99.928571                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12998                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        12998                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        12998                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        12998                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        12998                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        12998                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93547                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        93547                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        93547                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        93547                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        93547                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        93547                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1645041500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1645041500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1645041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1645041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1645041500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1645041500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006798                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006798                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006798                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006798                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006798                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006798                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17585.187125                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17585.187125                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17585.187125                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17585.187125                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17585.187125                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17585.187125                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        91476                       # number of writebacks
+system.cpu.icache.writebacks::total             91476                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12544                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        12544                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        12544                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst        12544                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        12544                       # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_miss_latency::total   1588807000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1588807000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total   1588807000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006801                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006801                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006801                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16988.045977                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16988.045977                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16988.045977                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132064                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30597.382084                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             281892                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164129                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.717503                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           133079                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30599.466713                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             282960                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           165171                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.713134                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26451.406117                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2221.195572                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1924.780395                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.807233                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.067786                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.058740                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.933758                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32065                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3040                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28434                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          367                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978546                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          5041408                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         5041408                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       168788                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168788                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12616                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12616                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        86178                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        86178                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34172                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        34172                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        86178                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46788                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          132966                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        86178                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46788                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         132966                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130783                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130783                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         7369                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         7369                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27822                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        27822                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         7369                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158605                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        165974                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         7369                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158605                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       165974                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13881530500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13881530500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    599246500                       # number of ReadCleanReq miss cycles
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -939,122 +944,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.writebacks::total           114348                       # number of writebacks
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 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89063.996118                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71321.278328                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94900.154472                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93853.287262                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912060                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912060                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.068506                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448624                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448624                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.772009                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.551973                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772009                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.551973                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96197.631209                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96197.631209                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72605.587639                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88379.055994                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88379.055994                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94824.585235                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93962.081417                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94824.585235                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93962.081417                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       591735                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       292795                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       591895                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       292875                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         4025                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4025                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         4047                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4047                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        155540                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       283136                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       141723                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143399                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143399                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        93547                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        61994                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       278591                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612083                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            890674                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5986944                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23947584                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           29934528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      132064                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       723799                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.005561                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.074364                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        155625                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       283215                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        91476                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        51263                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143394                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143394                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        93525                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        62101                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       278525                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612389                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            890914                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11840000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23955008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           35795008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      133079                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       432099                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.009366                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.096323                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             719774     99.44%     99.44% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4025      0.56%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             428052     99.06%     99.06% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               4047      0.94%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         723799                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      464655500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     140327982                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         432099                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      556225500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     140299972                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     308097983                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     308258967                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              35190                       # Transaction distribution
-system.membus.trans_dist::Writeback            114348                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            15746                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130783                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130783                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         35190                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462040                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 462040                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17940544                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17940544                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              34266                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       114413                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14730                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130784                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130784                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34266                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       459243                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 459243                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17885632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17885632                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            296067                       # Request fanout histogram
+system.membus.snoop_fanout::samples            294193                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  296067    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  294193    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              296067                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           778875000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              294193                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           777045500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          857731250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          852834000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index 67f744153..c1732fe78 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,77 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.056991                       # Number of seconds simulated
-sim_ticks                                 56991022500                       # Number of ticks simulated
-final_tick                                56991022500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.056961                       # Number of seconds simulated
+sim_ticks                                 56960656500                       # Number of ticks simulated
+final_tick                                56960656500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 186679                       # Simulator instruction rate (inst/s)
-host_op_rate                                   238735                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              150024942                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 325676                       # Number of bytes of host memory used
-host_seconds                                   379.88                       # Real time elapsed on the host
+host_inst_rate                                 199606                       # Simulator instruction rate (inst/s)
+host_op_rate                                   255266                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              160327771                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 325784                       # Number of bytes of host memory used
+host_seconds                                   355.28                       # Real time elapsed on the host
 sim_insts                                    70915128                       # Number of instructions simulated
 sim_ops                                      90690084                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            318720                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7923904                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8242624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       318720                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          318720                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5514048                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5514048                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               4980                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             123811                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128791                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           86157                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                86157                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              5592460                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            139037758                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               144630218                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5592460                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5592460                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          96752923                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               96752923                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          96752923                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5592460                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           139037758                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              241383141                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128791                       # Number of read requests accepted
-system.physmem.writeReqs                        86157                       # Number of write requests accepted
-system.physmem.readBursts                      128791                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      86157                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8242176                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5512640                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8242624                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5514048                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            285184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7924608                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8209792                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       285184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          285184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5517504                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5517504                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4456                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             123822                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128278                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           86211                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                86211                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              5006684                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            139124239                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               144130923                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5006684                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5006684                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          96865176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               96865176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          96865176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5006684                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           139124239                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              240996099                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128278                       # Number of read requests accepted
+system.physmem.writeReqs                        86211                       # Number of write requests accepted
+system.physmem.readBursts                      128278                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      86211                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8209408                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5515712                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8209792                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5517504                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8144                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8370                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8248                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8170                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8315                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8436                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8084                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7955                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8060                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7629                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7815                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               7829                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               7881                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7878                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7975                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               7995                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5393                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           6908                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                8061                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8314                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8233                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8140                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8284                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8402                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8056                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7915                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8035                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7586                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7763                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               7815                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               7871                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7867                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7968                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               7962                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5394                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                5541                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5464                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5326                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5352                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5547                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5252                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5180                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                5465                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5335                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5367                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5560                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5259                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5181                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                5155                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                5101                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5292                       # Per bank write bursts
@@ -79,27 +79,27 @@ system.physmem.perBankWrBursts::11               5270                       # Pe
 system.physmem.perBankWrBursts::12               5531                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               5597                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               5703                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5431                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5432                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     56990990500                       # Total gap between requests
+system.physmem.totGap                     56960630500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128791                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128278                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  86157                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    116650                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     12110                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        24                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  86211                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    116041                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     12210                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5285                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5310                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5310                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5336                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      661                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5327                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5368                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5453                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5463                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     5922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5462                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       18                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
@@ -193,98 +193,98 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38662                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      355.683203                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     216.343519                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     336.125731                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12148     31.42%     31.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8177     21.15%     52.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4090     10.58%     63.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2852      7.38%     70.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2693      6.97%     77.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1623      4.20%     81.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1296      3.35%     85.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1161      3.00%     88.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4622     11.95%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38662                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        38843                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      353.305769                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     214.370646                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.820424                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12327     31.74%     31.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8308     21.39%     53.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4009     10.32%     63.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2908      7.49%     70.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2579      6.64%     77.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1645      4.23%     81.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1295      3.33%     85.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1183      3.05%     88.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4589     11.81%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38843                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5293                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.322124                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      352.056892                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.231438                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      352.038332                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-1023           5291     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            5293                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          5293                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.273380                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.256688                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.768255                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4654     87.93%     87.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  4      0.08%     88.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                500      9.45%     97.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                109      2.06%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 18      0.34%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  5      0.09%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  2      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.282449                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.265601                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.771117                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4623     87.34%     87.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  6      0.11%     87.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                534     10.09%     97.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                111      2.10%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 13      0.25%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  2      0.04%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  2      0.04%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5293                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1683428000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4098128000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    643920000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13071.72                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     1678352000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4083452000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    641360000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13084.32                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31821.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         144.62                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          96.73                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      144.63                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       96.75                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31834.32                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         144.12                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          96.83                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      144.13                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       96.87                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.89                       # Data bus utilization in percentage
+system.physmem.busUtil                           1.88                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.13                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.51                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     112096                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64153                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.04                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.46                       # Row buffer hit rate for writes
-system.physmem.avgGap                       265138.50                       # Average gap between requests
-system.physmem.pageHitRate                      82.00                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  151963560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   82916625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 512397600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                278957520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3722150640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11726025750                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            23906742000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              40381153695                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              708.591931                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    39643767750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1902940000                       # Time in different power states
+system.physmem.avgWrQLen                        23.44                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     111810                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     63793                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.17                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                       265564.34                       # Average gap between requests
+system.physmem.pageHitRate                      81.87                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  153158040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   83568375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 509862600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                279223200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3720116400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11565367830                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            24028947750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              40340244195                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              708.261877                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    39847901500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1901900000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     15441187500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     15206891000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  140313600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   76560000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 491751000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                  140419440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   76617750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 490214400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                279138960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3722150640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11059172775                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24491665500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              40260752475                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              706.479908                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40617302250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1902940000                       # Time in different power states
+system.physmem_1.refreshEnergy             3720116400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            10938128715                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24579157500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              40223793165                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              706.217322                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40763292250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1901900000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     14467595250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     14291603250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14800541                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9905717                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            381681                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9438549                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6732145                       # Number of BTB hits
+system.cpu.branchPred.lookups                14800638                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9905777                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            381686                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9438449                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6732187                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             71.326059                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1714124                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             71.327259                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1714133                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -404,67 +404,67 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        113982045                       # number of cpu cycles simulated
+system.cpu.numCycles                        113921313                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915128                       # Number of instructions committed
 system.cpu.committedOps                      90690084                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1144890                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1144928                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.607302                       # CPI: cycles per instruction
-system.cpu.ipc                               0.622161                       # IPC: instructions per cycle
-system.cpu.tickCycles                        95587829                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        18394216                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            156435                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.142814                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42624094                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            160531                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.519395                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.606446                       # CPI: cycles per instruction
+system.cpu.ipc                               0.622492                       # IPC: instructions per cycle
+system.cpu.tickCycles                        95595424                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        18325889                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            156436                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4067.127430                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42624259                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            160532                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            265.518769                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         822760500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.142814                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992955                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992955                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.127430                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992951                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992951                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1110                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2940                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1105                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2947                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86016729                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86016729                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22866654                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22866654                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19642187                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642187                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        83415                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         83415                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          86016734                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         86016734                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22866824                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22866824                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19642179                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19642179                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83418                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83418                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42508841                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42508841                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42592256                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42592256                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        51701                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         51701                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       207714                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207714                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        44590                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        44590                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       259415                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         259415                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       304005                       # number of overall misses
-system.cpu.dcache.overall_misses::total        304005                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1492164500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1492164500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  16804934500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  16804934500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18297099000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18297099000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18297099000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18297099000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22918355                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22918355                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      42509003                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42509003                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42592421                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42592421                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        51533                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         51533                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       207722                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       207722                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        44587                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        44587                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       259255                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         259255                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       303842                       # number of overall misses
+system.cpu.dcache.overall_misses::total        303842                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1489955500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1489955500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  16807631000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  16807631000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  18297586500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18297586500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18297586500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18297586500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22918357                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22918357                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data       128005                       # number of SoftPFReq accesses(hits+misses)
@@ -473,28 +473,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42768256                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42768256                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42896261                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42896261                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002256                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002256                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.348346                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.348346                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.006066                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.006066                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007087                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007087                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28861.424344                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28861.424344                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80904.197599                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80904.197599                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70532.155041                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70532.155041                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60186.835743                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60186.835743                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     42768258                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42768258                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42896263                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42896263                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002249                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002249                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010465                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.010465                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.348322                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.348322                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006062                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006062                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007083                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007083                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28912.648206                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28912.648206                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80914.063027                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 80914.063027                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70577.564560                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70577.564560                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60220.728207                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60220.728207                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -503,36 +503,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128400                       # number of writebacks
-system.cpu.dcache.writebacks::total            128400                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22183                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        22183                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100686                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100686                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       122869                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       122869                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       122869                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       122869                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29518                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        29518                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       128377                       # number of writebacks
+system.cpu.dcache.writebacks::total            128377                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22014                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        22014                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100694                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       100694                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       122708                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       122708                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       122708                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       122708                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29519                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        29519                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107028                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       107028                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23985                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total        23985                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       136546                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       136546                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       160531                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       160531                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    578376000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    578376000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8484284000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8484284000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1716349500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1716349500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9062660000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9062660000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10779009500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10779009500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       136547                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       136547                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       160532                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160532                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    577658500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    577658500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8488450500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8488450500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1712416500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1712416500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9066109000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9066109000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10778525500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10778525500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
@@ -543,70 +543,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003193
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003193                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19594.010434                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19594.010434                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79271.629854                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79271.629854                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71559.287054                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71559.287054                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66370.746855                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66370.746855                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67145.968691                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67145.968691                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19569.040279                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19569.040279                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79310.558919                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79310.558919                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71395.309568                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71395.309568                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66395.519491                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66395.519491                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67142.535445                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67142.535445                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             42866                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1852.547846                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24941084                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             44908                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            555.381758                       # Average number of references to valid blocks.
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+system.cpu.icache.tags.sampled_refs             44910                       # Sample count of references to valid blocks.
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 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1852.547846                       # Average occupied blocks per requestor
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 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
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 system.cpu.icache.tags.age_task_id_blocks_1024::3          918                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1004                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          50016894                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         50016894                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24941084                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24941084                       # number of ReadReq hits
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-system.cpu.icache.overall_hits::total        24941084                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        44909                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         44909                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        44909                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          44909                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        44909                       # number of overall misses
-system.cpu.icache.overall_misses::total         44909                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    929470000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    929470000                       # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::total    929470000                       # number of overall miss cycles
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 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001797                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.001797                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.001797                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.001797                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001797                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001797                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20696.742301                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20696.742301                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20696.742301                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20696.742301                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20696.742301                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20696.742301                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19966.711941                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19966.711941                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19966.711941                       # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19966.711941                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19966.711941                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -615,129 +615,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44909                       # number of ReadReq MSHR misses
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001797                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.001797                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.001797                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19696.764568                       # average ReadReq mshr miss latency
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19696.764568                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 18966.734208                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            95654                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29860.905704                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             161645                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26579.253739                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1620.855600                       # Average occupied blocks per requestor
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 system.cpu.l2cache.ReadExReq_accesses::cpu.data       107028                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       107028                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        44909                       # number of ReadCleanReq accesses(hits+misses)
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-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955600                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955600                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.111136                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.111136                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.403716                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.403716                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111136                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.771664                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.627273                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.data     0.771664                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.627273                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80896.808635                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80896.808635                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79002.304147                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79002.304147                       # average ReadCleanReq miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86810.092593                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79002.304147                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81927.895638                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81814.587908                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79002.304147                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81927.895638                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81814.587908                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79633.333333                       # average ReadCleanReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79633.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81919.041200                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81839.440142                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -746,132 +752,133 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        86157                       # number of writebacks
-system.cpu.l2cache.writebacks::total            86157                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           10                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           10                       # number of ReadCleanReq MSHR hits
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-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           65                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           65                       # number of demand (read+write) MSHR hits
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+system.cpu.l2cache.demand_mshr_hits::cpu.data           62                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           75                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           10                       # number of overall MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::total           75                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1374                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         1374                       # number of CleanEvict MSHR misses
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+system.cpu.l2cache.overall_mshr_miss_latency::total   9215652000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955600                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955600                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.110913                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.110913                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.402501                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402501                       # mshr miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771259                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.626908                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.110913                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771259                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.626908                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70896.808635                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70896.808635                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69031.419394                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69031.419394                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76857.975389                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76857.975389                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69031.419394                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71933.660983                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71821.417479                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69031.419394                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71933.660983                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71821.417479                       # average overall mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70936.803974                       # average ReadExReq mshr miss latency
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+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76581.805523                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69664.236033                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71919.032967                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71840.690994                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69664.236033                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71919.032967                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71840.690994                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       404741                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       199337                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       404747                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       199340                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7814                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3360                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3331                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         3362                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3333                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           29                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         98411                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       214557                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        72584                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         98414                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       214588                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        39288                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        34000                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       107028                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       107028                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        44909                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        53503                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       129104                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       473262                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            602366                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2874112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18491584                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           21365696                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       95654                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       500395                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.038076                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.191682                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        44911                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        53504                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       129109                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       473266                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            602375                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5388672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18490176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           23878848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       96386                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       301829                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.037243                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.189864                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             481371     96.20%     96.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              18995      3.80%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             290617     96.29%     96.29% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              11183      3.71%     99.99% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                 29      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         500395                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      330770500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      67369485                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         301829                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      373618500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      67384461                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     240829933                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     240832431                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              26515                       # Transaction distribution
-system.membus.trans_dist::Writeback             86157                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7510                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102276                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102276                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         26515                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       351249                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 351249                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13756672                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13756672                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              26001                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        86211                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6908                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102277                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102277                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         26001                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       349675                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 349675                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13727296                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13727296                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            222458                       # Request fanout histogram
+system.membus.snoop_fanout::samples            221397                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  222458    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  221397    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              222458                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           591531500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              221397                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           590585500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          679686000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          676907000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 4fc60452d..6b580b547 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,119 +1,119 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.033346                       # Number of seconds simulated
-sim_ticks                                 33346420000                       # Number of ticks simulated
-final_tick                                33346420000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.033788                       # Number of seconds simulated
+sim_ticks                                 33787619000                       # Number of ticks simulated
+final_tick                                33787619000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 116263                       # Simulator instruction rate (inst/s)
-host_op_rate                                   148687                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54676178                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 326572                       # Number of bytes of host memory used
-host_seconds                                   609.89                       # Real time elapsed on the host
+host_inst_rate                                 117892                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150770                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56175899                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 326928                       # Number of bytes of host memory used
+host_seconds                                   601.46                       # Real time elapsed on the host
 sim_insts                                    70907630                       # Number of instructions simulated
 sim_ops                                      90682585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            581760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           2519040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher      6191552                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9292352                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       581760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          581760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6257152                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6257152                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               9090                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              39360                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        96743                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                145193                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97768                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97768                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             17445951                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             75541542                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher    185673665                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               278661158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        17445951                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           17445951                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         187640892                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              187640892                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         187640892                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            17445951                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            75541542                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher    185673665                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              466302050                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        145193                       # Number of read requests accepted
-system.physmem.writeReqs                        97768                       # Number of write requests accepted
-system.physmem.readBursts                      145193                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97768                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9285376                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6976                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6255360                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9292352                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6257152                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      109                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              6                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9137                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9395                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9161                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                9548                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9715                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9765                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9098                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                9032                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9205                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8593                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8826                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8653                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               8623                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               8667                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8699                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8967                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5976                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6230                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6094                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6205                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6124                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6340                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6054                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6041                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6001                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6103                       # Per bank write bursts
+system.physmem.bytes_read::cpu.inst            736896                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           2854400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher      6176576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9767872                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       736896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          736896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6229632                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6229632                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              11514                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              44600                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        96509                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                152623                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97338                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97338                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             21809646                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             84480650                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher    182805897                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               289096192                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        21809646                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           21809646                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         184376176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              184376176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         184376176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            21809646                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            84480650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher    182805897                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              473472369                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        152624                       # Number of read requests accepted
+system.physmem.writeReqs                        97338                       # Number of write requests accepted
+system.physmem.readBursts                      152624                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97338                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9758080                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9856                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6227712                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9767936                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6229632                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      154                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       1                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          27837                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9027                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9355                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9548                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12185                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10599                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10432                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9787                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                9285                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9499                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9569                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9134                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8776                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               8706                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               8772                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8686                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9110                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5979                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6226                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6146                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6158                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6081                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6325                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6021                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5966                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5954                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6102                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               6248                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5916                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6074                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6102                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6204                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6028                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5872                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6030                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6061                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6151                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5988                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     33346162500                       # Total gap between requests
+system.physmem.totGap                     33787609500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  145193                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  152624                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97768                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     41267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     55036                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14561                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     10407                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6013                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5200                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4615                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4275                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3568                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        90                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       40                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97338                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     49823                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     54272                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13781                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     10225                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5327                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4741                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4387                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3645                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        77                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       35                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
@@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1892                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2595                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4284                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6229                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6535                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7588                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8293                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6877                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1280                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2913                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3782                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7521                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8929                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6643                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
@@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        88566                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      175.437436                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     110.610569                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     239.212794                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          52129     58.86%     58.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22374     25.26%     84.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4601      5.19%     89.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1696      1.91%     91.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1069      1.21%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          812      0.92%     93.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          692      0.78%     94.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          790      0.89%     95.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4403      4.97%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          88566                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5908                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.550271                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       21.061813                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      186.955752                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            5907     99.98%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5908                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5908                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.543670                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.503041                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.228970                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4711     79.74%     79.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 35      0.59%     80.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                768     13.00%     93.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                163      2.76%     96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                108      1.83%     97.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 61      1.03%     98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 38      0.64%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.17%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 10      0.17%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  3      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5908                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     7011292666                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9731617666                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    725420000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       48325.75                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        95484                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      167.396422                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     105.401782                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     235.895158                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          59753     62.58%     62.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22097     23.14%     85.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4150      4.35%     90.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1579      1.65%     91.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          956      1.00%     92.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          842      0.88%     93.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          589      0.62%     94.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          882      0.92%     95.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4636      4.86%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          95484                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5850                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.058462                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      198.495488                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            5849     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14848-15359            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5850                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5850                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.633846                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.583273                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.382653                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4554     77.85%     77.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 25      0.43%     78.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                781     13.35%     91.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                204      3.49%     95.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                105      1.79%     96.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 84      1.44%     98.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 47      0.80%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 32      0.55%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  8      0.14%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  5      0.09%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  3      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5850                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6712073801                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9570886301                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    762350000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       44022.26                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  67075.75                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         278.45                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         187.59                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      278.66                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      187.64                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  62772.26                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         288.81                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         184.32                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      289.10                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      184.38                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.64                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.18                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.47                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.62                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.60                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     118088                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     36158                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.39                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  36.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                       137249.03                       # Average gap between requests
-system.physmem.pageHitRate                      63.51                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  342241200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  186738750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 583385400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                317818080                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             2177653920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11790659475                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             9661917750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              25060414575                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              751.639504                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    15978647517                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1113320000                       # Time in different power states
+system.physmem.busUtil                           3.70                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.26                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.44                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.40                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     121004                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     33280                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.36                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  34.19                       # Row buffer hit rate for writes
+system.physmem.avgGap                       135170.98                       # Average gap between requests
+system.physmem.pageHitRate                      61.76                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  375641280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  204963000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 625404000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                316826640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             2206641840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            15342350850                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             6812703000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              25884530610                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              766.158096                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    11227638574                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1128140000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16249048233                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     21429077176                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  326909520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  178373250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 547528800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                315329760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             2177653920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11234568330                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            10149705000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              24930068580                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              747.730472                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    16793127980                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1113320000                       # Time in different power states
+system.physmem_1.actEnergy                  346043880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  188813625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 563401800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                313625520                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             2206641840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13705423425                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             8248614750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              25572564840                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              756.923807                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    13625050098                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1128140000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     15434548270                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     19031683152                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17208509                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11519539                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            648302                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9342884                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7675123                       # Number of BTB hits
+system.cpu.branchPred.lookups                17216173                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11524251                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            650211                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9349330                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7678783                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             82.149398                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1872388                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             101556                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             82.131907                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1872954                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             101563                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -411,95 +412,95 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         66692841                       # number of cpu cycles simulated
+system.cpu.numCycles                         67575239                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5046776                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       88195647                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17208509                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9547511                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      60140641                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1322595                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 6428                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            25                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        13633                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22763338                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 69414                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           65868800                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.694437                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.296898                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            5134859                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       88248834                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17216173                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9551737                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      60707500                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1326839                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 5350                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            27                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        12635                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22778595                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 70008                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           66523790                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.678669                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.300955                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 20089005     30.50%     30.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  8265359     12.55%     43.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9198123     13.96%     57.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 28316313     42.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 20715769     31.14%     31.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8270385     12.43%     43.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9211836     13.85%     57.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 28325800     42.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             65868800                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.258026                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.322416                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8616725                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              19555814                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  31576285                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               5627882                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 492094                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3179727                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                171045                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              101400911                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3043244                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 492094                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13372904                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5353130                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         801467                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  32232883                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13616322                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               99196979                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                981006                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3848899                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  63135                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                4311075                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                5311261                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           103921430                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             457681852                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        115406862                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             66523790                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.254770                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.305934                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8696241                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              20116868                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  31576119                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5641245                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 493317                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3182236                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                172097                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              101426011                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3049995                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 493317                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13462916                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5983097                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         839028                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  32232549                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13512883                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               99220100                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                979828                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3816376                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  66808                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4343458                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5148151                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           103925700                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             457807646                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        115438955                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               552                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 10292204                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              18659                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          18650                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12699652                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             24320213                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21993792                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1400092                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2341142                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   98161647                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               34523                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  94891012                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            695609                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7513585                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     20245943                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            737                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      65868800                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.440606                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.149928                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 10296474                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              18669                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          18667                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12740509                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             24326602                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            22004719                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1418947                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2350394                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   98183255                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               34522                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  94912265                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            694103                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7535192                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     20267739                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            736                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      66523790                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.426742                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.152135                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17598833     26.72%     26.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17429188     26.46%     53.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17113322     25.98%     79.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            11675618     17.73%     96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2050869      3.11%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 970      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            18209770     27.37%     27.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17473699     26.27%     53.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17129113     25.75%     79.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            11665460     17.54%     96.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2044780      3.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 968      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        65868800                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        66523790                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 6712111     22.40%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     39      0.00%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 6707680     22.40%     22.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     41      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.40% # attempts to use FU when none available
@@ -527,13 +528,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.40% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11183885     37.33%     59.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              12062879     40.26%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11186120     37.35%     59.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              12052780     40.25%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49494737     52.16%     52.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                89878      0.09%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49503200     52.16%     52.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                89866      0.09%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
@@ -554,91 +555,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Ty
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              9      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24064392     25.36%     77.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21241967     22.39%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24070106     25.36%     77.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21249051     22.39%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               94891012                       # Type of FU issued
-system.cpu.iq.rate                           1.422807                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    29958914                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.315719                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          286305140                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         105721004                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     93462242                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           57                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              124849808                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     118                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1363438                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               94912265                       # Type of FU issued
+system.cpu.iq.rate                           1.404542                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    29946621                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.315519                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          286988829                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         105764420                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     93479370                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 215                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                254                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           62                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              124858764                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     122                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1365617                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1453951                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2082                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11760                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1438054                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1460340                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2088                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11950                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1448981                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       138729                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        184462                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       137954                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        185768                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 492094                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  624554                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                468032                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            98206039                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 493317                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  628934                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                513918                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            98227667                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              24320213                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21993792                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              18603                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1634                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                463552                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11760                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         302690                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       221650                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               524340                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              93974044                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23757485                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            916968                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              24326602                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             22004719                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              18602                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1669                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                509191                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11950                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         303594                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       221648                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               525242                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93991933                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23762441                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            920332                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9869                       # number of nop insts executed
-system.cpu.iew.exec_refs                     44742217                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14251815                       # Number of branches executed
-system.cpu.iew.exec_stores                   20984732                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.409057                       # Inst execution rate
-system.cpu.iew.wb_sent                       93584291                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      93462299                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  44972986                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  76550519                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          9890                       # number of nop insts executed
+system.cpu.iew.exec_refs                     44753885                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14253415                       # Number of branches executed
+system.cpu.iew.exec_stores                   20991444                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.390923                       # Inst execution rate
+system.cpu.iew.wb_sent                       93601796                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      93479432                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  44975266                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  76559860                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.401384                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.587494                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.383339                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.587452                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         6533064                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         6553334                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            479099                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     64811353                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.399263                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.164401                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            480109                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     65462437                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.385346                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.157754                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     31214732     48.16%     48.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16807105     25.93%     74.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4339311      6.70%     80.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4161583      6.42%     87.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1937068      2.99%     90.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1261836      1.95%     92.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       738743      1.14%     93.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       580049      0.89%     94.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3770926      5.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     31857215     48.66%     48.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16813031     25.68%     74.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4347273      6.64%     80.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4157866      6.35%     87.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1935310      2.96%     90.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1259510      1.92%     92.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       744006      1.14%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       581672      0.89%     94.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3766554      5.75%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     64811353                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     65462437                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913182                       # Number of instructions committed
 system.cpu.commit.committedOps               90688137                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -684,386 +685,386 @@ system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          90688137                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3770926                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    158236329                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195501562                       # The number of ROB writes
-system.cpu.timesIdled                           24613                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          824041                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3766554                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    158912055                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195546008                       # The number of ROB writes
+system.cpu.timesIdled                           28044                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1051449                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907630                       # Number of Instructions Simulated
 system.cpu.committedOps                      90682585                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.940559                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.940559                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.063197                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.063197                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                102271310                       # number of integer regfile reads
-system.cpu.int_regfile_writes                56791274                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 346086877                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 38805113                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                44208470                       # number of misc regfile reads
+system.cpu.cpi                               0.953004                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.953004                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.049314                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.049314                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                102290506                       # number of integer regfile reads
+system.cpu.int_regfile_writes                56802248                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        40                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       24                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 346154538                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 38804906                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                44219892                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            485016                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           510.742621                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40419295                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            485528                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             83.248124                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         152905500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   510.742621                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997544                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997544                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            485017                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           510.752563                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40412566                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            485529                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             83.234093                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         153371500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   510.752563                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997564                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997564                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          456                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84611982                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84611982                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21497006                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21497006                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18830802                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18830802                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        60196                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         60196                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15349                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15349                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          84615901                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84615901                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21489624                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21489624                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18831353                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18831353                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        60282                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         60282                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15348                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15348                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40327808                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40327808                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40388004                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40388004                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       555640                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        555640                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1019099                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1019099                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        68639                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        68639                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data      40320977                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40320977                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40381259                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40381259                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       564963                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        564963                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1018548                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1018548                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        68572                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        68572                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data          577                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total          577                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1574739                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1574739                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1643378                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1643378                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9002363000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9002363000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  14580629410                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  14580629410                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5329000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      5329000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  23582992410                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  23582992410                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  23582992410                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  23582992410                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22052646                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22052646                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      1583511                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1583511                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1652083                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1652083                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9256149500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9256149500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  14245975429                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  14245975429                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5465000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      5465000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  23502124929                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  23502124929                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  23502124929                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  23502124929                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22054587                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22054587                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128835                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128835                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128854                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128854                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15925                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        15925                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41902547                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41902547                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42031382                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42031382                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025196                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025196                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051340                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.051340                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532767                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.532767                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036230                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036230                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037581                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037581                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039099                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039099                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16201.790728                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16201.790728                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14307.372895                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 14307.372895                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9235.701906                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9235.701906                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14975.810220                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14975.810220                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14350.315271                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14350.315271                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           29                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3096615                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          130248                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     4.833333                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    23.774760                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     41904488                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41904488                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42033342                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42033342                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025617                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025617                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051312                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.051312                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532168                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.532168                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036232                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036232                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037789                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037789                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039304                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039304                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16383.638398                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16383.638398                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13986.552847                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 13986.552847                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9471.403813                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9471.403813                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14841.781919                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14841.781919                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14225.753143                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14225.753143                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          112                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      2896869                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                15                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          131288                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.466667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    22.064995                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       253749                       # number of writebacks
-system.cpu.dcache.writebacks::total            253749                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       256216                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       256216                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870580                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       870580                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       485017                       # number of writebacks
+system.cpu.dcache.writebacks::total            485017                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       265550                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       265550                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870019                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       870019                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          577                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total          577                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1126796                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1126796                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1126796                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1126796                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299424                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       299424                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148519                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       148519                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37595                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        37595                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       447943                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       447943                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       485538                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       485538                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3220458500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3220458500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2349684961                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2349684961                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2014368500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2014368500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5570143461                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5570143461                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7584511961                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7584511961                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013578                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013578                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007482                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007482                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291807                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291807                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data      1135569                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1135569                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1135569                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1135569                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299413                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       299413                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148529                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       148529                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37597                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        37597                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       447942                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       447942                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       485539                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       485539                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3625766000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3625766000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2305447971                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2305447971                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1884857000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1884857000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5931213971                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5931213971                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7816070971                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7816070971                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013576                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013576                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291780                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291780                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010690                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.010690                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011552                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.011552                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10755.512250                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10755.512250                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.770144                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.770144                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53580.755420                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53580.755420                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12434.938064                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12434.938064                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15620.841131                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15620.841131                       # average overall mshr miss latency
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011551                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.011551                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12109.581080                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12109.581080                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15521.870954                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15521.870954                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50133.175519                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50133.175519                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13241.031140                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13241.031140                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16097.720206                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16097.720206                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            322602                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.289801                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22429330                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            323114                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             69.416150                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        1108313500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.289801                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996660                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996660                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            323105                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.281102                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22444187                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            323617                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             69.354166                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        1133816500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.281102                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996643                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996643                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          350                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          341                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45849556                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45849556                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22429330                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22429330                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22429330                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22429330                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22429330                       # number of overall hits
-system.cpu.icache.overall_hits::total        22429330                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       333886                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        333886                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       333886                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         333886                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       333886                       # number of overall misses
-system.cpu.icache.overall_misses::total        333886                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   3387462898                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   3387462898                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   3387462898                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   3387462898                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   3387462898                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   3387462898                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22763216                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22763216                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22763216                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22763216                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22763216                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22763216                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014668                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014668                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014668                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014668                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014668                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014668                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10145.567343                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10145.567343                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10145.567343                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10145.567343                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10145.567343                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10145.567343                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       275055                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          45880575                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45880575                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22444187                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22444187                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22444187                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22444187                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22444187                       # number of overall hits
+system.cpu.icache.overall_hits::total        22444187                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       334287                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        334287                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       334287                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         334287                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       334287                       # number of overall misses
+system.cpu.icache.overall_misses::total        334287                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   3550514898                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   3550514898                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   3550514898                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   3550514898                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   3550514898                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   3550514898                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22778474                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22778474                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22778474                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22778474                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22778474                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22778474                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014676                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014676                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014676                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014676                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014676                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014676                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10621.157562                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10621.157562                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10621.157562                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10621.157562                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10621.157562                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10621.157562                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       261417                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           50                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs             16465                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs             16440                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.705436                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    15.901277                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets           25                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10762                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        10762                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        10762                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        10762                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        10762                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        10762                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323124                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       323124                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       323124                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       323124                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       323124                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       323124                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3106237439                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   3106237439                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3106237439                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   3106237439                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3106237439                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   3106237439                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014195                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014195                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014195                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014195                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014195                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014195                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9613.143682                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9613.143682                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9613.143682                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9613.143682                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9613.143682                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9613.143682                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       323105                       # number of writebacks
+system.cpu.icache.writebacks::total            323105                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10659                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        10659                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        10659                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        10659                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        10659                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        10659                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323628                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       323628                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       323628                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       323628                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       323628                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       323628                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3274041434                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   3274041434                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3274041434                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   3274041434                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3274041434                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   3274041434                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014208                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014208                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014208                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014208                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014208                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014208                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10116.681604                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10116.681604                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10116.681604                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 10116.681604                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10116.681604                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 10116.681604                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       824554                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       825997                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         1265                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       822385                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       826178                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         3328                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        78883                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           129320                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16077.798328                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1332136                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           145605                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.148972                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage        78886                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           128056                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15991.461548                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1186413                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           144416                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             8.215246                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 12580.729391                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1435.218060                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1954.277207                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   107.573670                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.767867                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087599                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.119280                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006566                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.981311                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022           27                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        16258                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           14                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2698                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11935                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          582                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          887                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001648                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.992310                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         24877336                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        24877336                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks       253749                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       253749                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       137176                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       137176                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       313988                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       313988                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       305816                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       305816                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       313988                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       442992                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          756980                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       313988                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       442992                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         756980                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        11383                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        11383                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9125                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         9125                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        31153                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        31153                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         9125                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        42536                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         51661                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         9125                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        42536                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        51661                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1232022000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1232022000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    709673500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    709673500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2693968000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2693968000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    709673500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   3925990000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   4635663500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    709673500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   3925990000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   4635663500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks       253749                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       253749                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.tags.occ_blocks::writebacks 15890.954967                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   100.506581                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.969907                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006134                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.976041                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022           34                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        16326                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           18                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2702                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12111                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          578                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          810                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.002075                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996460                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         24986640                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        24986640                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       253426                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       253426                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       474834                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       474834                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       137075                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       137075                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       312075                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       312075                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       300547                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       300547                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       312075                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       437622                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          749697                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       312075                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       437622                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         749697                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           10                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           10                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        11487                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        11487                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        11542                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        11542                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        36420                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        36420                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        11542                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        47907                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         59449                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        11542                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        47907                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        59449                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1187801500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1187801500                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3000401500                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.WritebackDirty_accesses::total       253426                       # number of WritebackDirty accesses(hits+misses)
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 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           10                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           10                       # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.600000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076623                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.076623                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.028241                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.028241                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.092451                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.092451                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.028241                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.087608                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.063886                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028241                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.087608                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.063886                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 108233.506106                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 108233.506106                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77772.438356                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77772.438356                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86475.395628                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86475.395628                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77772.438356                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92298.053414                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89732.360969                       # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92298.053414                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89732.360969                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.077321                       # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103403.978410                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103403.978410                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75578.669208                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75578.669208                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82383.347062                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82383.347062                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::total 85123.921344                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75578.669208                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87423.612416                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 85123.921344                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1072,159 +1073,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97768                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97768                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3059                       # number of ReadExReq MSHR hits
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-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          117                       # number of ReadSharedReq MSHR hits
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-system.cpu.l2cache.overall_mshr_hits::total         3211                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         3482                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total         3482                       # number of CleanEvict MSHR misses
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-system.cpu.l2cache.HardPFReq_mshr_misses::total       112450                       # number of HardPFReq MSHR misses
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-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10622734578                       # number of HardPFReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10622734578                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  14447414078                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
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 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056032                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056032                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.028133                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.028133                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.092103                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.092103                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028133                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.081066                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.059915                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028133                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.081066                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.055781                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.055781                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.035582                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.035582                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.107764                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.107764                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.035582                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.091859                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.069351                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.035582                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.091859                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.198976                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94466.292379                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17333.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17333.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80754.565113                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80754.565113                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71826.512651                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71826.512651                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80537.939812                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80537.939812                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71826.512651                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80583.752541                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78940.753354                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71826.512651                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80583.752541                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89791.262138                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.208803                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91619.328749                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        17300                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        17300                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78895.981658                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78895.981658                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69588.884064                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69588.884064                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76420.909867                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76420.909867                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69588.884064                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76880.795964                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75384.469393                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69588.884064                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76880.795964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86227.151487                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1616280                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       807659                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        79832                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        20376                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        20194                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          182                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        660093                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       351517                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       505600                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       141126                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests      1617289                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       808162                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        79873                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        67046                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        56613                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        10433                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp        660594                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       350764                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       474834                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        78545                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       142478                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           10                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           10                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       148559                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       148559                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       323124                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       336969                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       938319                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1406791                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2345110                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20679232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     47313728                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           67992960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      270457                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1886726                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.095537                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.294284                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       148562                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       148562                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       323628                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       336967                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       939793                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1406789                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2346582                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     39434560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     58959360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           98393920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      318372                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1127528                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.139590                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.372305                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1706655     90.46%     90.46% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             179889      9.53%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                182      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             980569     86.97%     86.97% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             136526     12.11%     99.07% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              10433      0.93%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1886726                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1061889000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          3.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     485111148                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     728499095                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1127528                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1616766500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          4.8                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy     485882115                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     728582930                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             136869                       # Transaction distribution
-system.membus.trans_dist::Writeback             97768                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            30364                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              8324                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             8324                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        136869                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       418530                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 418530                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15549504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15549504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             144336                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        97338                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            27827                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               10                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              10                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              8287                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             8287                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        144337                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       430432                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 430432                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15997504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15997504                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            273331                       # Request fanout histogram
+system.membus.snoop_fanout::samples            277799                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  273331    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  277799    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              273331                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           739892708                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              277799                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           747949896                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          756443702                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          797228853                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index 617d9f369..ce3c1254b 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.208801                       # Number of seconds simulated
-sim_ticks                                1208800797500                       # Number of ticks simulated
-final_tick                               1208800797500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.208729                       # Number of seconds simulated
+sim_ticks                                1208728699500                       # Number of ticks simulated
+final_tick                               1208728699500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 309355                       # Simulator instruction rate (inst/s)
-host_op_rate                                   309355                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              204748768                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299532                       # Number of bytes of host memory used
-host_seconds                                  5903.82                       # Real time elapsed on the host
+host_inst_rate                                 339450                       # Simulator instruction rate (inst/s)
+host_op_rate                                   339450                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              224654099                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 299384                       # Number of bytes of host memory used
+host_seconds                                  5380.40                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -18,71 +18,71 @@ system.physmem.bytes_read::cpu.data         124969728                       # Nu
 system.physmem.bytes_read::total            125030976                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        61248                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           61248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65417024                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65417024                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     65416576                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65416576                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                957                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data            1952652                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total               1953609                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1022141                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1022141                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                50668                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            103383228                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               103433896                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           50668                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              50668                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          54117291                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               54117291                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          54117291                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               50668                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           103383228                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              157551187                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::writebacks         1022134                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1022134                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                50671                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            103389394                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               103440066                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           50671                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              50671                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          54120148                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               54120148                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          54120148                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               50671                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           103389394                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              157560214                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                       1953609                       # Number of read requests accepted
-system.physmem.writeReqs                      1022141                       # Number of write requests accepted
+system.physmem.writeReqs                      1022134                       # Number of write requests accepted
 system.physmem.readBursts                     1953609                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1022141                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                124949504                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     81472                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65415744                       # Total number of bytes written to DRAM
+system.physmem.writeBursts                    1022134                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                124947712                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83264                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65415296                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                 125030976                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65417024                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1273                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytesWrittenSys               65416576                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1301                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118329                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         897725                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              118310                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              113529                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              115744                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117255                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              115745                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117258                       # Per bank write bursts
 system.physmem.perBankRdBursts::4              117308                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117125                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119396                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124121                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126643                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              129581                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128162                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             129917                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             125585                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             124851                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122145                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             122645                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61422                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61663                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60725                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61394                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61815                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117123                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119399                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124116                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126646                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              129571                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128166                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             129914                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             125584                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             124843                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122159                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             122637                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61419                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61661                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60723                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61396                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61819                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               63308                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               64356                       # Per bank write bursts
 system.physmem.perBankWrBursts::7               65855                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65579                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66031                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65643                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65948                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64510                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64527                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64896                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65578                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66028                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65644                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65946                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64498                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64533                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64901                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              64449                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1208800695000                       # Total gap between requests
+system.physmem.totGap                    1208728583000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -96,9 +96,9 @@ system.physmem.writePktSize::2                      0                       # Wr
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1022141                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1830062                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    122257                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1022134                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1829960                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    122331                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    30676                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    32058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55267                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    59672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    60060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60201                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    60176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    60139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    60194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    60147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    60253                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    60193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    61081                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    60653                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    61102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59618                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    30641                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    31976                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    59652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    60231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    60228                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    60672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    61063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    60669                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59820                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59627                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
@@ -193,31 +193,31 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1831783                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.923052                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.128953                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     130.461416                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1453465     79.35%     79.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       261783     14.29%     93.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        48685      2.66%     96.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20654      1.13%     97.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13128      0.72%     98.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7168      0.39%     98.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5621      0.31%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4509      0.25%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16770      0.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1831783                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59616                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.746846                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      147.774131                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           59455     99.73%     99.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023          113      0.19%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535           11      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1831742                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.922688                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.125561                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     130.468112                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1453729     79.36%     79.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       261245     14.26%     93.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        48901      2.67%     96.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20697      1.13%     97.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13090      0.71%     98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7260      0.40%     98.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5482      0.30%     98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4525      0.25%     99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16813      0.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1831742                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59619                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.744729                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      150.866534                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59458     99.73%     99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          115      0.19%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1536-2047            8      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-3071            4      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            9      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            3      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-3583            3      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            3      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
@@ -225,103 +225,104 @@ system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # R
 system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10752-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59616                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59616                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.145079                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.109083                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.114634                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27440     46.03%     46.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1214      2.04%     48.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              26474     44.41%     92.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3953      6.63%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                450      0.75%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 71      0.12%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 11      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59616                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36544132750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               73150432750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9761680000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18718.16                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::15360-15871            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           59619                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59619                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.144098                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.107874                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.119193                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27514     46.15%     46.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1196      2.01%     48.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              26405     44.29%     92.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3955      6.63%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                448      0.75%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 78      0.13%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 15      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  6      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           59619                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    36502723500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73108498500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9761540000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18697.22                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37468.16                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  37447.22                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         103.37                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          54.12                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      103.43                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      103.44                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                       54.12                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.81                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.42                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     723493                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    419177                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.06                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.01                       # Row buffer hit rate for writes
-system.physmem.avgGap                       406217.15                       # Average gap between requests
+system.physmem.avgWrQLen                        24.64                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     723641                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    419030                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.07                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                       406193.88                       # Average gap between requests
 system.physmem.pageHitRate                      38.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6716750040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3664893375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7353886800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3243486240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            78952922880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           415155955455                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           361108109250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             876196004040                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              724.847786                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   597970225000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     40364480000                       # Time in different power states
+system.physmem_0.actEnergy                 6715147320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3664018875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7353699600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3243479760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            78947837280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           414818688735                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           361357239750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             876100111320                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              724.815145                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   598389652500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     40361880000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    570465308750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    569973346500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7131529440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3891211500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7874240400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3379857840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            78952922880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           426545221500                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           351117525000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             878892508560                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              727.078515                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   581276348750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     40364480000                       # Time in different power states
+system.physmem_1.actEnergy                 7132791960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3891900375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7873632000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3379818960                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            78947837280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           426678504030                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           350953893000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             878858377605                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              727.097114                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   581002634000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     40361880000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    587159309750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    587357637250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               246104681                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186361047                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15590665                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            167674402                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               165200232                       # Number of BTB hits
+system.cpu.branchPred.lookups               246098302                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186353272                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15586995                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            167674122                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               165197435                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.524420                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18413418                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104179                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.522916                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18413853                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104375                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    452862393                       # DTB read hits
-system.cpu.dtb.read_misses                    4979628                       # DTB read misses
+system.cpu.dtb.read_hits                    452860961                       # DTB read hits
+system.cpu.dtb.read_misses                    4979889                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                457842021                       # DTB read accesses
-system.cpu.dtb.write_hits                   161378642                       # DTB write hits
-system.cpu.dtb.write_misses                   1709394                       # DTB write misses
+system.cpu.dtb.read_accesses                457840850                       # DTB read accesses
+system.cpu.dtb.write_hits                   161378751                       # DTB write hits
+system.cpu.dtb.write_misses                   1709377                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               163088036                       # DTB write accesses
-system.cpu.dtb.data_hits                    614241035                       # DTB hits
-system.cpu.dtb.data_misses                    6689022                       # DTB misses
+system.cpu.dtb.write_accesses               163088128                       # DTB write accesses
+system.cpu.dtb.data_hits                    614239712                       # DTB hits
+system.cpu.dtb.data_misses                    6689266                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                620930057                       # DTB accesses
-system.cpu.itb.fetch_hits                   597998986                       # ITB hits
+system.cpu.dtb.data_accesses                620928978                       # DTB accesses
+system.cpu.itb.fetch_hits                   597989879                       # ITB hits
 system.cpu.itb.fetch_misses                        19                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               597999005                       # ITB accesses
+system.cpu.itb.fetch_accesses               597989898                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -335,82 +336,82 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2417601595                       # number of cpu cycles simulated
+system.cpu.numCycles                       2417457399                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1826378509                       # Number of instructions committed
 system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      51825441                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      51810559                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.323713                       # CPI: cycles per instruction
-system.cpu.ipc                               0.755451                       # IPC: instructions per cycle
-system.cpu.tickCycles                      2075284528                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       342317067                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9121986                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4080.726688                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           601540360                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9126082                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.914415                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.323634                       # CPI: cycles per instruction
+system.cpu.ipc                               0.755496                       # IPC: instructions per cycle
+system.cpu.tickCycles                      2075240271                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       342217128                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9121937                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.725777                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           601539424                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126033                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.914667                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle       16821281500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4080.726688                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4080.725777                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.996271                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.996271                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1562                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2407                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1547                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2403                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1231278878                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1231278878                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    443058336                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       443058336                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    158482024                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158482024                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     601540360                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        601540360                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    601540360                       # number of overall hits
-system.cpu.dcache.overall_hits::total       601540360                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7289560                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7289560                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2246478                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2246478                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      9536038                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9536038                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9536038                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9536038                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 185462944500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 185462944500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 108451503000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 108451503000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 293914447500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 293914447500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 293914447500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 293914447500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    450347896                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    450347896                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1231276891                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1231276891                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    443057425                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       443057425                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    158481999                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158481999                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     601539424                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        601539424                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    601539424                       # number of overall hits
+system.cpu.dcache.overall_hits::total       601539424                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7289502                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7289502                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2246503                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2246503                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9536005                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9536005                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9536005                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9536005                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 185435901500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 185435901500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 108411798000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 108411798000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 293847699500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 293847699500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 293847699500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 293847699500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    450346927                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    450346927                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    611076398                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    611076398                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    611076398                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    611076398                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016187                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.016187                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    611075429                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    611075429                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    611075429                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    611075429                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016186                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.016186                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013977                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.013977                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.015605                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.015605                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015605                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015605                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25442.268738                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25442.268738                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48276.236402                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48276.236402                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30821.442563                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30821.442563                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30821.442563                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30821.442563                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25438.761317                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25438.761317                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48258.025028                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48258.025028                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30814.549646                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30814.549646                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30814.549646                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30814.549646                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -419,32 +420,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3686591                       # number of writebacks
-system.cpu.dcache.writebacks::total           3686591                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50801                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        50801                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359155                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       359155                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       409956                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       409956                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       409956                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       409956                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238759                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238759                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887323                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887323                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9126082                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126082                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9126082                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126082                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176998396500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 176998396500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83275965000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  83275965000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260274361500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 260274361500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260274361500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 260274361500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      3686592                       # number of writebacks
+system.cpu.dcache.writebacks::total           3686592                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50797                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        50797                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359175                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       359175                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       409972                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       409972                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       409972                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       409972                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238705                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7238705                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887328                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1887328                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9126033                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9126033                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9126033                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9126033                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176973816500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 176973816500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83260117500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  83260117500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260233934000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 260233934000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260233934000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 260233934000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016074                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016074                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011742                       # mshr miss rate for WriteReq accesses
@@ -453,66 +454,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014934
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014934                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014934                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014934                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24451.483535                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24451.483535                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44123.854263                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44123.854263                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.835949                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.835949                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.835949                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.835949                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.270305                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.270305                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44115.340577                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44115.340577                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28515.559170                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28515.559170                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28515.559170                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28515.559170                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           749.172343                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           597998029                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           749.290154                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           597988922                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               957                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          624867.323929                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          624857.807732                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   749.172343                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.365807                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.365807                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   749.290154                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.365864                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.365864                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          873                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1195998929                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1195998929                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    597998029                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       597998029                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     597998029                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        597998029                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    597998029                       # number of overall hits
-system.cpu.icache.overall_hits::total       597998029                       # number of overall hits
+system.cpu.icache.tags.tag_accesses        1195980715                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1195980715                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    597988922                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       597988922                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     597988922                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        597988922                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    597988922                       # number of overall hits
+system.cpu.icache.overall_hits::total       597988922                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          957                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           957                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            957                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          957                       # number of overall misses
 system.cpu.icache.overall_misses::total           957                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     77181000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     77181000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     77181000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     77181000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     77181000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     77181000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    597998986                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    597998986                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    597998986                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    597998986                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    597998986                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    597998986                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     76621000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     76621000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     76621000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     76621000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     76621000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     76621000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    597989879                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    597989879                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    597989879                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    597989879                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    597989879                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    597989879                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80648.902821                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 80648.902821                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 80648.902821                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 80648.902821                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 80648.902821                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 80648.902821                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80063.740857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 80063.740857                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 80063.740857                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 80063.740857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 80063.740857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 80063.740857                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -521,125 +522,131 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks            3                       # number of writebacks
+system.cpu.icache.writebacks::total                 3                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          957                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          957                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          957                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          957                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76224000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     76224000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76224000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     76224000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76224000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     76224000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75664000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     75664000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75664000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     75664000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75664000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     75664000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79648.902821                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79648.902821                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79648.902821                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 79648.902821                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79648.902821                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 79648.902821                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79063.740857                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 79063.740857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 79063.740857                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1920882                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30765.249465                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14409739                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1950686                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.387011                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1920885                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30765.167230                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14409636                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1950689                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.386947                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      89219766000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14798.314674                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.741446                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.193345                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.451609                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001304                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.485968                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.938881                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 14798.522218                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.781155                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15923.863857                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.451615                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29804                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1217                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12865                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15534                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1218                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12864                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15532                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909546                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149830233                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149830233                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      3686591                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3686591                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1106811                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1106811                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6066619                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6066619                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7173430                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7173430                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7173430                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7173430                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       780512                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       780512                       # number of ReadExReq misses
+system.cpu.l2cache.tags.tag_accesses        149829457                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149829457                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3686592                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3686592                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1106819                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1106819                       # number of ReadExReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6066562                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6066562                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7173381                       # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::total        7173381                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       780509                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       780509                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          957                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total          957                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1172140                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1172140                       # number of ReadSharedReq misses
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 system.cpu.l2cache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.inst          957                       # number of overall misses
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 system.cpu.l2cache.overall_misses::total      1953609                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68753946000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  68753946000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     74786500                       # number of ReadCleanReq miss cycles
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-system.cpu.l2cache.ReadSharedReq_miss_latency::total 102412790500                       # number of ReadSharedReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data 171166736500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 171241523000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     74786500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 171166736500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 171241523000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      3686591                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3686591                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887323                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1887323                       # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadSharedReq_miss_latency::total 102389221500                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.data 171125481000                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::total 171199708500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3686592                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3686592                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
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 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          957                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total          957                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238759                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7238759                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238705                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7238705                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          957                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9126082                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9127039                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9126033                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9126990                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          957                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9126082                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9127039                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413555                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413555                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9126033                       # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413552                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.413552                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161926                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161926                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161927                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161927                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.213964                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214046                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.213965                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.213964                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214046                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88088.262576                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88088.262576                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78146.812957                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78146.812957                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87372.490061                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87372.490061                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78146.812957                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87658.597897                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87653.938429                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78146.812957                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87658.597897                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87653.938429                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.213965                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214047                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88065.940944                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88065.940944                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77562.695925                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77562.695925                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87352.158824                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87352.158824                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77562.695925                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87637.469964                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87632.534709                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77562.695925                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87637.469964                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87632.534709                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -648,122 +655,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1022141                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1022141                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          245                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          245                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780512                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       780512                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1022134                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1022134                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          242                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          242                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780509                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       780509                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          957                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total          957                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172140                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172140                       # number of ReadSharedReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data      1952652                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total      1953609                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data      1952652                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total      1953609                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60948826000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60948826000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65216500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65216500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90691390500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90691390500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65216500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151640216500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 151705433000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65216500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151640216500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 151705433000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60931169500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60931169500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64657500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64657500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90667791500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90667791500                       # number of ReadSharedReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151598961000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 151663618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64657500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151598961000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 151663618500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413555                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413555                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413552                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413552                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161926                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161926                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161927                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161927                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.213964                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214046                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.213965                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214047                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213964                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214046                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78088.262576                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78088.262576                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68146.812957                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68146.812957                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77372.490061                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77372.490061                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68146.812957                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77658.597897                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.938429                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213965                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214047                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78065.940944                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78065.940944                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67562.695925                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77352.158824                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77352.158824                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77637.469964                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77632.534709                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77637.469964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77632.534709                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18249028                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121989                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18248930                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121940                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1267                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1267                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1268                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1268                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7239716                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4708732                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6334139                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887323                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887323                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7239662                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4708726                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6334096                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887328                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887328                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          957                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238759                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238705                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1917                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374150                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27376067                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820011072                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          820072320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1920882                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20169910                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000063                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.007925                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374003                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27375920                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820008000                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          820069440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1920885                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11047875                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000115                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.010713                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           20168643     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1267      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11046607     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1268      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20169910                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12811105000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11047875                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12811060000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1435500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13689123000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13689049500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1173097                       # Transaction distribution
-system.membus.trans_dist::Writeback           1022141                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           897719                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            780512                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           780512                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1173097                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827078                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5827078                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190448000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190448000                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1173100                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1022134                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           897725                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            780509                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           780509                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1173100                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827077                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5827077                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190447552                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190447552                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3873469                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3873468                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3873469    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3873468    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3873469                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8428000500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3873468                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8428126500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10685481750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10685578000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index bb4922b1c..5a6b26759 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.669557                       # Number of seconds simulated
-sim_ticks                                669556582000                       # Number of ticks simulated
-final_tick                               669556582000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.669525                       # Number of seconds simulated
+sim_ticks                                669525393000                       # Number of ticks simulated
+final_tick                               669525393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 160543                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160543                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61918292                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299292                       # Number of bytes of host memory used
-host_seconds                                 10813.55                       # Real time elapsed on the host
+host_inst_rate                                 166227                       # Simulator instruction rate (inst/s)
+host_op_rate                                   166227                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               64107392                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 299384                       # Number of bytes of host memory used
+host_seconds                                 10443.81                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             60864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125490304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125551168                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        60864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           60864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65555584                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65555584                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                951                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1960786                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1961737                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1024306                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1024306                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                90902                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            187423001                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               187513903                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           90902                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              90902                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          97908953                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               97908953                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          97908953                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               90902                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           187423001                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              285422856                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1961737                       # Number of read requests accepted
-system.physmem.writeReqs                      1024306                       # Number of write requests accepted
-system.physmem.readBursts                     1961737                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1024306                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125467392                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83776                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65553984                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125551168                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65555584                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1309                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             60992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125490432                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125551424                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        60992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           60992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65555904                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65555904                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                953                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1960788                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1961741                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1024311                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1024311                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                91097                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            187431923                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               187523021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           91097                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              91097                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          97913992                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               97913992                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          97913992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               91097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           187431923                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              285437013                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1961741                       # Number of read requests accepted
+system.physmem.writeReqs                      1024311                       # Number of write requests accepted
+system.physmem.readBursts                     1961741                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1024311                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125468352                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83072                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65554688                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125551424                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65555904                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1298                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118679                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              113901                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116111                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117641                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117753                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117515                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119854                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124644                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127345                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130108                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128796                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130507                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126297                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125432                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122623                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123222                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61508                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61766                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         903686                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              118677                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113900                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116118                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117645                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117762                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117513                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119856                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124646                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127338                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130111                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128791                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130502                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126296                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125424                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122633                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123231                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61509                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61765                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               60825                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61511                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61967                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63434                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61513                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61969                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63433                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               64481                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65996                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65997                       # Per bank write bursts
 system.physmem.perBankWrBursts::8               65770                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66159                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66158                       # Per bank write bursts
 system.physmem.perBankWrBursts::10              65809                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              66083                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64701                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64659                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              65023                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64589                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              66082                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64703                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64664                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65021                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64593                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    669556486500                       # Total gap between requests
+system.physmem.totGap                    669525297500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1961737                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1961741                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1024306                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1618471                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    241016                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     69944                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     30981                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1024311                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1618506                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    241044                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     69880                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     30998                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26250                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    27792                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49335                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    56790                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    26356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    27917                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49392                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56811                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59370                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60627                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60983                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61281                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                    61428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62350                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    63649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    65159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60239                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61603                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    63632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    65011                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62797                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61721                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    60222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,149 +193,148 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1769592                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      107.945804                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      82.951779                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     137.536097                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1374979     77.70%     77.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       270914     15.31%     93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53662      3.03%     96.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21295      1.20%     97.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12785      0.72%     97.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6489      0.37%     98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4949      0.28%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3948      0.22%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20571      1.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1769592                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60107                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.574625                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      148.683386                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           59945     99.73%     99.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023          118      0.20%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            6      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-3071            5      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583            3      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            1      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-4607            1      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1769975                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      107.923423                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.935475                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     137.553027                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1375598     77.72%     77.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       270762     15.30%     93.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        53515      3.02%     96.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21283      1.20%     97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12968      0.73%     97.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6460      0.36%     98.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4828      0.27%     98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3885      0.22%     98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20676      1.17%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1769975                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60095                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.621932                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      151.728866                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59931     99.73%     99.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          120      0.20%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535           12      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            4      0.01%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            5      0.01%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            5      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            4      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-8703            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-9727            2      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60107                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60107                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.040960                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.998792                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.235687                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              31915     53.10%     53.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1364      2.27%     55.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              21027     34.98%     90.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               4732      7.87%     98.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                816      1.36%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                161      0.27%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 44      0.07%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 14      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  8      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  3      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  3      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-15871            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           60095                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60095                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.044546                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.002519                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.231700                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              31758     52.85%     52.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1379      2.29%     55.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              21272     35.40%     90.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4591      7.64%     98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                816      1.36%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                185      0.31%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 43      0.07%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 20      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  5      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::32                  3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33                  1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  2      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::34                  2      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::35                  1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  2      0.00%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::37                  1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::39                  1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  3      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::40                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::41                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60107                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    40555708000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               77313733000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9802140000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20687.17                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::41                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60095                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    40550197000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77308503250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9802215000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20684.20                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39437.17                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         187.39                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39434.20                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         187.40                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          97.91                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      187.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      187.52                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                       97.91                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.98                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     792895                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    422217                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.94                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     792754                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    422001                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   40.44                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.22                       # Row buffer hit rate for writes
-system.physmem.avgGap                       224228.68                       # Average gap between requests
-system.physmem.pageHitRate                      40.71                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6483387960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3537562875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7379541000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3249642240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            43732091520                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           304280359155                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           134820686250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             503483271000                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              751.966482                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   222309059500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     22357920000                       # Time in different power states
+system.physmem.writeRowHitRate                  41.20                       # Row buffer hit rate for writes
+system.physmem.avgGap                       224217.56                       # Average gap between requests
+system.physmem.pageHitRate                      40.70                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6484552200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3538198125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7379689200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3249668160                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            43730057280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           304192019700                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           134879490000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             503453674665                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              751.957257                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   222404009750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     22356880000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    424888778500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    424763715750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 6894704880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3761991750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7911610200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3387698640                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            43732091520                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           311328000180                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           128638545000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             505654642170                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              755.209486                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   211980924500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     22357920000                       # Time in different power states
+system.physmem_1.actEnergy                 6896443680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3762940500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7911594600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3387744000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            43730057280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           311181502770                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           128748364500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             505618647330                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              755.190855                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   212167441250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     22356880000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    435216639250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    435000017500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               409355418                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         318166975                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15963047                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            282312141                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               278580615                       # Number of BTB hits
+system.cpu.branchPred.lookups               409350195                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         318164532                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15963584                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            282308187                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               278578841                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.678227                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                26172204                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 20                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.678981                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                26172152                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 19                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    644928587                       # DTB read hits
-system.cpu.dtb.read_misses                   12158902                       # DTB read misses
+system.cpu.dtb.read_hits                    644938332                       # DTB read hits
+system.cpu.dtb.read_misses                   12159455                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                657087489                       # DTB read accesses
-system.cpu.dtb.write_hits                   218092717                       # DTB write hits
-system.cpu.dtb.write_misses                   7512154                       # DTB write misses
+system.cpu.dtb.read_accesses                657097787                       # DTB read accesses
+system.cpu.dtb.write_hits                   218091822                       # DTB write hits
+system.cpu.dtb.write_misses                   7511788                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               225604871                       # DTB write accesses
-system.cpu.dtb.data_hits                    863021304                       # DTB hits
-system.cpu.dtb.data_misses                   19671056                       # DTB misses
+system.cpu.dtb.write_accesses               225603610                       # DTB write accesses
+system.cpu.dtb.data_hits                    863030154                       # DTB hits
+system.cpu.dtb.data_misses                   19671243                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                882692360                       # DTB accesses
-system.cpu.itb.fetch_hits                   420625120                       # ITB hits
+system.cpu.dtb.data_accesses                882701397                       # DTB accesses
+system.cpu.itb.fetch_hits                   420624983                       # ITB hits
 system.cpu.itb.fetch_misses                        37                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               420625157                       # ITB accesses
+system.cpu.itb.fetch_accesses               420625020                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -349,98 +348,98 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1339113165                       # number of cpu cycles simulated
+system.cpu.numCycles                       1339050787                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          431760554                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3410003764                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   409355418                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          304752819                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     884588278                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                45380492                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles          431760433                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3409990757                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   409350195                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          304750993                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     884524854                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                45382362                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          1660                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           27                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 420625120                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8288982                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1339040790                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.546602                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.150665                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles           14                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 420624983                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8290664                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1338978167                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.546711                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.150697                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                714026661     53.32%     53.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 47659433      3.56%     56.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 24224234      1.81%     58.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 45105968      3.37%     62.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                142792146     10.66%     72.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 65943853      4.92%     77.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 43594254      3.26%     80.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 29429342      2.20%     83.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                226264899     16.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                713970324     53.32%     53.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 47658259      3.56%     56.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 24222568      1.81%     58.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 45103345      3.37%     62.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                142790906     10.66%     72.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 65943786      4.92%     77.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 43594409      3.26%     80.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 29428241      2.20%     83.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                226266329     16.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1339040790                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.305691                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.546464                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                353769612                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             403558275                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 524215531                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              34807834                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               22689538                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             62027781                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   752                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3256129377                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2069                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               22689538                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                372008249                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               212535269                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7646                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 537155328                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             194644760                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3173788478                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents               1809495                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               20462310                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents              148566154                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30882701                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2371842618                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4117718959                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       4117582524                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            136434                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1338978167                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.305702                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.546573                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                353776569                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             403484138                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 524228681                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              34798314                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               22690465                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             62024721                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   760                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3256106209                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2093                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               22690465                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                372012141                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               212467548                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7342                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 537162613                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             194638058                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3173768927                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents               1816422                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               20455726                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              148599653                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30860374                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2371827952                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4117690277                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4117553850                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            136426                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                995639655                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                143                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            142                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  99637264                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            717251547                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           272457871                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          90453848                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         58428187                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2884203449                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 122                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2620051581                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1544935                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1148159789                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    502731368                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             93                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1339040790                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.956663                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.148213                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                995624989                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                146                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            145                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  99592668                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            717246268                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           272455740                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          90411000                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         58626283                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2884178650                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 125                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2620049271                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1544769                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1148134993                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    502709027                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             96                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1338978167                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.956753                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.148253                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           535540081     39.99%     39.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           169652118     12.67%     52.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           157969981     11.80%     64.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           149186997     11.14%     75.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           125999252      9.41%     85.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            84166081      6.29%     91.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            68019052      5.08%     96.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            34101039      2.55%     98.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8            14406189      1.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           535496202     39.99%     39.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           169647302     12.67%     52.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           157966093     11.80%     64.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149142376     11.14%     75.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           126023638      9.41%     85.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            84181895      6.29%     91.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            68010869      5.08%     96.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            34104922      2.55%     98.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            14404870      1.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1339040790                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1338978167                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                13157777     35.84%     35.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                13158801     35.84%     35.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     35.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.84% # attempts to use FU when none available
@@ -469,17 +468,17 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.84% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               18965028     51.65%     87.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4592425     12.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               18966749     51.66%     87.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4591786     12.51%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1716938805     65.53%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1716928227     65.53%     65.53% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                  113      0.00%     65.53% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              896154      0.03%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              896664      0.03%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                  19      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 163      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 165      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                 30      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.56% # Type of FU issued
@@ -503,84 +502,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.56% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            671533572     25.63%     91.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           230682699      8.80%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            671542182     25.63%     91.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           230681845      8.80%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2620051581                       # Type of FU issued
-system.cpu.iq.rate                           1.956557                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    36715230                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014013                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6615464746                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        4031257680                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2518620612                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1939371                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1248863                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       886699                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2655799836                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  966975                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         69396280                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2620049271                       # Type of FU issued
+system.cpu.iq.rate                           1.956647                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36717336                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014014                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6615397697                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4031207578                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2518612422                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1941117                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1249905                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       887144                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2655798760                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  967847                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         69398293                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    272655884                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       373351                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       145486                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    111729369                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    272650605                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       374228                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       146038                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    111727238                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          229                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       6306976                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          239                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       6310160                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               22689538                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               149806110                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              21267531                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3035207367                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           6595956                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             717251547                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            272457871                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                122                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 801675                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              20722786                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         145486                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10633585                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8701131                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19334716                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2574896999                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             657087498                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          45154582                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               22690465                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               149836338                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              21229362                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3035183152                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6595413                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             717246268                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            272455740                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                125                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 801803                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              20684202                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         146038                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10633994                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8701055                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19335049                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2574897906                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             657097795                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          45151365                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     151003796                       # number of nop insts executed
-system.cpu.iew.exec_refs                    882692437                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                315488895                       # Number of branches executed
-system.cpu.iew.exec_stores                  225604939                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.922837                       # Inst execution rate
-system.cpu.iew.wb_sent                     2549331117                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2519507311                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1487495376                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1918378348                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     151004377                       # number of nop insts executed
+system.cpu.iew.exec_refs                    882701473                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                315482828                       # Number of branches executed
+system.cpu.iew.exec_stores                  225603678                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.922928                       # Inst execution rate
+system.cpu.iew.wb_sent                     2549323154                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2519499566                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1487497634                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1918379503                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.881475                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.775392                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.881556                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.775393                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       998666714                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       998640819                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15962339                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1201055691                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.515150                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.548433                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15962868                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1200994355                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.515228                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.548533                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    712334289     59.31%     59.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    159635442     13.29%     72.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     79514551      6.62%     79.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     52029279      4.33%     83.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28475742      2.37%     85.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     19476450      1.62%     87.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19964545      1.66%     89.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     23047887      1.92%     91.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    106577506      8.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    712309125     59.31%     59.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    159609736     13.29%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     79494019      6.62%     79.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     52028691      4.33%     83.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28473987      2.37%     85.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     19488340      1.62%     87.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19957354      1.66%     89.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     23050317      1.92%     91.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106582786      8.87%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1201055691                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1200994355                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -626,138 +625,138 @@ system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
-system.cpu.commit.bw_lim_events             106577506                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3827145825                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5775013033                       # The number of ROB writes
-system.cpu.timesIdled                             710                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           72375                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events             106582786                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3827053314                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5774960362                       # The number of ROB writes
+system.cpu.timesIdled                             711                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           72620                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.771359                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.771359                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.296413                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.296413                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3463596666                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2019349968                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     39643                       # number of floating regfile reads
+system.cpu.cpi                               0.771323                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.771323                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.296473                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.296473                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3463595596                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2019348323                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     39740                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                      588                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9207223                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.441459                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           712346742                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9211319                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             77.333848                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           9207181                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.441061                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           712353360                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9211277                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             77.334919                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        5127954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.441459                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997911                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997911                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.441061                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997910                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997910                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          707                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2960                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          698                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2969                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1470153653                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1470153653                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    556848599                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       556848599                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155498140                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155498140                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1470163219                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1470163219                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    556855010                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       556855010                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155498347                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155498347                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     712346739                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        712346739                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    712346739                       # number of overall hits
-system.cpu.dcache.overall_hits::total       712346739                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12894062                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12894062                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5230362                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5230362                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     712353357                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        712353357                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    712353357                       # number of overall hits
+system.cpu.dcache.overall_hits::total       712353357                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12892455                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12892455                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5230155                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5230155                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     18124424                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       18124424                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     18124424                       # number of overall misses
-system.cpu.dcache.overall_misses::total      18124424                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 412011773000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 412011773000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 315105865697                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 315105865697                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     18122610                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       18122610                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     18122610                       # number of overall misses
+system.cpu.dcache.overall_misses::total      18122610                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 411787652500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 411787652500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 315044398573                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 315044398573                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        72500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        72500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 727117638697                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 727117638697                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 727117638697                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 727117638697                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    569742661                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    569742661                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 726832051073                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 726832051073                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 726832051073                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 726832051073                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    569747465                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    569747465                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    730471163                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    730471163                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    730471163                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    730471163                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022631                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.022631                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032542                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032542                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    730475967                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    730475967                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    730475967                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    730475967                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022628                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022628                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032540                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032540                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024812                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024812                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.024812                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.024812                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31953.605698                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31953.605698                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60245.517556                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60245.517556                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024809                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024809                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.024809                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.024809                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31940.204755                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 31940.204755                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60236.149516                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60236.149516                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40118.110164                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40118.110164                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40118.110164                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40118.110164                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     15661523                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      9569226                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1103711                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           68026                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.189877                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   140.670126                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40106.367188                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40106.367188                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40106.367188                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40106.367188                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     15689743                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      9578184                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1104687                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           68028                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.202886                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   140.797672                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3727748                       # number of writebacks
-system.cpu.dcache.writebacks::total           3727748                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5561934                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5561934                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3351172                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3351172                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      8913106                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      8913106                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      8913106                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      8913106                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332128                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7332128                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879190                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1879190                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3727717                       # number of writebacks
+system.cpu.dcache.writebacks::total           3727717                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5560371                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5560371                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3350963                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3350963                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      8911334                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      8911334                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      8911334                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      8911334                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332084                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7332084                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879192                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1879192                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9211318                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9211318                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9211318                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9211318                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182959853500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 182959853500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84331903655                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84331903655                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9211276                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9211276                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9211276                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9211276                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182956640000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 182956640000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84332021587                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84332021587                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        71500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        71500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267291757155                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 267291757155                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267291757155                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 267291757155                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267288661587                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 267288661587                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267288661587                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 267288661587                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012869                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012869                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011692                       # mshr miss rate for WriteReq accesses
@@ -768,201 +767,208 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012610
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012610                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012610                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24953.172326                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24953.172326                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.730748                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.730748                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24952.883791                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24952.883791                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.745743                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.745743                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        71500                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        71500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.753719                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.753719                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.753719                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.753719                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.549967                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.549967                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.549967                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.549967                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           755.106219                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           420623640                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               951                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          442296.151420                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           755.122971                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           420623501                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               953                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          441367.786988                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   755.106219                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.368704                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.368704                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          950                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   755.122971                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.368712                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.368712                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          952                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          886                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.463867                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         841251191                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        841251191                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    420623640                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       420623640                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     420623640                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        420623640                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    420623640                       # number of overall hits
-system.cpu.icache.overall_hits::total       420623640                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1480                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1480                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1480                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1480                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1480                       # number of overall misses
-system.cpu.icache.overall_misses::total          1480                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    114807500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    114807500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    114807500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    114807500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    114807500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    114807500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    420625120                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    420625120                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    420625120                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    420625120                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total    420625120                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_task_id_percent::1024     0.464844                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         841250919                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        841250919                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    420623501                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst         1482                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1482                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst         1482                       # number of overall misses
+system.cpu.icache.overall_misses::total          1482                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    113433000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    113433000                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total    113433000                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total    113433000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    420624983                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    420624983                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total    420624983                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77572.635135                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77572.635135                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77572.635135                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77572.635135                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77572.635135                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77572.635135                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          288                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76540.485830                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76540.485830                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76540.485830                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76540.485830                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76540.485830                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76540.485830                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          290                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    57.600000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
+system.cpu.icache.writebacks::total                 1                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          529                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total          529                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst          529                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_hits::total          529                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst          529                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total          529                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          951                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          951                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          951                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          951                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          951                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          951                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     79672000                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83777.076761                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83777.076761                       # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 83777.076761                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83777.076761                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total 83072.402938                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1929031                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31408.547403                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14580190                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1958818                       # Sample count of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle      28140218000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14352.760847                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.833600                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 17029.952956                       # Average occupied blocks per requestor
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 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29787                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          975                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          615                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909027                       # Percentage of cache occupancy per task id
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 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411033                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.411033                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
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 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
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 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89676.114069                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81567.156348                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89618.015334                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81567.156348                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89673.715363                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89669.777254                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -971,122 +977,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1024306                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1024306                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          241                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          241                       # number of CleanEvict MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total       772416                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          951                       # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188370                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          951                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1960786                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1961737                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          951                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1960786                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1961737                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61608280500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61608280500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68730000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68730000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94619528500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94619528500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68730000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156227809000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 156296539000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68730000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156227809000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 156296539000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks      1024311                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1024311                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          240                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          240                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772417                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       772417                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          953                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          953                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1188371                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188371                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          953                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1960788                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1961741                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          953                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1960788                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1961741                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61607524500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61607524500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68203500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68203500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94615740500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94615740500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68203500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156223265000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 156291468500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68203500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156223265000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 156291468500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411033                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411033                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162077                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162077                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162079                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162079                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212867                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.212948                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212868                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.212950                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212867                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.212948                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79760.492403                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79760.492403                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72271.293375                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79621.269891                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79621.269891                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79676.114069                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79672.524401                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212868                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.212950                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79759.410396                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79759.410396                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71567.156348                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79618.015334                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79618.015334                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79673.715363                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.777254                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79673.715363                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.777254                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18419494                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207224                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18419412                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207182                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1279                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1279                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1280                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1280                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7333064                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4752054                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6384201                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1879206                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1879206                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          951                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332113                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1903                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629861                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27631764                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        60864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828100288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          828161152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1929031                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20348525                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000063                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.007928                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       7333022                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4752028                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6384190                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1879208                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1879208                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          953                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332069                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1907                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629735                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27631642                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828095616                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          828156672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1929037                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11141267                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000115                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.010718                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           20347246     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1279      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11139987     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1280      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20348525                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12937495000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11141267                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12937424000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1426500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1429500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13816978500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13816915500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1189321                       # Transaction distribution
-system.membus.trans_dist::Writeback           1024306                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           903687                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            772416                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           772416                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1189321                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851467                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5851467                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191106752                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               191106752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1189324                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1024311                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           903686                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            772417                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           772417                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1189324                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851479                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5851479                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191107328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               191107328                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3889730                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3889738                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3889730    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3889738    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3889730                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8475633500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3889738                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8475624000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10684578250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10684646000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index d971ffdfc..2fb4a6971 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.623057                       # Number of seconds simulated
-sim_ticks                                2623057163500                       # Number of ticks simulated
-final_tick                               2623057163500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.636720                       # Number of seconds simulated
+sim_ticks                                2636719559500                       # Number of ticks simulated
+final_tick                               2636719559500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1405944                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1405944                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2026548224                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 297224                       # Number of bytes of host memory used
-host_seconds                                  1294.35                       # Real time elapsed on the host
+host_inst_rate                                1488641                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1488641                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2156924734                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297352                       # Number of bytes of host memory used
+host_seconds                                  1222.44                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data            1951440                       # Nu
 system.physmem.num_reads::total               1952242                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1021962                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1021962                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                19568                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             47613206                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                47632774                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           19568                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              19568                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          24934862                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               24934862                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          24934862                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               19568                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            47613206                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               72567635                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                19467                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             47366494                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                47385960                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           19467                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              19467                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          24805660                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               24805660                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          24805660                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               19467                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            47366494                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               72191620                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -70,7 +70,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       5246114327                       # number of cpu cycles simulated
+system.cpu.numCycles                       5273439119                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1819780127                       # Number of instructions committed
@@ -89,7 +89,7 @@ system.cpu.num_mem_refs                     611922547                       # nu
 system.cpu.num_load_insts                   449492741                       # Number of load instructions
 system.cpu.num_store_insts                  162429806                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5246114327                       # Number of busy cycles
+system.cpu.num_busy_cycles                 5273439119                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.Branches                         214632552                       # Number of branches fetched
@@ -129,19 +129,19 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1826378509                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           9107638                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4079.260769                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4079.293901                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           596212431                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9111734                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             65.433476                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       40977438500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4079.260769                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995913                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995913                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle       41036287500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4079.293901                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.995921                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.995921                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1237                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2584                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          200                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1197                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2638                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          206                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses        1219760064                       # Number of tag accesses
@@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data      9111734                       # n
 system.cpu.dcache.demand_misses::total        9111734                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9111734                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9111734                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143001525000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143001525000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57421337000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57421337000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200422862000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200422862000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200422862000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200422862000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 151181633000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  62898029000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  62898029000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 214079662000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 214079662000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 214079662000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 214079662000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
@@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.015053
 system.cpu.dcache.demand_miss_rate::total     0.015053                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015053                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015053                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19799.685396                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19799.685396                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30392.594690                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30392.594690                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21996.127411                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21996.127411                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21996.127411                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21996.127411                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23494.942017                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23494.942017                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9111734
 system.cpu.dcache.demand_mshr_misses::total      9111734                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9111734                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9111734                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135779111000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 135779111000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  55532017000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  55532017000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191311128000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 191311128000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191311128000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 191311128000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  61008709000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  61008709000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 204967928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 204967928000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011755                       # mshr miss rate for WriteReq accesses
@@ -228,26 +228,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015053
 system.cpu.dcache.demand_mshr_miss_rate::total     0.015053                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015053                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.015053                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18799.685396                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18799.685396                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29392.594690                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29392.594690                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20996.127411                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20996.127411                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20996.127411                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20996.127411                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           612.447387                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           612.605858                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1826377708                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               802                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          2277278.937656                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   612.447387                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.299047                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.299047                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   612.605858                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.299124                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.299124                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          801                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          730                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.391113                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses        3652757822                       # Number of tag accesses
@@ -264,12 +265,12 @@ system.cpu.icache.demand_misses::cpu.inst          802                       # n
 system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
 system.cpu.icache.overall_misses::total           802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     44163500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     44163500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     44163500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     44163500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     44163500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     44163500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     49759500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     49759500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     49759500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     49759500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     49759500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     49759500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1826378510                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1826378510                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1826378510                       # number of demand (read+write) accesses
@@ -282,12 +283,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.708229                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55066.708229                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.708229                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55066.708229                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.708229                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55066.708229                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 62044.264339                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62044.264339                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -296,55 +297,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
+system.cpu.icache.writebacks::total                 1                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          802                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     43361500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     43361500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     43361500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     43361500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     43361500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     43361500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     48957500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     48957500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     48957500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     48957500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     48957500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     48957500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54066.708229                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54066.708229                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54066.708229                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54066.708229                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54066.708229                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54066.708229                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1919524                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30534.757407                       # Cycle average of tags in use
+system.cpu.l2cache.tags.replacements          1919525                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30540.825713                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           14380256                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1949316                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.377078                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     218167130000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15101.273798                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    38.972607                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15394.511002                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.460854                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001189                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.469803                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.931847                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.sampled_refs          1949317                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.377074                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     218471945000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    38.824340                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.460561                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001185                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.470286                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.932032                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29792                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1062                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1254                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27300                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1058                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1255                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27302                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909180                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149600036                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149600036                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      3679426                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3679426                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses        149600037                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149600037                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3679426                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3679426                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total            1                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data      1106935                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total      1106935                       # number of ReadExReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6053359                       # number of ReadSharedReq hits
@@ -365,20 +370,22 @@ system.cpu.l2cache.demand_misses::total       1952242                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          802                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data      1951440                       # number of overall misses
 system.cpu.l2cache.overall_misses::total      1952242                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41075219500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  41075219500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     42150500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     42150500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  61385220500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  61385220500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     42150500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 102460440000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 102502590500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     42150500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 102460440000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 102502590500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      3679426                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3679426                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  46551911500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  46551911500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     47746500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     47746500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  69565328500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  69565328500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     47746500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 116117240000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 116164986500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     47746500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 116117240000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 116164986500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3679426                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3679426                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889320                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      1889320                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          802                       # number of ReadCleanReq accesses(hits+misses)
@@ -403,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.214237                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.214168                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.214237                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.008947                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.008947                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52556.733167                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52556.733167                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52508.411067                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52508.411067                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52556.733167                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52505.042430                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52505.063665                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52556.733167                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52505.042430                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52505.063665                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.005113                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.005113                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59534.289277                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59534.289277                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.607948                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.607948                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59534.289277                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59503.361620                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59503.374326                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59534.289277                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59503.361620                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59503.374326                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -425,8 +432,8 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1021962                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1021962                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          243                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          243                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          242                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          242                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782385                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       782385                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          802                       # number of ReadCleanReq MSHR misses
@@ -439,18 +446,18 @@ system.cpu.l2cache.demand_mshr_misses::total      1952242
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data      1951440                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total      1952242                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  33251369500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  33251369500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     34130500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     34130500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  49694670500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  49694670500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34130500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  82946040000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  82980170500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34130500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  82946040000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  82980170500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  38728061500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  38728061500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     39726500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     39726500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  57874778500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  57874778500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     39726500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  96602840000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  96642566500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     39726500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  96602840000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  96642566500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.414109                       # mshr miss rate for ReadExReq accesses
@@ -465,18 +472,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.214237
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214168                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.214237                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.008947                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.008947                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42556.733167                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42556.733167                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42508.411067                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42508.411067                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42556.733167                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42505.042430                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.063665                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18220175                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9107639                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -485,7 +492,8 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops         1122                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1122                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp       7223216                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4701388                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4701388                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict      6325775                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1889320                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1889320                       # Transaction distribution
@@ -494,29 +502,29 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq      7222414
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1605                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27331106                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total          27332711                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51392                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818634240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          818685568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1919524                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20139699                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000056                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.007464                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size::total          818685632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1919525                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11032061                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000102                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.010084                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           20138577     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11030939     99.99%     99.99% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1               1122      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20139699                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12789513500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11032061                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12789514500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1203000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13667601000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp            1169857                       # Transaction distribution
-system.membus.trans_dist::Writeback           1021962                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1021962                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           896683                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            782385                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           782385                       # Transaction distribution
@@ -526,19 +534,19 @@ system.membus.pkt_count::total                5823129                       # Pa
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190349056                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size::total               190349056                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3872712                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3870887                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3872712    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3870887    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3872712                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7960873524                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3870887                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          7958742500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         9761522024                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         9761210000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index 766f60b6c..144dc4013 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.116866                       # Number of seconds simulated
-sim_ticks                                1116865669500                       # Number of ticks simulated
-final_tick                               1116865669500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.116861                       # Number of seconds simulated
+sim_ticks                                1116860578500                       # Number of ticks simulated
+final_tick                               1116860578500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 226280                       # Simulator instruction rate (inst/s)
-host_op_rate                                   243783                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              163622006                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317884                       # Number of bytes of host memory used
-host_seconds                                  6825.89                       # Real time elapsed on the host
+host_inst_rate                                 237615                       # Simulator instruction rate (inst/s)
+host_op_rate                                   255994                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              171817202                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317996                       # Number of bytes of host memory used
+host_seconds                                  6500.28                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             50368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         130931456                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            130981824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        50368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst             50176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         130931712                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            130981888                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50176                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks     67207872                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          67207872                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                787                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2045804                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2046591                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst                784                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2045808                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2046592                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1050123                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1050123                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                45098                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            117231158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               117276256                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           45098                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              45098                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          60175430                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               60175430                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          60175430                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               45098                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           117231158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              177451686                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2046591                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst                44926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            117231922                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               117276848                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           44926                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              44926                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          60175704                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               60175704                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          60175704                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               44926                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           117231922                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              177452552                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2046592                       # Number of read requests accepted
 system.physmem.writeReqs                      1050123                       # Number of write requests accepted
-system.physmem.readBursts                     2046591                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                     2046592                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                    1050123                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                130897024                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     84800                       # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM                130898112                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83776                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                  67206400                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 130981824                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                 130981888                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys               67207872                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1325                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                     1309                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              127282                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              124660                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              121599                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              123658                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              122616                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              122675                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              123246                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              123764                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              131397                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              133514                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             132084                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133304                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             133248                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             133365                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             129309                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             129545                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         962724                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              127279                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              124661                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              121601                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              123659                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              122620                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              122678                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              123247                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              123768                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              131395                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              133511                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             132082                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             133309                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             133249                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             133361                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             129308                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             129555                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               66136                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               64410                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               62576                       # Per bank write bursts
@@ -71,25 +71,25 @@ system.physmem.perBankWrBursts::3               63006                       # Pe
 system.physmem.perBankWrBursts::4               63000                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               63100                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               64443                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65436                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67310                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               67797                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67549                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65435                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67311                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               67795                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67548                       # Per bank write bursts
 system.physmem.perBankWrBursts::11              67882                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67326                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67328                       # Per bank write bursts
 system.physmem.perBankWrBursts::13              67793                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66482                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66483                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              65854                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1116865575000                       # Total gap between requests
+system.physmem.totGap                    1116860484000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2046591                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2046592                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,8 +97,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                1050123                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1916631                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    128617                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                   1916633                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    128632                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    32784                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    34018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56910                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    61213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61610                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61708                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61596                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61703                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61754                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    62537                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    62061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    32728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    33960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    56927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    61204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61599                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61654                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    62074                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    61140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       86                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
@@ -193,54 +193,53 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1910448                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.693777                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.830782                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     125.503425                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1485607     77.76%     77.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       305343     15.98%     93.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples      1910141                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.711749                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.835384                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.555895                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1485377     77.76%     77.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       305179     15.98%     93.74% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383        52494      2.75%     96.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20883      1.09%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13429      0.70%     98.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7609      0.40%     98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5497      0.29%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5095      0.27%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        14491      0.76%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1910448                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61128                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.415767                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      160.633753                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          61083     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047           20      0.03%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::384-511        21040      1.10%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13364      0.70%     98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7561      0.40%     98.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5492      0.29%     98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5154      0.27%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        14480      0.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1910141                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61138                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.410579                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      159.595244                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          61092     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           21      0.03%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61128                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61128                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.178707                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.143614                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.099153                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              26983     44.14%     44.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1095      1.79%     45.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              28688     46.93%     92.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3942      6.45%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                361      0.59%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 49      0.08%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                  8      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           61138                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61138                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.175897                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.140866                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.098115                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27038     44.22%     44.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1118      1.83%     46.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              28658     46.87%     92.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3907      6.39%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                362      0.59%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 47      0.08%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  6      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::26                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61128                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38113681000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76462418500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10226330000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18635.07                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           61138                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38118822750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76467879000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10226415000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18637.43                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37385.07                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  37387.43                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         117.20                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          60.17                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                      117.28                       # Average system read bandwidth in MiByte/s
@@ -250,46 +249,46 @@ system.physmem.busUtil                           1.39                       # Da
 system.physmem.busUtilRead                       0.92                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     773150                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    411758                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   37.80                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.21                       # Row buffer hit rate for writes
-system.physmem.avgGap                       360661.52                       # Average gap between requests
-system.physmem.pageHitRate                      38.28                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 7040439000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3841509375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7717788000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3318453360                       # Energy for write commands per rank (pJ)
+system.physmem.avgWrQLen                        24.32                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     773327                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    411912                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   37.81                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.23                       # Row buffer hit rate for writes
+system.physmem.avgGap                       360659.76                       # Average gap between requests
+system.physmem.pageHitRate                      38.29                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 7038745560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3840585375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7718170200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3318446880                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy            72947846400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           420410239110                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           301335056250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             816611331495                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              731.167175                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   498591665750                       # Time in different power states
+system.physmem_0.actBackEnergy           420695682570                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           301084680000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             816644156985                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              731.196552                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   498171573500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     37294400000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    580976292250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    581394006750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7402532760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 4039080375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                8234920200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3486194640                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                 7401920400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 4038746250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                8234982600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3486201120                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy            72947846400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           429557025690                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           293311559250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             818979159315                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              733.287251                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   485194866750                       # Time in different power states
+system.physmem_1.actBackEnergy           429157184085                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           293662305750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             818929186605                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              733.242498                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   485776924250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     37294400000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    594372992750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    593789084750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               239639075                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186342287                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups               239639085                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186342301                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          14526140                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            130646101                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122079387                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups            130646105                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               122079391                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             93.442809                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                15657029                       # Number of times the RAS was used to get a target.
@@ -412,68 +411,68 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       2233731339                       # number of cpu cycles simulated
+system.cpu.numCycles                       2233721157                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563088                       # Number of instructions committed
 system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      41470082                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      41470128                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.446190                       # CPI: cycles per instruction
-system.cpu.ipc                               0.691472                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1834124286                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       399607053                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9221039                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.616235                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624218894                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9225135                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.665015                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.446183                       # CPI: cycles per instruction
+system.cpu.ipc                               0.691475                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1834122800                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       399598357                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9221041                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4085.616187                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624218895                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9225137                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.665000                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        9804990500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.616235                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4085.616187                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997465                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997465                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          253                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1229                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          245                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1237                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         2553                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1276841917                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1276841917                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    453887722                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       453887722                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170331049                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170331049                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1276841907                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276841907                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    453887715                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       453887715                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170331057                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170331057                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624218771                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624218771                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624218772                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624218772                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7334497                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7334497                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2254998                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2254998                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     624218772                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624218772                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    624218773                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624218773                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7334498                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7334498                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2254990                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2254990                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9589495                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9589495                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9589497                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9589497                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 190935436500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 109060065500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 299995502000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 299995502000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 299995502000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 299995502000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461222219                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461222219                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9589488                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9589488                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9589490                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9589490                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 190927662500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 190927662500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 109073789000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 109073789000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 300001451500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 300001451500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 300001451500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 300001451500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    461222213                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461222213                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
@@ -482,10 +481,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    633808266                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    633808266                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    633808269                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    633808269                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    633808260                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    633808260                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    633808263                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    633808263                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015902                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.015902                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013066                       # miss rate for WriteReq accesses
@@ -496,14 +495,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.015130
 system.cpu.dcache.demand_miss_rate::total     0.015130                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015130                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015130                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31283.764369                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31283.757845                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.456072                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.456072                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48369.965720                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48369.965720                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.407624                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31284.407624                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.401100                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31284.401100                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -512,36 +511,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3684564                       # number of writebacks
-system.cpu.dcache.writebacks::total           3684564                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      3684566                       # number of writebacks
+system.cpu.dcache.writebacks::total           3684566                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          215                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          215                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364146                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       364146                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       364361                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       364361                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       364361                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       364361                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7334282                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7334282                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890852                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1890852                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364137                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       364137                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       364352                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       364352                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       364352                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       364352                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7334283                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7334283                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890853                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1890853                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9225134                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9225134                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9225135                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9225135                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84757207500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84757207500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9225136                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9225136                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9225137                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9225137                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183587623500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 183587623500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84772423500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84772423500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        74000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        74000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 268352592000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 268352666000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268360047000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 268360047000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268360121000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 268360121000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
@@ -552,24 +551,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014555
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014555                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014555                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014555                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.434361                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.434361                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44832.900019                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44832.900019                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        74000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        74000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.091138                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.091138                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.096006                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.096006                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                29                       # number of replacements
-system.cpu.icache.tags.tagsinuse           661.385274                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           465281545                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           661.384835                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           465281420                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               820                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          567416.518293                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          567416.365854                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   661.385274                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   661.384835                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.322942                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.322942                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
@@ -577,44 +576,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           32
 system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         930565550                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        930565550                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    465281545                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       465281545                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     465281545                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        465281545                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    465281545                       # number of overall hits
-system.cpu.icache.overall_hits::total       465281545                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         930565300                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        930565300                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    465281420                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       465281420                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     465281420                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        465281420                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    465281420                       # number of overall hits
+system.cpu.icache.overall_hits::total       465281420                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          820                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           820                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          820                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            820                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          820                       # number of overall misses
 system.cpu.icache.overall_misses::total           820                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62174000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62174000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62174000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62174000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62174000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62174000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    465282365                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    465282365                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    465282365                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    465282365                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    465282365                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    465282365                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     62291000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     62291000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     62291000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     62291000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     62291000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     62291000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    465282240                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    465282240                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    465282240                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    465282240                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    465282240                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    465282240                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75821.951220                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75821.951220                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75964.634146                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75964.634146                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75964.634146                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75964.634146                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75964.634146                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75964.634146                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -623,129 +622,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks           29                       # number of writebacks
+system.cpu.icache.writebacks::total                29                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          820                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          820                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          820                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          820                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          820                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          820                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61354000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     61354000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61354000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     61354000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61354000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     61354000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61471000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     61471000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61471000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     61471000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61471000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     61471000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74964.634146                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 74964.634146                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 74964.634146                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          2013890                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31258.297879                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14509190                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          2043665                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.099593                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          2013920                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31258.306174                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14509192                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2043695                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.099490                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      59769702000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14832.420356                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.588666                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.288857                       # Average occupied blocks per requestor
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -766,120 +771,121 @@ system.cpu.l2cache.demand_mshr_hits::total            5                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.959756                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423702                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423702                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.956098                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.956098                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.169703                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.169703                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.221764                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.956098                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.221765                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.221830                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.959756                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.221764                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.956098                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.221765                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.221830                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77915.750182                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77915.750182                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66309.311224                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66309.311224                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77284.125886                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77284.125886                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66309.311224                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77531.476316                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77527.177376                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66309.311224                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77531.476316                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77527.177376                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18447023                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9221080                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18447027                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9221082                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1287                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1281                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7335103                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4734687                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6498677                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1890852                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1890852                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7335104                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4734689                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           29                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6498678                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1890853                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1890853                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          820                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7334283                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7334284                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1669                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27669715                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27671384                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52480                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826220736                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          826273216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2013890                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20460913                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000220                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.014837                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27669721                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27671390                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826220992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          826275328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2013920                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11239877                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000258                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.016091                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           20456426     99.98%     99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4481      0.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11236984     99.97%     99.97% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2887      0.03%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  6      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20460913                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12908075500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11239877                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12908108500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1230499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13837704496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13837707496                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1245436                       # Transaction distribution
-system.membus.trans_dist::Writeback           1050123                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           962723                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            801155                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           801155                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1245436                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6106028                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6106028                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198189696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               198189696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1245433                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1050123                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           962724                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            801159                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           801159                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1245433                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6106031                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6106031                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198189760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               198189760                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4059437                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4059439                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 4059437    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 4059439    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             4059437                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8662977500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4059439                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8663213500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11191643250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        11191513500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 09d71d56d..41989d0e2 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.770336                       # Number of seconds simulated
-sim_ticks                                770336310500                       # Number of ticks simulated
-final_tick                               770336310500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.767966                       # Number of seconds simulated
+sim_ticks                                767965542000                       # Number of ticks simulated
+final_tick                               767965542000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 130811                       # Simulator instruction rate (inst/s)
-host_op_rate                                   140929                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               65240720                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314688                       # Number of bytes of host memory used
-host_seconds                                 11807.60                       # Real time elapsed on the host
+host_inst_rate                                 135762                       # Simulator instruction rate (inst/s)
+host_op_rate                                   146263                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               67501614                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354608                       # Number of bytes of host memory used
+host_seconds                                 11377.00                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             66496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         238054976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     63977600                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            302099072                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        66496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           66496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    104804160                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         104804160                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1039                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            3719609                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       999650                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               4720298                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1637565                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1637565                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                86321                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            309027334                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     83051518                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               392165172                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           86321                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              86321                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         136049877                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              136049877                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         136049877                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               86321                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           309027334                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     83051518                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              528215049                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       4720298                       # Number of read requests accepted
-system.physmem.writeReqs                      1637565                       # Number of write requests accepted
-system.physmem.readBursts                     4720298                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1637565                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                301639360                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    459712                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104801536                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 302099072                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              104804160                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     7183                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      11                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              296850                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              294498                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              288916                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              292682                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              290729                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              289596                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              284483                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              281209                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              297427                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              303552                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             295336                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             302232                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             303231                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             302345                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             297342                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             292687                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              104014                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              101992                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               99263                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               99947                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               99433                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               98879                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              102579                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104318                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              105363                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              104471                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             102169                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             102930                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             102920                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             102581                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104115                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102550                       # Per bank write bursts
+system.physmem.bytes_read::cpu.inst             65024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         235466816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     63671744                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            299203584                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        65024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           65024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    104705856                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         104705856                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1016                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            3679169                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       994871                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               4675056                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1636029                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1636029                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                84670                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            306611173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     82909637                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               389605481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           84670                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              84670                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         136341867                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              136341867                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         136341867                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               84670                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           306611173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     82909637                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              525947348                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       4675056                       # Number of read requests accepted
+system.physmem.writeReqs                      1636029                       # Number of write requests accepted
+system.physmem.readBursts                     4675056                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1636029                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                298722176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    481408                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 104702912                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 299203584                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              104705856                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     7522                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      20                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs        3003359                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              301326                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              298715                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              284983                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              287209                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              287920                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              285373                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              281637                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              277868                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              293986                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              298704                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             291815                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             297314                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             299397                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             298122                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             294010                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             289155                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103823                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              101759                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               99255                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               99822                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               99277                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               98671                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              102768                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104279                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              105369                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104220                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             102032                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             102651                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             102828                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             102619                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104194                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102416                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    770336158500                       # Total gap between requests
+system.physmem.totGap                    767965500500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 4720298                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 4675056                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1637565                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   2783946                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1045590                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    328353                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    232144                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    151285                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     83614                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     38578                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     23869                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     18243                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4278                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1738                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      814                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      426                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1636029                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   2763524                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1029428                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    325669                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    231653                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    149305                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     81525                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     37575                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     23680                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     18003                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4105                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1652                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      753                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      428                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      226                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
@@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    23160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    24842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    60100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    75642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    85493                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    93558                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    99663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   103776                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   105596                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   106074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   106708                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   108208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   111119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   114322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   105421                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   102034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   101193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    25881                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    28453                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    56077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    73176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    84966                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    93772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    99981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   103836                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   105655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   106267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   107107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   108335                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   109521                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   111129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   111161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   103920                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   101092                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   100232                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -197,114 +197,123 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      4289513                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       94.751761                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      78.903148                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     101.431882                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3416049     79.64%     79.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       675171     15.74%     95.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        96645      2.25%     97.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35451      0.83%     98.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        23003      0.54%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12074      0.28%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         6995      0.16%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5025      0.12%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19100      0.45%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        4289513                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         98662                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        47.769871                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       32.372187                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       98.540692                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255           96215     97.52%     97.52% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511          1195      1.21%     98.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767           729      0.74%     99.47% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023          403      0.41%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1279           87      0.09%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1535           19      0.02%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791            4      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1792-2047            4      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2303            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2304-2559            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-2815            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3327            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-3839            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5120-5375            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           98662                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         98662                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.597312                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.563431                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.103098                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              72815     73.80%     73.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1780      1.80%     75.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              18354     18.60%     94.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3927      3.98%     98.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                986      1.00%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                404      0.41%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                201      0.20%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                116      0.12%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 44      0.04%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 22      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 12      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           98662                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   131160021238                       # Total ticks spent queuing
-system.physmem.totMemAccLat              219530927488                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  23565575000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27828.73                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples      4246279                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       95.006264                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      78.933304                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     102.667614                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3382951     79.67%     79.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       666013     15.68%     95.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        94842      2.23%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35210      0.83%     98.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        22787      0.54%     98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12374      0.29%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7276      0.17%     99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5157      0.12%     99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19669      0.46%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        4246279                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         97783                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        47.733256                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       99.725873                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-127           93691     95.82%     95.82% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-255          1680      1.72%     97.53% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-383           798      0.82%     98.35% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::384-511           374      0.38%     98.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-639           374      0.38%     99.11% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::640-767           340      0.35%     99.46% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-895           220      0.22%     99.69% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::896-1023          159      0.16%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1151           76      0.08%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1152-1279           37      0.04%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1407           11      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1408-1535            7      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-1663            5      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1664-1791            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1792-1919            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2176-2303            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2304-2431            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2432-2559            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3200-3327            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3712-3839            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3840-3967            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           97783                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         97783                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.730751                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.687620                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.251075                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              68399     69.95%     69.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               2006      2.05%     72.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              18369     18.79%     90.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               5745      5.88%     96.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20               1950      1.99%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                718      0.73%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                317      0.32%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                149      0.15%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 75      0.08%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 33      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 10      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           97783                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   128413030932                       # Total ticks spent queuing
+system.physmem.totMemAccLat              215929293432                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  23337670000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27511.96                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46578.73                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         391.57                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         136.05                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      392.17                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      136.05                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46261.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         388.98                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         136.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      389.61                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      136.34                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           4.12                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.06                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.44                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1707273                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    353841                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   36.22                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  21.61                       # Row buffer hit rate for writes
-system.physmem.avgGap                       121162.75                       # Average gap between requests
-system.physmem.pageHitRate                      32.46                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                16082924760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 8775405375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy               18087474600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5251508640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            50314383600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           409609386630                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           102893262750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             611014346355                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              793.182199                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   168633417027                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     25723100000                       # Time in different power states
+system.physmem.busUtil                           4.10                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.04                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.07                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.42                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.89                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1709654                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    347571                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   36.63                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  21.25                       # Row buffer hit rate for writes
+system.physmem.avgGap                       121685.18                       # Average gap between requests
+system.physmem.pageHitRate                      32.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                15953799960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 8704950375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy               17977486800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5246246880                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            50159272800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           414403163865                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            97263315750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             609708236430                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              793.934243                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   159282861364                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     25643800000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    575976400473                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    583033093643                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                16345687680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 8918778000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy               18674323200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5359543200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            50314383600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           410844304170                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           101810001750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             612267021600                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              794.808347                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   166829398639                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     25723100000                       # Time in different power states
+system.physmem_1.actEnergy                16147600560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 8810694750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy               18427445400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5354300880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            50159272800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           410341742010                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           100825962000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             610067018400                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              794.401440                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   165241048217                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     25643800000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    577780670361                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    577073869783                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               286278310                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         223407435                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14630059                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            158227088                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               150348964                       # Number of BTB hits
+system.cpu.branchPred.lookups               286290965                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         223414875                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14630075                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            157650249                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               150360830                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.021002                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                16641238                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             95.376208                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                16641594                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 64                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -424,128 +433,128 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1540672622                       # number of cpu cycles simulated
+system.cpu.numCycles                       1535931085                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           13926355                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2067514794                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   286278310                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          166990202                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1512022873                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29284737                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  188                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles         1021                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 656940964                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   966                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1540592805                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.437738                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.228920                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           13926236                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2067547876                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   286290965                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          167002424                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1507284638                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29284969                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  196                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          917                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 656963855                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   927                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1535854471                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.442200                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.228202                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                458181319     29.74%     29.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                465421558     30.21%     59.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                101422593      6.58%     66.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                515567335     33.47%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                453416615     29.52%     29.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                465436740     30.30%     59.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                101431033      6.60%     66.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                515570083     33.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1540592805                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.185814                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.341956                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 74646858                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             543216907                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 849967493                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              58119883                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               14641664                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             42201795                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   757                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2037179352                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              52470113                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               14641664                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                139717275                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               462450514                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          13916                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 837848883                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              85920553                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1976355004                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              26745374                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              45156757                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 125486                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1486003                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               25049006                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1985823032                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            9128033727                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2432836892                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               151                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1535854471                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.186396                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.346120                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 74705927                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             538395080                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 849912555                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              58199125                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               14641784                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             42202960                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   740                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2037254051                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              52495885                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               14641784                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                139801946                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               457449218                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          13751                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 837842602                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              86105170                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1976447004                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              26743472                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              45311241                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 126368                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1599527                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               25035305                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1985923292                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            9128451044                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2432959840                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               125                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                310924087                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                156                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            148                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 111428528                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            542554069                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           199305704                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          26941972                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         29270810                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1947933260                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 215                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1857474146                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13497185                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       283901059                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    647116126                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             45                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1540592805                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.205688                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.150881                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                311024347                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                154                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            145                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 111506310                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            542573483                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           199309856                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          26973622                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         29535518                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1948030100                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 211                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1857442950                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13480165                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       283997895                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    647563158                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             41                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1535854471                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.209387                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.150580                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           587702275     38.15%     38.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           325996808     21.16%     59.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           378232244     24.55%     83.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           219639231     14.26%     98.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            29016078      1.88%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                6169      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           582872858     37.95%     37.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           326140941     21.24%     59.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           378202799     24.62%     83.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           219661262     14.30%     98.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            28970430      1.89%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                6181      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1540592805                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1535854471                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu               166081126     41.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   1996      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     41.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              191505284     47.27%     88.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              47530605     11.73%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu               166043738     41.02%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   1958      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              191460391     47.30%     88.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              47270881     11.68%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1138242397     61.28%     61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               801060      0.04%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1138255914     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               800916      0.04%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -567,90 +576,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              32      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              28      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            532116023     28.65%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           186314612     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            532080715     28.65%     89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186305355     10.03%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1857474146                       # Type of FU issued
-system.cpu.iq.rate                           1.205625                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   405119011                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.218102                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5674157044                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2231847189                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1805703414                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 249                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                266                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           72                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2262593018                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     139                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         17811740                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1857442950                       # Type of FU issued
+system.cpu.iq.rate                           1.209327                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   404776968                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.217922                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5668997271                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2232041055                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1805706922                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 233                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                216                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           68                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2262219787                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     131                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         17802666                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     84247735                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        66708                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13149                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     24458659                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     84267149                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        66494                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13286                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     24462811                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      4504401                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4884981                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      4478194                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       4870766                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               14641664                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                25329983                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1325123                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1947933556                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               14641784                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                25370881                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1332488                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1948030384                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             542554069                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            199305704                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                153                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 159005                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1165002                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13149                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        7699177                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8705456                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             16404633                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1827812064                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             516937908                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29662082                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             542573483                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            199309856                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                149                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 159276                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1171811                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13286                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        7699902                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8704078                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             16403980                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1827785519                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             516901938                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          29657431                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            81                       # number of nop insts executed
-system.cpu.iew.exec_refs                    698690935                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                229542500                       # Number of branches executed
-system.cpu.iew.exec_stores                  181753027                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.186373                       # Inst execution rate
-system.cpu.iew.wb_sent                     1808734068                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1805703486                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1169239698                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1689624086                       # num instructions consuming a value
+system.cpu.iew.exec_nop                            73                       # number of nop insts executed
+system.cpu.iew.exec_refs                    698651224                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                229542579                       # Number of branches executed
+system.cpu.iew.exec_stores                  181749286                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.190018                       # Inst execution rate
+system.cpu.iew.wb_sent                     1808742163                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1805706990                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1169201528                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1689618558                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.172023                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.692012                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.175643                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.691991                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       258007667                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       258099025                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14629355                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1501111622                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.108533                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.025633                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14629375                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1496362804                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.112051                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.027734                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    920819202     61.34%     61.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    250634053     16.70%     78.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    110061016      7.33%     85.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     55281373      3.68%     89.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29321487      1.95%     91.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     34081425      2.27%     93.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     24716781      1.65%     94.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     18131809      1.21%     96.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     58064476      3.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    916038990     61.22%     61.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    250656359     16.75%     77.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    110050903      7.35%     85.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     55261193      3.69%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29363802      1.96%     90.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     34102831      2.28%     93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     24718362      1.65%     94.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     18151757      1.21%     96.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     58018607      3.88%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1501111622                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1496362804                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
 system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -696,76 +705,76 @@ system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              58064476                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3365086648                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3883566462                       # The number of ROB writes
-system.cpu.timesIdled                             859                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           79817                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              58018607                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3360475057                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3883759706                       # The number of ROB writes
+system.cpu.timesIdled                             836                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           76614                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
 system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.997481                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.997481                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.002525                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.002525                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2175803949                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1261568723                       # number of integer regfile writes
+system.cpu.cpi                               0.994411                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.994411                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.005620                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.005620                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2175771978                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1261585669                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        40                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       54                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                6965710140                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                551865181                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               675846539                       # number of misc regfile reads
+system.cpu.fp_regfile_writes                       50                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                6965626191                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                551852831                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               675841321                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements          17004606                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.964973                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           638063275                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          17005118                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.521838                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          77839500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.964973                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999932                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999932                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements          17004065                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.964813                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           638072070                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          17004577                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.523549                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          77932500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.964813                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999931                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999931                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          420                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          416                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1335698850                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1335698850                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    469343498                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       469343498                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    168719659                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      168719659                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1335720557                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1335720557                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    469353506                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       469353506                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    168718419                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      168718419                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     638063157                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        638063157                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    638063157                       # number of overall hits
-system.cpu.dcache.overall_hits::total       638063157                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     17417197                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      17417197                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3866388                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3866388                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     638071925                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        638071925                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    638071925                       # number of overall hits
+system.cpu.dcache.overall_hits::total       638071925                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     17418313                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      17418313                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3867628                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3867628                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     21283585                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       21283585                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21283587                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21283587                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 415522893500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 415522893500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 149855935942                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 149855935942                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       216000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       216000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 565378829442                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 565378829442                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 565378829442                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 565378829442                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    486760695                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    486760695                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     21285941                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       21285941                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21285943                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21285943                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 412331077000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 412331077000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 148962559255                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 148962559255                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       196500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       196500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 561293636255                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 561293636255                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 561293636255                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 561293636255                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    486771819                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    486771819                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
@@ -774,440 +783,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    659346742                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    659346742                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    659346744                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    659346744                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035782                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.035782                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022403                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.022403                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    659357866                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    659357866                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    659357868                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    659357868                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035783                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.035783                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022410                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.022410                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032280                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032280                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032280                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032280                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23857.047348                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23857.047348                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38758.638797                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38758.638797                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        54000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        54000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26564.078817                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26564.078817                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26564.076320                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26564.076320                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20755892                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3446894                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            946527                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67143                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.928473                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    51.336610                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032283                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032283                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032283                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032283                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23672.273945                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23672.273945                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.224126                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.224126                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        49125                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        49125                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26369.218831                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26369.218831                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26369.216353                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26369.216353                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     20544187                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3409553                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            942936                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67231                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.787467                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    50.714001                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      4835415                       # number of writebacks
-system.cpu.dcache.writebacks::total           4835415                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3149636                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3149636                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1128832                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1128832                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks     17004065                       # number of writebacks
+system.cpu.dcache.writebacks::total          17004065                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3151291                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3151291                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1130068                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1130068                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4278468                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4278468                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4278468                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4278468                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14267561                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total     14267561                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737556                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2737556                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4281359                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4281359                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4281359                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4281359                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14267022                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total     14267022                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737560                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2737560                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     17005117                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     17005117                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     17005118                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     17005118                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335383172000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 335383172000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116381847286                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 116381847286                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data     17004582                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     17004582                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     17004583                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     17004583                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331931922000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 331931922000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115721294597                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 115721294597                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        68000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        68000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451765019286                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 451765019286                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451765087286                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 451765087286                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029311                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029311                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447653216597                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 447653216597                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447653284597                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 447653284597                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029309                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029309                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015862                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025791                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025791                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025791                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025791                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23506.692700                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23506.692700                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42513.047144                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42513.047144                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025790                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025790                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025790                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025790                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23265.676747                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23265.676747                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42271.692528                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42271.692528                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        68000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        68000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26566.416408                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26566.416408                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26566.418844                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26566.418844                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26325.446671                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26325.446671                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26325.449121                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26325.449121                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               592                       # number of replacements
-system.cpu.icache.tags.tagsinuse           446.127099                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           656939322                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1080                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          608277.150000                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               587                       # number of replacements
+system.cpu.icache.tags.tagsinuse           444.617750                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           656962266                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1073                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          612266.790308                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   446.127099                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.871342                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.871342                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          488                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   444.617750                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.868394                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.868394                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          486                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.953125                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1313883006                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1313883006                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    656939322                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       656939322                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     656939322                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        656939322                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    656939322                       # number of overall hits
-system.cpu.icache.overall_hits::total       656939322                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1641                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1641                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1641                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1641                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1641                       # number of overall misses
-system.cpu.icache.overall_misses::total          1641                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    107375484                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    107375484                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    107375484                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    107375484                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    107375484                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    107375484                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    656940963                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    656940963                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    656940963                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    656940963                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    656940963                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    656940963                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          441                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1313928777                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1313928777                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    656962266                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       656962266                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     656962266                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        656962266                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    656962266                       # number of overall hits
+system.cpu.icache.overall_hits::total       656962266                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1586                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1586                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1586                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1586                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1586                       # number of overall misses
+system.cpu.icache.overall_misses::total          1586                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     98890487                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     98890487                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     98890487                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     98890487                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     98890487                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     98890487                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    656963852                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    656963852                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total    656963852                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65432.957952                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65432.957952                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65432.957952                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65432.957952                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65432.957952                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65432.957952                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        18112                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets         1654                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               192                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets              10                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    94.333333                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets   165.400000                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62352.135561                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62352.135561                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62352.135561                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 62352.135561                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62352.135561                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62352.135561                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        17132                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          145                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               194                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    88.309278                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           29                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          561                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          561                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          561                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          561                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          561                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          561                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1080                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1080                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1080                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1080                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1080                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1080                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     76771987                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     76771987                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     76771987                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     76771987                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     76771987                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     76771987                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks          587                       # number of writebacks
+system.cpu.icache.writebacks::total               587                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          511                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          511                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          511                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          511                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          511                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          511                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1075                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1075                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1075                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1075                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1075                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1075                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     73172990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     73172990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     73172990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     73172990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     73172990                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     73172990                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71085.173148                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71085.173148                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71085.173148                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71085.173148                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71085.173148                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71085.173148                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68067.897674                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68067.897674                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68067.897674                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68067.897674                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68067.897674                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68067.897674                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued     11620529                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified     11640215                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit        14721                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued     11609988                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified     11638125                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit        19145                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4656609                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements          4712362                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16129.977996                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           27367770                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          4728288                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             5.788093                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      29479829000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  5227.936161                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    18.488571                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  7534.908085                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  3348.645178                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.319088                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001128                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.459894                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.204385                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.984496                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          817                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15109                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            3                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1          599                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          215                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          502                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2347                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1263                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1830                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.049866                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.922180                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        551302751                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       551302751                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      4835415                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      4835415                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1752988                       # number of ReadExReq hits
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-system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11483491                       # number of ReadSharedReq hits
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-system.cpu.l2cache.demand_hits::cpu.data     13236479                       # number of demand (read+write) hits
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-system.cpu.l2cache.ReadCleanReq_misses::total         1039                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2784028                       # number of ReadSharedReq misses
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-system.cpu.l2cache.overall_misses::cpu.data      3768639                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      3769678                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  99828708999                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  99828708999                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75380000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     75380000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 238235637000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 238235637000                       # number of ReadSharedReq miss cycles
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-system.cpu.l2cache.demand_miss_latency::cpu.data 338064345999                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 338139725999                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     75380000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 338064345999                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 338139725999                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      4835415                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      4835415                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737599                       # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1080                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         1080                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14267519                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.inst         1080                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     17005118                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     17006198                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1080                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     17005118                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     17006198                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.359662                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.359662                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.962037                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.962037                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.195130                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.195130                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.962037                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.221618                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.221665                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.962037                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.221618                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.221665                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101388.984075                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101388.984075                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72550.529355                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72550.529355                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85572.284833                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85572.284833                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72550.529355                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89704.624401                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89699.896383                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72550.529355                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89704.624401                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89699.896383                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs           30                       # number of cycles access was blocked
+system.cpu.l2cache.prefetcher.pfRemovedFull            5                       # number of prefetches dropped due to prefetch queue size
+system.cpu.l2cache.prefetcher.pfSpanPage      4657211                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements          4708196                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16099.895635                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           22828795                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          4724118                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.832393                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      54830616500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 13098.409047                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data     2.246929                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  2999.239659                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.799463                       # Average percentage of cache occupancy
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+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358157                       # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.946977                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.946977                       # miss rate for ReadCleanReq accesses
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+system.cpu.l2cache.overall_miss_rate::total     0.219245                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22916.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22916.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101046.539390                       # average ReadExReq miss latency
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70417.485265                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85286.105404                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85286.105404                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70417.485265                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89431.907399                       # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70417.485265                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89431.907399                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89426.715710                       # average overall miss latency
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 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                2                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs           15                       # average number of cycles each access was blocked
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 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1637565                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1637565                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         4105                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         4105                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45593                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45593                       # number of ReadSharedReq MSHR hits
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-system.cpu.l2cache.overall_mshr_hits::total        49698                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks       100082                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total       100082                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1001959                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total      1001959                       # number of HardPFReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses::total      4721939                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  72923665986                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  72923665986                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  93548158999                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  93548158999                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     69146000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     69146000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218917649000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218917649000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     69146000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312465807999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 312534953999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     69146000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312465807999                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72923665986                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 385458619985                       # number of overall MSHR miss cycles
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
+system.cpu.l2cache.writebacks::writebacks      1636029                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1636029                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3958                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3958                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45559                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45559                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data        49517                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total        49518                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data        49517                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total        49518                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1144921                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total      1144921                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       976534                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       976534                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1017                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1017                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2701329                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2701329                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1017                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      3677863                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      3678880                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1017                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      3677863                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1144921                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      4823801                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  72325395404                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  72325395404                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       101500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       101500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  92841040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  92841040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65516000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65516000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215255322500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215255322500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 308096362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 308161878500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65516000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 308096362500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72325395404                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 380487273904                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358163                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358163                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.962037                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.962037                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.191935                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.191935                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.962037                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.218695                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.218743                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.962037                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.218695                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356711                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356711                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.946047                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.946047                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189341                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189341                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.946047                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216287                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.216333                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.946047                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216287                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.277660                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72781.087835                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95408.043397                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95408.043397                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66550.529355                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66550.529355                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79942.612843                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79942.612843                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66550.529355                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84020.103572                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84015.224275                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66550.529355                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84020.103572                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81631.427256                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.283659                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63170.642694                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95071.999541                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95071.999541                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64420.845624                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64420.845624                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79684.970805                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79684.970805                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64420.845624                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83770.483702                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83765.134633                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64420.845624                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83770.483702                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78877.066841                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     34011398                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     17005208                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21592                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       111772                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       111653                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          119                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp      14268599                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      6472980                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict     15222988                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq      1281199                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2737599                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2737599                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1080                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq     14267519                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2748                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     50993254                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          50996002                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        69120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1397794112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1397863232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     5993561                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     40004959                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.003877                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.062190                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests     34010311                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     17004668                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21296                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops      2921208                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops      2902417                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        18791                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp      14268046                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      6464245                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     12155140                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      5774511                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq      1435676                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFResp            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq            6                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            6                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2737604                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2737604                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1075                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266973                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2731                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     50991946                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          50994677                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       105984                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2175190848                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2175296832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     8846223                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     25851874                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.114549                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.320751                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           39849994     99.61%     99.61% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             154846      0.39%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                119      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           22909361     88.62%     88.62% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            2923722     11.31%     99.93% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              18791      0.07%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       40004959                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    21841114998                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          2.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1620000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       25851874                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    34009808017                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          4.4                       # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy        10525                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1610997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   25507681990                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   25506872492                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            3739654                       # Transaction distribution
-system.membus.trans_dist::Writeback           1637565                       # Transaction distribution
-system.membus.trans_dist::CleanEvict          3065415                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            980644                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           980644                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       3739654                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     14143576                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               14143576                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    406903232                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               406903232                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            3698381                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1636029                       # Transaction distribution
+system.membus.trans_dist::CleanEvict          3003353                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            976674                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           976674                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       3698382                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     13989505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               13989505                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    403909376                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               403909376                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           9423278                       # Request fanout histogram
+system.membus.snoop_fanout::samples           9314444                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 9423278    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 9314444    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             9423278                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         17318873513                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        25673835894                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             9314444                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         17663480706                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        25423271236                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 3fad64f8d..02c08f292 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,41 +1,41 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.363368                       # Number of seconds simulated
-sim_ticks                                2363368369500                       # Number of ticks simulated
-final_tick                               2363368369500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.377030                       # Number of seconds simulated
+sim_ticks                                2377029670500                       # Number of ticks simulated
+final_tick                               2377029670500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1008024                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1086287                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1548215415                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 315828                       # Number of bytes of host memory used
-host_seconds                                  1526.51                       # Real time elapsed on the host
+host_inst_rate                                 970948                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1046333                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1499891883                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 316204                       # Number of bytes of host memory used
+host_seconds                                  1584.80                       # Real time elapsed on the host
 sim_insts                                  1538759602                       # Number of instructions simulated
 sim_ops                                    1658228915                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         124870144                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            124909568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124870272                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124909696                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        39424                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           39424                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks     65352128                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          65352128                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                616                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1951096                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1951712                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1951098                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1951714                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1021127                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1021127                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                16681                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             52835667                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52852348                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           16681                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              16681                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          27652112                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               27652112                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          27652112                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               16681                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            52835667                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               80504461                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                16585                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             52532063                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52548648                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           16585                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              16585                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          27493190                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               27493190                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          27493190                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               16585                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            52532063                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               80041838                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -154,7 +154,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       4726736739                       # number of cpu cycles simulated
+system.cpu.numCycles                       4754059341                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1538759602                       # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs                     633153380                       # nu
 system.cpu.num_load_insts                   458306334                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               4726736738.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               4754059340.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         213462427                       # Number of branches fetched
@@ -215,19 +215,19 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1664032481                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           9111140                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4083.732103                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4083.741120                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           618380069                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9115236                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             67.840270                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       25164683500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4083.732103                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997005                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997005                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle       25224281500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4083.741120                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997007                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997007                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1213                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2578                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1156                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2640                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          147                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses        1264105846                       # Number of tag accesses
@@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data      9115235                       # n
 system.cpu.dcache.demand_misses::total        9115235                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9115236                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9115236                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143052931500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57408921000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57408921000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200461852500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200461852500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200461852500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200461852500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 151235084500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  62883763000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  62883763000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 214118847500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 214118847500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 214118847500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 214118847500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    454909135                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    454909135                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
@@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.014526
 system.cpu.dcache.demand_miss_rate::total     0.014526                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.014526                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.014526                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21991.956598                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21991.954185                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23490.216928                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23490.214351                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9115235
 system.cpu.dcache.demand_mshr_misses::total      9115235                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9115236                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  55519772000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  55519772000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        54000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        54000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 191346617500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 191346671500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  60994614000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  60994614000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        61000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        61000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 205003612500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 205003673500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015885                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015885                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                       # mshr miss rate for WriteReq accesses
@@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014526
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014526                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014526                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014526                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        54000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        54000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        61000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        61000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 7                       # number of replacements
-system.cpu.icache.tags.tagsinuse           515.003151                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           515.144337                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1544564953                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               638                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          2420948.202194                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   515.003151                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.251466                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.251466                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   515.144337                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.251535                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.251535                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          631                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
@@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst          638                       # n
 system.cpu.icache.demand_misses::total            638                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          638                       # number of overall misses
 system.cpu.icache.overall_misses::total           638                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     34234000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     34234000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     34234000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     34234000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     34234000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     34234000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     38540000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     38540000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     38540000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     38540000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     38540000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     38540000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1544565591                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1544565591                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1544565591                       # number of demand (read+write) accesses
@@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53658.307210                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53658.307210                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 60407.523511                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 60407.523511                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -405,93 +405,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks            7                       # number of writebacks
+system.cpu.icache.writebacks::total                 7                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          638                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          638                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          638                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          638                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          638                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          638                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     33596000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     33596000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     33596000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     33596000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     33596000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     33596000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     37902000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     37902000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     37902000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     37902000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     37902000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     37902000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1919018                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31008.199290                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14386233                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1948786                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.382151                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     150067869000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    23.734659                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.473510                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000724                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.472061                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.946295                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          1919027                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31012.105366                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14386231                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1948795                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.382116                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     150459065000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    23.646166                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.473115                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000722                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.472578                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.946414                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29768                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1084                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1732                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26839                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1085                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1728                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26842                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908447                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149644895                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149644895                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      3681379                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3681379                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1107017                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1107017                       # number of ReadExReq hits
+system.cpu.l2cache.tags.tag_accesses        149644904                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149644904                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3681379                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3681379                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks            7                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total            7                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1107015                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1107015                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           22                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total           22                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6057123                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total      6057123                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           22                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7164140                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7164162                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7164138                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7164160                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           22                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7164140                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7164162                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       782132                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       782132                       # number of ReadExReq misses
+system.cpu.l2cache.overall_hits::cpu.data      7164138                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7164160                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       782134                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       782134                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          616                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total          616                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1168964                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total      1168964                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          616                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1951096                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1951712                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1951098                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1951714                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          616                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1951096                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1951712                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41062370000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  41062370000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     32383000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     32383000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  61386933500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  61386933500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     32383000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 102481686500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     32383000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 102481686500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      3681379                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3681379                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data      1951098                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1951714                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  46537233000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  46537233000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     36689000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     36689000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  69569093500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  69569093500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     36689000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 116143015500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     36689000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 116143015500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3681379                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3681379                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks            7                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total            7                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889149                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      1889149                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          638                       # number of ReadCleanReq accesses(hits+misses)
@@ -504,30 +510,30 @@ system.cpu.l2cache.demand_accesses::total      9115874                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst          638                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      9115236                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      9115874                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.414013                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.414013                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.414014                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.414014                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.965517                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.965517                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161770                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161770                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965517                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.214048                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214100                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.214101                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965517                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.214048                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214100                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.214101                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -538,58 +544,58 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1021127                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1021127                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          226                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          226                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782132                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       782132                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          219                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          219                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782134                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       782134                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          616                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total          616                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1168964                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1168964                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          616                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1951096                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1951712                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1951098                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1951714                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          616                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1951096                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1951712                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  33241050000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  33241050000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     26223000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     26223000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  49697293500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  49697293500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     26223000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  82938343500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  82964566500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     26223000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  82938343500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  82964566500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1951098                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1951714                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  38715893000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  38715893000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     30529000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     30529000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  57879453500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  57879453500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30529000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  96595346500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  96625875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30529000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  96595346500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  96625875500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.414013                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.414013                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.414014                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.414014                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965517                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161770                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161770                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214048                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214100                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214101                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214048                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214100                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214101                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18227021                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9111154                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -598,8 +604,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops         1063                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1063                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp       7226725                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4702506                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6326508                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4702506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean            7                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6326510                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1889149                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1889149                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          638                       # Transaction distribution
@@ -607,51 +614,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq      7226087
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1283                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27340461                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total          27341744                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        41280                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818983360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          819024192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1919018                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20146039                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000167                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.012936                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size::total          819024640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1919027                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11034901                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000201                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.014186                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           20142667     99.98%     99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               3372      0.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11032680     99.98%     99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2221      0.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20146039                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12794889500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11034901                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12794896500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        957000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13672854000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
 system.membus.trans_dist::ReadResp            1169580                       # Transaction distribution
-system.membus.trans_dist::Writeback           1021127                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           897054                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            782132                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           782132                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1021127                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           897056                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            782134                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           782134                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq       1169580                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5821605                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5821605                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190261696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190261696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5821611                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5821611                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190261824                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190261824                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3870264                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3869897                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3870264    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3869897    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3870264                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7969342268                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3869897                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          7968854000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         9772290268                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         9758570000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index c34bcec93..d16f022eb 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,45 +1,45 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.882285                       # Number of seconds simulated
-sim_ticks                                5882284743500                       # Number of ticks simulated
-final_tick                               5882284743500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.895948                       # Number of seconds simulated
+sim_ticks                                5895947852500                       # Number of ticks simulated
+final_tick                               5895947852500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 704974                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1098413                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1378571885                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 317252                       # Number of bytes of host memory used
-host_seconds                                  4266.94                       # Real time elapsed on the host
+host_inst_rate                                 730138                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1137621                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1431096811                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317400                       # Number of bytes of host memory used
+host_seconds                                  4119.88                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         124876416                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            124919616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124876480                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124919680                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        43200                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           43200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65426432                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65426432                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     65426496                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65426496                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                675                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1951194                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1951869                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1022288                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1022288                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                 7344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             21229237                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                21236581                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst            7344                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total               7344                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          11122622                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               11122622                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          11122622                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst                7344                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            21229237                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               32359203                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data            1951195                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1951870                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1022289                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1022289                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                 7327                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             21180052                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                21187379                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst            7327                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total               7327                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          11096858                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               11096858                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          11096858                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst                7327                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            21180052                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               32284237                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                      11764569487                       # number of cpu cycles simulated
+system.cpu.numCycles                      11791895705                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  3008081022                       # Number of instructions committed
@@ -60,7 +60,7 @@ system.cpu.num_mem_refs                    1677713084                       # nu
 system.cpu.num_load_insts                  1239184746                       # Number of load instructions
 system.cpu.num_store_insts                  438528338                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               11764569486.998001                       # Number of busy cycles
+system.cpu.num_busy_cycles               11791895704.997999                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         248500691                       # Number of branches fetched
@@ -100,19 +100,19 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 4686862596                       # Class of executed instruction
 system.cpu.dcache.tags.replacements           9108581                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4084.586459                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4084.587762                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs          1668600407                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9112677                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            183.107599                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       58853917500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4084.586459                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997213                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997213                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.warmup_cycle       58914110500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4084.587762                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997214                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997214                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          926                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2744                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          320                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          901                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2764                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          329                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses        3364538845                       # Number of tag accesses
@@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data      9112677                       # n
 system.cpu.dcache.demand_misses::total        9112677                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9112677                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9112677                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 142985038000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 142985038000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57429949000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57429949000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200414987000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200414987000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200414987000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200414987000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 151166404000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  62906975000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  62906975000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 214073379000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 214073379000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 214073379000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 214073379000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data   1239184746                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total   1239184746                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    438528338                       # number of WriteReq accesses(hits+misses)
@@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.005432
 system.cpu.dcache.demand_miss_rate::total     0.005432                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.005432                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.207591                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.207591                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.998041                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.998041                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21992.987022                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21992.987022                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21992.987022                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21992.987022                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23491.821229                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23491.821229                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3682721                       # number of writebacks
-system.cpu.dcache.writebacks::total           3682721                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      3682716                       # number of writebacks
+system.cpu.dcache.writebacks::total           3682716                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222850                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      7222850                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889827                       # number of WriteReq MSHR misses
@@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9112677
 system.cpu.dcache.demand_mshr_misses::total      9112677                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9112677                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135762188000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 135762188000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  55540122000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  55540122000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191302310000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 191302310000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191302310000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 191302310000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  61017148000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  61017148000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 204960702000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 204960702000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                       # mshr miss rate for WriteReq accesses
@@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005432                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005432                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.207591                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.207591                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.998041                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.998041                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20992.987022                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20992.987022                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20992.987022                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20992.987022                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                10                       # number of replacements
-system.cpu.icache.tags.tagsinuse           555.701425                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           555.751337                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          4013232207                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               675                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          5945529.195556                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   555.701425                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.271339                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.271339                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   555.751337                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.271363                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.271363                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          665                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          632                       # Occupied blocks per task id
@@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst          675                       # n
 system.cpu.icache.demand_misses::total            675                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          675                       # number of overall misses
 system.cpu.icache.overall_misses::total           675                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     37142500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     37142500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     37142500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     37142500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     37142500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     37142500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     41859500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     41859500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     41859500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     41859500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     41859500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     41859500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   4013232882                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   4013232882                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   4013232882                       # number of demand (read+write) accesses
@@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55025.925926                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55025.925926                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55025.925926                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55025.925926                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55025.925926                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55025.925926                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 62014.074074                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62014.074074                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -267,89 +267,95 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks           10                       # number of writebacks
+system.cpu.icache.writebacks::total                10                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          675                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          675                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          675                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     36467500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     36467500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     36467500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     36467500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     36467500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     36467500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     41184500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     41184500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     41184500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     41184500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     41184500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     41184500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54025.925926                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54025.925926                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54025.925926                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54025.925926                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54025.925926                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54025.925926                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1919162                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31136.006197                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14382006                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1948945                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.379380                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     340768623000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15266.348436                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.605704                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15844.052057                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.465892                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000781                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.483522                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.950196                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          1919169                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31137.283983                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14382005                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1948952                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.379353                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     341160385000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.568616                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.465750                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000780                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.483705                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.950234                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29783                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          997                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          743                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27920                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          995                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          740                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27925                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908905                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149614316                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149614316                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks      3682721                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3682721                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses        149614323                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149614323                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3682716                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3682716                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks           10                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total           10                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data      1107394                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total      1107394                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6054089                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6054089                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7161483                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7161483                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7161483                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7161483                       # number of overall hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6054088                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6054088                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7161482                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7161482                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7161482                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7161482                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       782433                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       782433                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          675                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total          675                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1168761                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1168761                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1168762                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1168762                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1951194                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1951869                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1951195                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1951870                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          675                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1951194                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1951869                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41077744500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  41077744500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     35453500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     35453500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  61359978500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  61359978500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     35453500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 102437723000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 102473176500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     35453500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 102437723000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 102473176500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks      3682721                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3682721                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::cpu.data      1951195                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1951870                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  46554770500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  46554770500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     40170500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     40170500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  69541354000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  69541354000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     40170500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 116136295000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     40170500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 116136295000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3682716                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3682716                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks           10                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total           10                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889827                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      1889827                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          675                       # number of ReadCleanReq accesses(hits+misses)
@@ -366,26 +372,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.414024
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.414024                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161814                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161814                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161815                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.161815                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.214119                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.214177                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.214119                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.214177                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.015337                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.015337                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52523.703704                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52523.703704                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.022246                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.022246                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52523.703704                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.019475                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52500.027666                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52523.703704                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.019475                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52500.027666                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -394,60 +400,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1022288                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1022288                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          218                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          218                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.writebacks::writebacks      1022289                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1022289                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          212                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          212                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782433                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       782433                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          675                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total          675                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1168761                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1168761                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1168762                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1168762                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1951194                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1951869                       # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::total      1951870                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1951194                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1951869                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  33253414500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  33253414500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     28703500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     28703500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  49672368500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  49672368500                       # number of ReadSharedReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  82925783000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  82954486500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     28703500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  82925783000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  82954486500                       # number of overall MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  38730440500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     33420500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     33420500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  57853734000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  57853734000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     33420500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  96584174500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  96617595000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     33420500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  96584174500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  96617595000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.414024                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.414024                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161814                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161814                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161815                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.161815                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214119                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.214177                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214119                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.214177                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.015337                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.015337                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42523.703704                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42523.703704                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.022246                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.022246                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42523.703704                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.019475                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.027666                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests     18221943                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9108591                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -456,8 +462,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops         1002                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1002                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp       7223525                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      4705009                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6322744                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4705005                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           10                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6322745                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1889827                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1889827                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq          675                       # Transaction distribution
@@ -465,53 +472,53 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq      7222850
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1360                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27333935                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total          27335295                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        43200                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818905472                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          818948672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1919162                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     20141105                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000050                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.007053                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        43840                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    818905152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          818948992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1919169                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11032521                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000091                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.009530                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           20140103    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1002      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11031519     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1002      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       20141105                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12793692500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11032521                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12793697500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1012500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13669015500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1169436                       # Transaction distribution
-system.membus.trans_dist::Writeback           1022288                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1169437                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1022289                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           896090                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            782433                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           782433                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1169436                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5822116                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5822116                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5822116                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190346048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    190346048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190346048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq       1169437                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5822119                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      5822119                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5822119                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190346176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    190346176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190346176                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3870262                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3870249                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3870262    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3870249    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3870262                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          7959418124                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3870249                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          7959407000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         9759348624                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         9759350000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index 11356e644..8b18f9604 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.051911                       # Nu
 sim_ticks                                 51910606500                       # Number of ticks simulated
 final_tick                                51910606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 339215                       # Simulator instruction rate (inst/s)
-host_op_rate                                   339215                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              191602600                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303192                       # Number of bytes of host memory used
-host_seconds                                   270.93                       # Real time elapsed on the host
+host_inst_rate                                 362776                       # Simulator instruction rate (inst/s)
+host_op_rate                                   362776                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              204910533                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303308                       # Number of bytes of host memory used
+host_seconds                                   253.33                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895           27      2.76%     85.70% # By
 system.physmem.bytesPerActivate::896-1023           27      2.76%     88.46% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          113     11.54%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total            979                       # Bytes accessed per row activation
-system.physmem.totQLat                       35331250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 135062500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                       35329750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 135061000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     26595000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6642.46                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6642.18                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25392.46                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25392.18                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           6.56                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        6.56                       # Average system read bandwidth in MiByte/s
@@ -227,28 +227,28 @@ system.physmem_0.preEnergy                    1914000                       # En
 system.physmem_0.readEnergy                  19835400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             3390060960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             1735578180                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            29619604500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              34770500880                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.907929                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    49271576750                       # Time in different power states
+system.physmem_0.actBackEnergy             1735573905                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            29619608250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              34770500355                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.907919                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    49271583750                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      1733160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       898679500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       898672500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.physmem_1.actEnergy                    3848040                       # Energy for activate commands per rank (pJ)
 system.physmem_1.preEnergy                    2099625                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                  21216000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             3390060960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1825261695                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            29540934750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              34783421070                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.156857                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    49142723000                       # Time in different power states
+system.physmem_1.actBackEnergy             1825260840                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            29540935500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              34783420965                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.156855                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    49142724000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      1733160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1030068000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1030067000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                11441088                       # Number of BP lookups
 system.cpu.branchPred.condPredicted           8207826                       # Number of conditional branches predicted
@@ -305,12 +305,12 @@ system.cpu.ipc                               0.885205                       # IP
 system.cpu.tickCycles                       102104321                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                         1716892                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1447.424804                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          1447.424803                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            26573200                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          11916.233184                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1447.424804                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  1447.424803                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.353375                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.353375                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
@@ -340,12 +340,12 @@ system.cpu.dcache.overall_misses::cpu.data         3431                       #
 system.cpu.dcache.overall_misses::total          3431                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data     40212500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total     40212500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    214035000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    214035000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    254247500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    254247500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    254247500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    254247500                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    214034000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    214034000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    254246500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    254246500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    254246500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    254246500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     20075528                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     20075528                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
@@ -364,12 +364,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data     0.000129
 system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 74103.031186                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 74103.031186                       # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 74102.739726                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 74102.739726                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -398,12 +398,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data         2230
 system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     37107000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total     37107000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131707500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    131707500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    168814500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    168814500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    168814500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    168814500                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131706500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    131706500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    168813500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    168813500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    168813500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    168813500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000268                       # mshr miss rate for WriteReq accesses
@@ -414,20 +414,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13850                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1640.456656                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1640.456655                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            22937703                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15815                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           1450.376415                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1640.456656                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1640.456655                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.801004                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.801004                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1965                       # Occupied blocks per task id
@@ -483,6 +483,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks        13850                       # number of writebacks
+system.cpu.icache.writebacks::total             13850                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15816                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        15816                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        15816                       # number of demand (read+write) MSHR misses
@@ -509,13 +511,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890
 system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2477.794194                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         2477.794192                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              26614                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3666                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             7.259684                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks    17.781001                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2100.046720                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2100.046719                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.data   359.966473                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064088                       # Average percentage of cache occupancy
@@ -530,8 +532,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2505
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111877                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses           261827                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses          261827                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks          107                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          107                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        13850                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        13850                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12647                       # number of ReadCleanReq hits
@@ -556,20 +560,22 @@ system.cpu.l2cache.demand_misses::total          5319                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3168                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2151                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         5319                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    128817000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    128817000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    236600000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    236600000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    128816000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    128816000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    236598500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    236598500                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35817000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::total     35817000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    236600000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    164634000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    401234000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    236600000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    164634000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    401234000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.demand_miss_latency::cpu.inst    236598500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    164633000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    401231500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    236598500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    164633000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    401231500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          107                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          107                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        13850                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        13850                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1745                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15815                       # number of ReadCleanReq accesses(hits+misses)
@@ -594,18 +600,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.294763                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200316                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964574                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.294763                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74937.172775                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74937.172775                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74684.343434                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74684.343434                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222                       # average ReadSharedReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74684.343434                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76538.354254                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75434.104155                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74684.343434                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76538.354254                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75434.104155                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -626,18 +632,18 @@ system.cpu.l2cache.demand_mshr_misses::total         5319
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3168                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2151                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5319                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    111627000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    111627000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    204920000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    204920000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    111626000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    111626000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    204918500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    204918500                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31497000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31497000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    204920000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    143124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    348044000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    204920000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    143124000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    348044000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    204918500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    143123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    348041500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    204918500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    143123000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    348041500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985100                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for ReadCleanReq accesses
@@ -650,18 +656,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.294763
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.294763                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests        32052                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests        14007                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -670,8 +676,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp         16300                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        13900                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          107                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        13850                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq        15815                       # Transaction distribution
@@ -679,23 +686,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq          485
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45480                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4617                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total             50097                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1012160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1898560                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1161728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            2048128                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        32052                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        18045                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              32052    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              18045    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          32052                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       16133000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.snoop_fanout::total          18045                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       29983000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      23722500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3345000                       # Layer occupancy (ticks)
@@ -719,9 +726,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                5319                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6413000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6412500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           28165750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           28165250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index cc5b93144..fdd161331 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.021919                       # Number of seconds simulated
-sim_ticks                                 21919473500                       # Number of ticks simulated
-final_tick                                21919473500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.021917                       # Number of seconds simulated
+sim_ticks                                 21916940500                       # Number of ticks simulated
+final_tick                                21916940500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 199769                       # Simulator instruction rate (inst/s)
-host_op_rate                                   199769                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52017673                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302932                       # Number of bytes of host memory used
-host_seconds                                   421.39                       # Real time elapsed on the host
+host_inst_rate                                 209109                       # Simulator instruction rate (inst/s)
+host_op_rate                                   209109                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54443336                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303052                       # Number of bytes of host memory used
+host_seconds                                   402.56                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            195776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            195712                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            138496                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               334272                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       195776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          195776                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3059                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               334208                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       195712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          195712                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3058                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5223                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8931601                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6318400                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15250001                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8931601                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8931601                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8931601                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6318400                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               15250001                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5223                       # Number of read requests accepted
+system.physmem.num_reads::total                  5222                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8929714                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6319130                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15248844                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8929714                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8929714                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8929714                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6319130                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15248844                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5222                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5223                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5222                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   334272                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   334208                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    334272                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    334208                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -50,7 +50,7 @@ system.physmem.perBankRdBursts::5                 223                       # Pe
 system.physmem.perBankRdBursts::6                 218                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 288                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 239                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 277                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                249                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                251                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                396                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     21919378500                       # Total gap between requests
+system.physmem.totGap                     21916845500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5223                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5222                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3272                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1189                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       507                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3268                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1190                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       509                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                       237                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          860                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      387.497674                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     231.928894                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     358.454487                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            254     29.53%     29.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          187     21.74%     51.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           83      9.65%     60.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           58      6.74%     67.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           36      4.19%     71.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           34      3.95%     75.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           40      4.65%     80.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           50      5.81%     86.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          118     13.72%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            860                       # Bytes accessed per row activation
-system.physmem.totQLat                       44538500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 142469750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26115000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8527.38                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          859                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      386.235157                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     231.364931                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     358.000658                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            253     29.45%     29.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          187     21.77%     51.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           82      9.55%     60.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           62      7.22%     67.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           35      4.07%     72.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           38      4.42%     76.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           35      4.07%     80.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           43      5.01%     85.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          124     14.44%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            859                       # Bytes accessed per row activation
+system.physmem.totQLat                       43137250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 141049750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26110000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8260.68                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27277.38                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27010.68                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          15.25                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       15.25                       # Average system read bandwidth in MiByte/s
@@ -216,70 +216,70 @@ system.physmem.busUtilRead                       0.12                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4358                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4353                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.44                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.36                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4196702.76                       # Average gap between requests
-system.physmem.pageHitRate                      83.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3160080                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1724250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19741800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      4197021.35                       # Average gap between requests
+system.physmem.pageHitRate                      83.36                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3122280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1703625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19461000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1431596400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy              935708580                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            12330335250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              14722266360                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.680556                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    20510216250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       731900000                       # Time in different power states
+system.physmem_0.refreshEnergy             1431087840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              912284145                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            12346211250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              14713870140                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.536045                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    20536521000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       731640000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       676644750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       642620250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3341520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1823250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  20872800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3311280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1806750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20748000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1431596400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy              913464900                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            12349847250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              14720946120                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.620322                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    20542312250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       731900000                       # Time in different power states
+system.physmem_1.refreshEnergy             1431087840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              917766405                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            12341402250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              14716122525                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.638843                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    20529652250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       731640000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       644355250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       650829750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16112018                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11701868                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            926184                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8628002                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7529875                       # Number of BTB hits
+system.cpu.branchPred.lookups                16111441                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11701383                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            926235                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8627871                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7529688                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.272523                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1595504                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                407                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             87.271680                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1595490                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                408                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     24062707                       # DTB read hits
-system.cpu.dtb.read_misses                     205786                       # DTB read misses
+system.cpu.dtb.read_hits                     24061115                       # DTB read hits
+system.cpu.dtb.read_misses                     205797                       # DTB read misses
 system.cpu.dtb.read_acv                             2                       # DTB read access violations
-system.cpu.dtb.read_accesses                 24268493                       # DTB read accesses
-system.cpu.dtb.write_hits                     7162407                       # DTB write hits
-system.cpu.dtb.write_misses                      1203                       # DTB write misses
+system.cpu.dtb.read_accesses                 24266912                       # DTB read accesses
+system.cpu.dtb.write_hits                     7162299                       # DTB write hits
+system.cpu.dtb.write_misses                      1202                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7163610                       # DTB write accesses
-system.cpu.dtb.data_hits                     31225114                       # DTB hits
-system.cpu.dtb.data_misses                     206989                       # DTB misses
+system.cpu.dtb.write_accesses                 7163501                       # DTB write accesses
+system.cpu.dtb.data_hits                     31223414                       # DTB hits
+system.cpu.dtb.data_misses                     206999                       # DTB misses
 system.cpu.dtb.data_acv                             2                       # DTB access violations
-system.cpu.dtb.data_accesses                 31432103                       # DTB accesses
-system.cpu.itb.fetch_hits                    15925407                       # ITB hits
+system.cpu.dtb.data_accesses                 31430413                       # DTB accesses
+system.cpu.itb.fetch_hits                    15924997                       # ITB hits
 system.cpu.itb.fetch_misses                        77                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                15925484                       # ITB accesses
+system.cpu.itb.fetch_accesses                15925074                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,139 +293,139 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         43838948                       # number of cpu cycles simulated
+system.cpu.numCycles                         43833882                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           16632320                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      137954260                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16112018                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9125379                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      25989721                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1930958                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles           16631894                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      137948476                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16111441                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9125178                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      25988337                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1931044                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  165                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          2266                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  15925407                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                365179                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           43589931                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.164819                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.433135                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  15924997                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                365277                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           43588192                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.164813                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.433150                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 19407451     44.52%     44.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2621129      6.01%     50.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1337584      3.07%     53.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1925835      4.42%     58.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3007413      6.90%     64.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1288266      2.96%     67.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1362128      3.12%     71.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   884292      2.03%     73.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 11755833     26.97%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 19406935     44.52%     44.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2620914      6.01%     50.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1337526      3.07%     53.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1925752      4.42%     58.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3007087      6.90%     64.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1288201      2.96%     67.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1362015      3.12%     71.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   884285      2.03%     73.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11755477     26.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43589931                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.367527                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.146842                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 12848398                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8248987                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19437203                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2101434                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 953909                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2651089                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 11974                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              132128383                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 49953                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 953909                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13970899                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4649700                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          10898                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20300581                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3703944                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              128750721                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 69632                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2039237                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1388591                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  55010                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            94550726                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             167277672                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        159796203                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7481468                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43588192                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.367557                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.147074                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 12849243                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               8247037                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19437084                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2100878                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 953950                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2651003                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11975                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              132120831                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 49966                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 953950                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13971462                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4650933                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          10896                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20300187                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3700764                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              128743195                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 69669                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2038779                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1385854                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  54667                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            94545107                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             167268798                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        159787749                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7481048                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 26123365                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                949                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            946                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8314647                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26912240                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8709829                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3514186                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1623457                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  111857121                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1283                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  99743085                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            115820                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        27678694                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     21106490                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            894                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43589931                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.288214                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.099779                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 26117746                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                950                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            948                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8310352                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26910154                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8709135                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3511293                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1618997                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  111850389                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1284                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  99739394                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            116060                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        27671963                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     21101257                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            895                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43588192                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.288220                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.099837                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            11253194     25.82%     25.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             7641118     17.53%     43.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7479948     17.16%     60.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5719610     13.12%     73.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4459621     10.23%     83.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2975044      6.83%     90.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2026173      4.65%     95.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1169285      2.68%     98.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              865938      1.99%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11252596     25.82%     25.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7641941     17.53%     43.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7479961     17.16%     60.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5717065     13.12%     73.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4459781     10.23%     83.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2974994      6.83%     90.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2026656      4.65%     95.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1169278      2.68%     98.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              865920      1.99%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43589931                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43588192                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  482162     20.24%     20.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  482625     20.24%     20.24% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     20.24% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   537      0.02%     20.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   536      0.02%     20.26% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                 34275      1.44%     21.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                12320      0.52%     22.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1010506     42.41%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 685066     28.75%     93.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                157661      6.62%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 34267      1.44%     21.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                12315      0.52%     22.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1010469     42.37%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 686537     28.79%     93.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                158059      6.63%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              60678292     60.83%     60.83% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               490564      0.49%     61.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60676588     60.84%     60.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               490565      0.49%     61.33% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2838989      2.85%     64.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115355      0.12%     64.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2438911      2.45%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             313691      0.31%     67.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              766049      0.77%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2839004      2.85%     64.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115354      0.12%     64.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2438838      2.45%     66.73% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             313701      0.31%     67.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              766055      0.77%     67.82% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.82% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
@@ -447,84 +447,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.82% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24838081     24.90%     92.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7262827      7.28%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24836317     24.90%     92.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7262646      7.28%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               99743085                       # Type of FU issued
-system.cpu.iq.rate                           2.275216                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2382527                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023887                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          229948900                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         130065304                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     89786778                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15625548                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9512793                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7169302                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               93776538                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 8349067                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1917366                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               99739394                       # Type of FU issued
+system.cpu.iq.rate                           2.275395                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2384808                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023910                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          229942315                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         130052988                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     89783673                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15625533                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9511643                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7169331                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               93775141                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8349054                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1917494                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6916042                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11056                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        41363                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2208726                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6913956                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11070                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        41356                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2208032                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        42784                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1527                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        42783                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1512                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 953909                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3616734                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                464700                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           122788755                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            239982                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26912240                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8709829                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1283                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  38454                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                420547                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          41363                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         525246                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       502956                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1028202                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              98432500                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24268972                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1310585                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 953950                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3617044                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                465078                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           122781228                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            240022                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              26910154                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8709135                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1284                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  38486                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                420890                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          41356                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         525280                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       502970                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1028250                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              98428862                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24267391                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1310532                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10930351                       # number of nop insts executed
-system.cpu.iew.exec_refs                     31432616                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12487704                       # Number of branches executed
-system.cpu.iew.exec_stores                    7163644                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.245321                       # Inst execution rate
-system.cpu.iew.wb_sent                       97645732                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      96956080                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  66985594                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95002941                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      10929555                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31430926                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12487406                       # Number of branches executed
+system.cpu.iew.exec_stores                    7163535                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.245497                       # Inst execution rate
+system.cpu.iew.wb_sent                       97642114                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      96953004                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  66984387                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95000699                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.211642                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.705090                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.211828                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.705094                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        30887581                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        30880053                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            914614                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     39095972                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.350704                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.921132                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            914663                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     39095166                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.350752                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.921213                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     14698430     37.60%     37.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8547015     21.86%     59.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3864183      9.88%     69.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1929221      4.93%     74.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1372371      3.51%     77.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1004316      2.57%     80.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       690404      1.77%     82.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       733733      1.88%     84.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6256299     16.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     14698751     37.60%     37.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8546224     21.86%     59.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3864207      9.88%     69.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1928510      4.93%     74.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1372257      3.51%     77.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1004424      2.57%     80.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       690640      1.77%     82.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       733325      1.88%     84.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6256828     16.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     39095972                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     39095166                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -570,118 +570,118 @@ system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6256299                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    155629269                       # The number of ROB reads
-system.cpu.rob.rob_writes                   250130763                       # The number of ROB writes
-system.cpu.timesIdled                            4629                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          249017                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6256828                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    155620406                       # The number of ROB reads
+system.cpu.rob.rob_writes                   250114778                       # The number of ROB writes
+system.cpu.timesIdled                            4635                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          245690                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.520778                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.520778                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.920204                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.920204                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                132982273                       # number of integer regfile reads
-system.cpu.int_regfile_writes                72919705                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6252521                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6155462                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  719143                       # number of misc regfile reads
+system.cpu.cpi                               0.520718                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.520718                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.920426                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.920426                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                132978272                       # number of integer regfile reads
+system.cpu.int_regfile_writes                72916434                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6252591                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6155476                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  719142                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements               158                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1457.350779                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28592916                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1457.328310                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28591208                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2244                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12741.941176                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12741.180036                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1457.350779                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.355799                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.355799                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1457.328310                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355793                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355793                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2086                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1389                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.509277                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          57207152                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         57207152                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22099846                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22099846                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492613                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492613                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          57203742                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         57203742                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22098137                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22098137                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492614                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492614                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data          457                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total          457                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28592459                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28592459                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28592459                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28592459                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1047                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1047                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8490                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8490                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      28590751                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28590751                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28590751                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28590751                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1051                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1051                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8489                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8489                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9537                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9537                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9537                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9537                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     69532500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     69532500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    543709251                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    543709251                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9540                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9540                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9540                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9540                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     72374000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     72374000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    544060252                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    544060252                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        85000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        85000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    613241751                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    613241751                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    613241751                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    613241751                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22100893                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22100893                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    616434252                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    616434252                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    616434252                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    616434252                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22099188                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22099188                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data          458                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total          458                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28601996                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28601996                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28601996                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28601996                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000047                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000047                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     28600291                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28600291                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28600291                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28600291                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000048                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001306                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001306                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002183                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002183                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000333                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000333                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000333                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000333                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66411.174785                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66411.174785                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64041.136749                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64041.136749                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000334                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000334                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000334                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000334                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68862.036156                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68862.036156                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64090.028507                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64090.028507                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64301.326518                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64301.326518                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64301.326518                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64301.326518                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        32746                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64615.749686                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64615.749686                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64615.749686                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64615.749686                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32998                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          127                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               389                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               378                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    84.179949                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    87.296296                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    63.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
 system.cpu.dcache.writebacks::total               108                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          540                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6754                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6754                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7294                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7294                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7294                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7294                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          544                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          544                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6753                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6753                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7297                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7297                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7297                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7297                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          507                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          507                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1736                       # number of WriteReq MSHR misses
@@ -692,16 +692,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2243
 system.cpu.dcache.demand_mshr_misses::total         2243                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2243                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2243                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39700000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     39700000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    135151495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    135151495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     40562000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     40562000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    135653495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    135653495                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        84000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        84000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    174851495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    174851495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    174851495                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    174851495                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    176215495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    176215495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    176215495                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    176215495                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
@@ -712,134 +712,138 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78303.747535                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78303.747535                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77852.243664                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77852.243664                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80003.944773                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80003.944773                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78141.414171                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78141.414171                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        84000                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        84000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77954.300045                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77954.300045                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77954.300045                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77954.300045                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78562.414177                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78562.414177                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78562.414177                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78562.414177                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              9477                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1601.339074                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            15910864                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11414                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1393.977922                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              9476                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1601.325936                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            15910465                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11413                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1394.065101                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1601.339074                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.781904                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.781904                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1601.325936                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.781897                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.781897                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          752                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          944                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          31862226                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         31862226                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     15910864                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        15910864                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      15910864                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         15910864                       # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total        15910864                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14542                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14542                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14542                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14542                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14542                       # number of overall misses
-system.cpu.icache.overall_misses::total         14542                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    447928500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    447928500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    447928500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    447928500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    447928500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    447928500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     15925406                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     15925406                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     15925406                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     15925406                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     15925406                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     15925406                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000913                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000913                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000913                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000913                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000913                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000913                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30802.399945                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 30802.399945                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 30802.399945                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 30802.399945                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 30802.399945                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 30802.399945                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          837                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          31861405                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         31861405                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     15910465                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        15910465                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        15910465                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14531                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total          14531                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        14531                       # number of overall misses
+system.cpu.icache.overall_misses::total         14531                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    444593500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    444593500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    444593500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    444593500                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total    444593500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     15924996                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     15924996                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     15924996                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     15924996                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     15924996                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000912                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000912                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000912                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000912                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000912                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000912                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30596.208107                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 30596.208107                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 30596.208107                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 30596.208107                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30596.208107                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 30596.208107                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          865                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs   209.250000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   216.250000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3128                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3128                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3128                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3128                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3128                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3128                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11414                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11414                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11414                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11414                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        11414                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        11414                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    338490500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    338490500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    338490500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    338490500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    338490500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    338490500                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         9476                       # number of writebacks
+system.cpu.icache.writebacks::total              9476                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3118                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3118                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3118                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst         3118                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3118                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11413                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        11413                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        11413                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::cpu.inst        11413                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        11413                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    335979500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    335979500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    335979500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    335979500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    335979500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    335979500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000717                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000717                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000717                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29655.729806                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 29655.729806                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29655.729806                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 29655.729806                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29438.315955                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 29438.315955                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 29438.315955                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2397.609271                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              17951                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3579                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             5.015647                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2397.525400                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              17950                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3578                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             5.016769                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.690606                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2004.677718                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   375.240947                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.688826                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2004.597838                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   375.238736                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061178                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061175                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.011451                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.073169                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3579                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          908                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total     0.073167                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3578                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          907                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2421                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109222                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           191659                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          191659                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks          108                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          108                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109192                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           191642                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          191642                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks          108                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          108                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         9476                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         9476                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8355                       # number of ReadCleanReq hits
@@ -854,66 +858,68 @@ system.cpu.l2cache.overall_hits::cpu.data           80                       # n
 system.cpu.l2cache.overall_hits::total           8435                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1710                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1710                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3059                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3059                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3058                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3058                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          454                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          454                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3059                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         3058                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         2164                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5223                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3059                       # number of overall misses
+system.cpu.l2cache.demand_misses::total          5222                       # number of demand (read+write) misses
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 system.cpu.l2cache.overall_misses::cpu.data         2164                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5223                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    132132500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    132132500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    233633500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    233633500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     38438500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     38438500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    233633500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    170571000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    404204500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    233633500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    170571000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    404204500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks          108                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          108                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.overall_misses::total         5222                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    132634500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    132634500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    230850500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    230850500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     39300500                       # number of ReadSharedReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.inst    230850500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    171935000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    402785500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    230850500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    171935000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    402785500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          108                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          108                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         9476                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         9476                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1736                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1736                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11414                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        11414                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11413                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        11413                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          508                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          508                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        11414                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        11413                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         2244                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        13658                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        11414                       # number of overall (read+write) accesses
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 system.cpu.l2cache.overall_accesses::cpu.data         2244                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        13658                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        13657                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985023                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.985023                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.268004                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.268004                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.267940                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.267940                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.893701                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.893701                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.268004                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.267940                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.964349                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.382413                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.268004                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.382368                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.267940                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964349                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.382413                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77270.467836                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77270.467836                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76375.776398                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76375.776398                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84666.299559                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84666.299559                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76375.776398                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78822.088725                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77389.335631                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76375.776398                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78822.088725                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77389.335631                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.382368                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77564.035088                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77564.035088                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75490.680183                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75490.680183                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86564.977974                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86564.977974                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75490.680183                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79452.402957                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77132.420529                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75490.680183                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79452.402957                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77132.420529                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -924,112 +930,113 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1710                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1710                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3059                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3059                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3058                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3058                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          454                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          454                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3059                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3058                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         2164                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5223                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3059                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5222                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3058                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2164                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5223                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115032500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115032500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    203043500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    203043500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33898500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33898500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    203043500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    148931000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    351974500                       # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    148931000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    351974500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total         5222                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115534500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115534500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    200270500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    200270500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     34760500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     34760500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200270500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    150295000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    350565500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200270500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    150295000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    350565500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985023                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985023                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.268004                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.267940                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.893701                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.893701                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.382413                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.268004                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.382368                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.382413                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67270.467836                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67270.467836                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66375.776398                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74666.299559                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74666.299559                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68822.088725                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67389.335631                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.382368                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67564.035088                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67564.035088                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.680183                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76564.977974                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76564.977974                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69452.402957                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67132.420529                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69452.402957                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67132.420529                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        23293                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         9635                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        23291                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         9634                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         11922                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          108                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         9527                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         11921                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          108                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         9476                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1736                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1736                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        11414                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        11413                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          508                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32305                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32302                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4646                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             36951                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       730496                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             36948                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1336896                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             881024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1487424                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        23293                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        13657                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              23293    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              13657    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          23293                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       11754500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          13657                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       21229500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17121000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      17119500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3366000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3513                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3512                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1710                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1710                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3513                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10446                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10446                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334272                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  334272                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          3512                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10444                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10444                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  334208                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5223                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5222                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5223    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5222    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5223                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6235500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5222                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6271000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           27428750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           27427000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index 13ae4452a..717d8e764 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.130773                       # Nu
 sim_ticks                                130772642500                       # Number of ticks simulated
 final_tick                               130772642500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 233615                       # Simulator instruction rate (inst/s)
-host_op_rate                                   246267                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              177290947                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 321196                       # Number of bytes of host memory used
-host_seconds                                   737.62                       # Real time elapsed on the host
+host_inst_rate                                 246902                       # Simulator instruction rate (inst/s)
+host_op_rate                                   260275                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              187375043                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321308                       # Number of bytes of host memory used
+host_seconds                                   697.92                       # Real time elapsed on the host
 sim_insts                                   172317810                       # Number of instructions simulated
 sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -591,6 +591,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.writebacks::writebacks         2888                       # number of writebacks
+system.cpu.icache.writebacks::total              2888                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4685                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         4685                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         4685                       # number of demand (read+write) MSHR misses
@@ -638,8 +640,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2004
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.084961                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses            76658                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses           76658                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks           16                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total           16                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         2566                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         2566                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2524                       # number of ReadCleanReq hits
@@ -676,8 +680,10 @@ system.cpu.l2cache.demand_miss_latency::total    294557500
 system.cpu.l2cache.overall_miss_latency::cpu.inst    161329500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data    133228000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total    294557500                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks           16                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total           16                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         2566                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         2566                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1098                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4685                       # number of ReadCleanReq accesses(hits+misses)
@@ -788,8 +794,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       #
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp          5396                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         2586                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         2566                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           20                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq         4685                       # Transaction distribution
@@ -797,22 +804,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq          712
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11935                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3656                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count::total             15591                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       299776                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       464000                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             416640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             580864                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         9425                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.083820                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.277132                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         6495                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.071132                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.257064                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               8635     91.62%     91.62% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                790      8.38%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               6033     92.89%     92.89% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                462      7.11%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9425                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        4728500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           6495                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7616500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       7026998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 7a60aaca0..ce097fad9 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,66 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.085039                       # Number of seconds simulated
-sim_ticks                                 85038866000                       # Number of ticks simulated
-final_tick                                85038866000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.085490                       # Number of seconds simulated
+sim_ticks                                 85490431000                       # Number of ticks simulated
+final_tick                                85490431000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 124768                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131526                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61578459                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 316956                       # Number of bytes of host memory used
-host_seconds                                  1380.98                       # Real time elapsed on the host
+host_inst_rate                                 129805                       # Simulator instruction rate (inst/s)
+host_op_rate                                   136836                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               64404554                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317332                       # Number of bytes of host memory used
+host_seconds                                  1327.40                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            127040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             47872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher        71424                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               246336                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       127040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          127040                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               1985                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                748                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         1116                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3849                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1493905                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               562943                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher       839898                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2896746                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1493905                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1493905                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1493905                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              562943                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher       839898                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2896746                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3849                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            587136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            132032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher        70784                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               789952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       587136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          587136                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               9174                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2063                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         1106                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 12343                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              6867856                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1544407                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher       827976                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 9240239                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         6867856                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            6867856                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             6867856                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1544407                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher       827976                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                9240239                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         12344                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3849                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       12344                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   246336                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   790016                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    246336                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    790016                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 309                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 223                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 134                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 318                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 300                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 302                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 262                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 237                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 252                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 219                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                292                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                194                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                191                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                211                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                211                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                194                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1112                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 371                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5091                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 435                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1954                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 426                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 266                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 369                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 265                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 221                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                323                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                197                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                249                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                227                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                543                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     85038722500                       # Total gap between requests
+system.physmem.totGap                     85490422000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3849                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   12344                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,15 +94,15 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      2529                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       872                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        88                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        40                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     10928                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       977                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       172                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        29                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
@@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          773                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      316.357050                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     198.451466                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     308.377497                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            239     30.92%     30.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          194     25.10%     56.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           84     10.87%     66.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           87     11.25%     78.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           29      3.75%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           37      4.79%     86.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           16      2.07%     88.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           13      1.68%     90.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           74      9.57%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            773                       # Bytes accessed per row activation
-system.physmem.totQLat                       41463141                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 113631891                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     19245000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10772.45                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         7242                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      108.822977                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      85.142878                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     132.567115                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           5271     72.78%     72.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         1523     21.03%     93.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          185      2.55%     96.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           87      1.20%     97.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           38      0.52%     98.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           26      0.36%     98.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           17      0.23%     98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           18      0.25%     98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           77      1.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           7242                       # Bytes accessed per row activation
+system.physmem.totQLat                      167084529                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 398534529                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     61720000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13535.69                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29522.45                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.90                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32285.69                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           9.24                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.90                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        9.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.07                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         2.83                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       3069                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5095                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.73                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   41.28                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22093718.50                       # Average gap between requests
-system.physmem.pageHitRate                      79.73                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    2789640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1522125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16239600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      6925666.07                       # Average gap between requests
+system.physmem.pageHitRate                      41.28                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   48527640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   26478375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  78156000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5553983760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2338576335                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            48968955000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              56882066460                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.934025                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    81466129254                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2839460000                       # Time in different power states
+system.physmem_0.refreshEnergy             5583480240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            17009559810                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            36370632750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              59116834815                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              691.542258                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    60400646468                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2854540000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       731738246                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     22233687032                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3031560                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1654125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13525200                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    6199200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3382500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  17869800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5553983760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2304071955                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            48999213750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              56875480350                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.856680                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    81513506905                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2839460000                       # Time in different power states
+system.physmem_1.refreshEnergy             5583480240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3325437855                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            48374248500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              57310618095                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.413332                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    80466021414                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2854540000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       681039595                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2165082586                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                85929659                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          68408036                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6017804                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             40110757                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                39021888                       # Number of BTB hits
+system.cpu.branchPred.lookups                85927149                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          68408695                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6018080                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             40104766                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                39018080                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.285344                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 3703815                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              81895                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.290382                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3702096                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              81897                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,96 +381,96 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        170077733                       # number of cpu cycles simulated
+system.cpu.numCycles                        170980863                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5627528                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      349301730                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85929659                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           42725703                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     158283885                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                12049307                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1743                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            5755157                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      349305240                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85927149                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42720176                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     158448180                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                12049937                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2618                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         2380                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  78962015                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 18924                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          169940212                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.150377                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.047263                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3916                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  78960236                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 19348                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          170234862                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.146650                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.050166                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 17375065     10.22%     10.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30210489     17.78%     28.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 31838895     18.74%     46.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 90515763     53.26%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 17669518     10.38%     10.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30211265     17.75%     28.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31838913     18.70%     46.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 90515166     53.17%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            169940212                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.505238                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.053777                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17579546                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              17112098                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 122676977                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6721861                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5849730                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             11135516                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                190121                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              306633664                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              27649172                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5849730                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37767470                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8469466                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         579515                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 108936835                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8337196                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              278676031                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13415385                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3051308                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 841767                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2187025                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  37328                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            26465                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           483141060                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1197017326                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        297598208                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3006154                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            170234862                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.502554                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.042949                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17700032                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              17289472                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 122672401                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6722857                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5850100                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11135652                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                190021                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              306632940                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              27644957                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5850100                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37887834                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8551246                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         582035                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 108933106                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8430541                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              278671233                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13418761                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3051568                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 841704                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2280860                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  35921                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            27095                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           483139430                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1196998780                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        297599206                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3005965                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                190164131                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              23534                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          23437                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13334158                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             34140467                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            14476937                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2547302                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1809047                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  264833552                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               45866                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 214914716                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5193890                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        83243464                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    219964835                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            650                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     169940212                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.264649                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.017441                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                190162501                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              23526                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          23429                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13338905                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             34139598                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14476816                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2548575                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1784456                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  264827834                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               45856                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 214914585                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5192491                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        83237736                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    219939522                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            640                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     170234862                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.262459                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.017804                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            52857789     31.10%     31.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            36101949     21.24%     52.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            65794996     38.72%     91.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            13566772      7.98%     99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1571259      0.92%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               47259      0.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 188      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            53140673     31.22%     31.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            36118420     21.22%     52.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            65796647     38.65%     91.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            13561298      7.97%     99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1570362      0.92%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               47243      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 219      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       169940212                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       170234862                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                35605031     66.12%     66.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 152953      0.28%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                35603971     66.12%     66.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 152944      0.28%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.40% # attempts to use FU when none available
@@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.40% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd              1062      0.00%     66.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd              1066      0.00%     66.40% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp             35733      0.07%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               238      0.00%     66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp             35746      0.07%     66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               240      0.00%     66.47% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc             1040      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult            34389      0.06%     66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               14077055     26.14%     92.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3945216      7.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              952      0.00%     66.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult            34296      0.06%     66.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               14072260     26.13%     92.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3948482      7.33%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             167357469     77.87%     77.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               918949      0.43%     78.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             167357330     77.87%     77.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               918980      0.43%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.30% # Type of FU issued
@@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.30% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.30% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33022      0.02%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33017      0.02%     78.31% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          165195      0.08%     78.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          245712      0.11%     78.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          165190      0.08%     78.39% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          245699      0.11%     78.51% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         460561      0.21%     78.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206706      0.10%     78.85% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         460522      0.21%     78.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206694      0.10%     78.85% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.88% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             32005826     14.89%     93.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13373316      6.22%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             32005177     14.89%     93.78% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13374016      6.22%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              214914716                       # Type of FU issued
-system.cpu.iq.rate                           1.263626                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    53852922                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.250578                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          654863168                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         346117768                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    204606131                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3953288                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2011882                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1806358                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266633604                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2134034                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1600995                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              214914585                       # Type of FU issued
+system.cpu.iq.rate                           1.256951                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    53850162                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.250565                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          655153476                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         346106935                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    204606292                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3953209                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2011310                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1806290                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              266630626                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2134121                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1600828                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6244323                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7621                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         6899                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1832303                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6243454                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7546                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         6949                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1832182                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        25728                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           844                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        25935                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           794                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5849730                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5682254                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 37001                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           264895393                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                5850100                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5682962                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 61282                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           264889651                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              34140467                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             14476937                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              23458                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3889                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 29998                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           6899                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3234969                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3247770                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              6482739                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             207531016                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              30721231                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7383700                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              34139598                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14476816                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              23448                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3916                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 54251                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           6949                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3234598                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3248118                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6482716                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             207529725                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              30719767                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7384860                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         15975                       # number of nop insts executed
-system.cpu.iew.exec_refs                     43860800                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 44937472                       # Number of branches executed
-system.cpu.iew.exec_stores                   13139569                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.220213                       # Inst execution rate
-system.cpu.iew.wb_sent                      206747617                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     206412489                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 129477272                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 221702085                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         15961                       # number of nop insts executed
+system.cpu.iew.exec_refs                     43859608                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 44936158                       # Number of branches executed
+system.cpu.iew.exec_stores                   13139841                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.213760                       # Inst execution rate
+system.cpu.iew.wb_sent                      206746993                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     206412582                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 129474820                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 221691878                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.213636                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.584015                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.207226                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.584031                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        69549191                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        69543013                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           5842881                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158496522                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.146084                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.646497                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           5843212                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158791205                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.143957                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.645227                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     73710350     46.51%     46.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     41283484     26.05%     72.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     22554549     14.23%     86.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9626760      6.07%     92.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3551822      2.24%     95.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2145509      1.35%     96.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1280291      0.81%     97.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       989155      0.62%     97.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3354602      2.12%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     73988497     46.59%     46.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     41295308     26.01%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     22556711     14.21%     86.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9630949      6.07%     92.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3552216      2.24%     95.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2148211      1.35%     96.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1284578      0.81%     97.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       986502      0.62%     97.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3348233      2.11%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158496522                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    158791205                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
 system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -655,380 +655,382 @@ system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3354602                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    406336252                       # The number of ROB reads
-system.cpu.rob.rob_writes                   513856795                       # The number of ROB writes
-system.cpu.timesIdled                            3529                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          137521                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3348233                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    406631126                       # The number of ROB reads
+system.cpu.rob.rob_writes                   513844376                       # The number of ROB writes
+system.cpu.timesIdled                            8957                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          746001                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
 system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.987085                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.987085                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.013084                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.013084                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                218963852                       # number of integer regfile reads
-system.cpu.int_regfile_writes               114515225                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2904259                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2441612                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 709595430                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                229551730                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                59313283                       # number of misc regfile reads
+system.cpu.cpi                               0.992327                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.992327                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.007733                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.007733                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                218966975                       # number of integer regfile reads
+system.cpu.int_regfile_writes               114516229                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2904204                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2441504                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 709589080                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                229556340                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                59312089                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements             72876                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.418230                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            41115950                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs             73388                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            560.254401                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         506092500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.418230                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998864                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998864                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements             72854                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.416253                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            41114439                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs             73366                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            560.401807                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         507537500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.416253                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998860                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998860                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          225                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          231                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           42                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          82530918                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         82530918                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28729730                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28729730                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12341303                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12341303                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          82527906                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         82527906                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28728233                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28728233                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12341290                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12341290                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          361                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           361                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        22149                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22149                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        22148                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22148                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41071033                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41071033                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41071394                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41071394                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89456                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89456                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        22984                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        22984                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          116                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          116                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data      41069523                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41069523                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41069884                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41069884                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89457                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89457                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        22997                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        22997                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          118                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          118                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data          259                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total          259                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       112440                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         112440                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       112556                       # number of overall misses
-system.cpu.dcache.overall_misses::total        112556                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    857049000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    857049000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    246637999                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    246637999                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2309500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      2309500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1103686999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1103686999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1103686999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1103686999                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28819186                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28819186                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       112454                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         112454                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       112572                       # number of overall misses
+system.cpu.dcache.overall_misses::total        112572                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1065753500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1065753500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    241354499                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    241354499                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2315500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      2315500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1307107999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1307107999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1307107999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1307107999                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28817690                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28817690                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          477                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          477                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22408                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        22408                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          479                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          479                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41183473                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41183473                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41183950                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41183950                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     41181977                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41181977                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41182456                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41182456                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003104                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003104                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001859                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001859                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.243187                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.243187                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011558                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011558                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002730                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002730                       # miss rate for demand accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001860                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001860                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.246347                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.246347                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011559                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011559                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002731                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002731                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002733                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002733                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9580.676534                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9580.676534                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10730.856204                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10730.856204                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8916.988417                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8916.988417                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9815.786188                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9815.786188                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9805.670058                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9805.670058                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8940.154440                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8940.154440                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 11623.490485                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 11611.306533                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          166                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        11592                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        10450                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             859                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             866                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs           83                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    13.494761                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    12.066975                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        64866                       # number of writebacks
-system.cpu.dcache.writebacks::total             64866                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24759                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        24759                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14406                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        14406                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        72854                       # number of writebacks
+system.cpu.dcache.writebacks::total             72854                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24777                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        24777                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14426                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        14426                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          259                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total          259                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        39165                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        39165                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        39165                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        39165                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64697                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        64697                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8578                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         8578                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          113                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          113                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data        73275                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total        73275                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data        73388                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total        73388                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    560382500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    560382500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     86241499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     86241499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       962000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       962000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    646623999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    646623999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    647585999                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    647585999                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002245                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002245                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000694                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000694                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.236897                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.236897                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data        39203                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39203                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39203                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39203                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64680                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        64680                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8571                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         8571                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          115                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          115                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data        73251                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total        73251                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data        73366                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total        73366                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    654439000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    654439000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     86279999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     86279999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       978000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       978000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    740718999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    740718999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    741696999                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    741696999                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002244                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002244                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000693                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000693                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.240084                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.240084                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001779                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001779                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001782                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001782                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8661.645826                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8661.645826                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10053.800303                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10053.800303                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8513.274336                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8513.274336                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8824.619570                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8824.619570                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8824.140173                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8824.140173                       # average overall mshr miss latency
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001781                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.001781                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8504.347826                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8504.347826                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             54478                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.603674                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            78903878                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             54990                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1434.876850                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       84285313500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.603674                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997273                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997273                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             54401                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.602972                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            78901806                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             54913                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1436.851128                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       84733597500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.602972                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997271                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997271                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          106                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          272                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           48                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         157978976                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        157978976                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     78903878                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        78903878                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      78903878                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         78903878                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     78903878                       # number of overall hits
-system.cpu.icache.overall_hits::total        78903878                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        58115                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         58115                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        58115                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          58115                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        58115                       # number of overall misses
-system.cpu.icache.overall_misses::total         58115                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    612004953                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    612004953                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    612004953                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    612004953                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    612004953                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    612004953                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     78961993                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     78961993                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     78961993                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     78961993                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     78961993                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     78961993                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000736                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000736                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000736                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000736                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000736                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000736                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10530.929244                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10530.929244                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10530.929244                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10530.929244                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10530.929244                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10530.929244                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        59295                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         157975329                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        157975329                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     78901806                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        78901806                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      78901806                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         78901806                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     78901806                       # number of overall hits
+system.cpu.icache.overall_hits::total        78901806                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        58402                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         58402                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        58402                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          58402                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        58402                       # number of overall misses
+system.cpu.icache.overall_misses::total         58402                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1157058425                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1157058425                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1157058425                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1157058425                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1157058425                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1157058425                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     78960208                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     78960208                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     78960208                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     78960208                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     78960208                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     78960208                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000740                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000740                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000740                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000740                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000740                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000740                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19811.965772                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19811.965772                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        72401                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           27                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2885                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3397                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    20.552860                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.313218                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3125                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3125                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3125                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3125                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3125                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3125                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54990                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        54990                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        54990                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        54990                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        54990                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        54990                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    544384465                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    544384465                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    544384465                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    544384465                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    544384465                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    544384465                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000696                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000696                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000696                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000696                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9899.699309                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9899.699309                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9899.699309                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9899.699309                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9899.699309                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9899.699309                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        54401                       # number of writebacks
+system.cpu.icache.writebacks::total             54401                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3488                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3488                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3488                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3488                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3488                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3488                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54914                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        54914                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        54914                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        54914                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        54914                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        54914                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1043630451                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1043630451                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1043630451                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1043630451                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1043630451                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1043630451                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000695                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000695                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000695                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued         9181                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified         9181                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued         9281                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified         9281                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage         1371                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage         1359                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2666.904370                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             230419                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3586                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            64.255159                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2148.551192                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             159756                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3199                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            49.939356                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   701.956928                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1376.038958                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   419.067836                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   169.840648                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.042844                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.083987                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.025578                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.010366                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.162775                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          265                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3321                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           19                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           85                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          161                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          749                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2293                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.016174                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.202698                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3935898                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3935898                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks        64866                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        64866                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         8409                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         8409                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        52999                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        52999                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        64221                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        64221                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        52999                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        72630                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          125629                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        52999                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        72630                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         125629                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data          239                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          239                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1991                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1991                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          519                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          519                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1991                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          758                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          2749                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1991                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          758                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         2749                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     19008500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     19008500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    136250000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    136250000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     38006500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     38006500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    136250000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     57015000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    193265000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    136250000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     57015000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    193265000                       # number of overall miss cycles
-system.cpu.l2cache.Writeback_accesses::writebacks        64866                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        64866                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         8648                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         8648                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54990                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        54990                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64740                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        64740                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        54990                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data        73388                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       128378                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        54990                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data        73388                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       128378                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027636                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.027636                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.036207                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.036207                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.008017                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.008017                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.036207                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.010329                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.021413                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.036207                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.010329                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.021413                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79533.472803                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79533.472803                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68432.948267                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68432.948267                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73230.250482                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73230.250482                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68432.948267                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75217.678100                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70303.746817                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68432.948267                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75217.678100                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70303.746817                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks  1987.164357                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   161.386835                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.121287                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009850                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.131137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          254                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2945                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           83                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          193                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          854                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          163                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1654                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015503                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.179749                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3989175                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3989175                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks        64840                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total        64840                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        51941                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        51941                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         8403                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         8403                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        45734                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        45734                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        62891                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        62891                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        45734                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        71294                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          117028                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        45734                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        71294                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         117028                       # number of overall hits
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+system.cpu.l2cache.ReadExReq_misses::total          237                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9180                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         9180                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1835                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total         1835                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         9180                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2072                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         11252                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         9180                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2072                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        11252                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     19043000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     19043000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    687767000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    687767000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    141031000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total    141031000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    687767000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    160074000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    847841000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    687767000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    160074000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    847841000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        64840                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        64840                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        51941                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        51941                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         8640                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         8640                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54914                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        54914                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu.l2cache.ReadSharedReq_accesses::total        64726                       # number of ReadSharedReq accesses(hits+misses)
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+system.cpu.l2cache.demand_accesses::cpu.data        73366                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.data        73366                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       128280                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027431                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.027431                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.167170                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.167170                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.028350                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.028350                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.167170                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.028242                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.087714                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167170                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.028242                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.087714                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80350.210970                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80350.210970                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74920.152505                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74920.152505                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76856.130790                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76856.130790                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74920.152505                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77255.791506                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75350.248845                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74920.152505                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77255.791506                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75350.248845                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1037,139 +1039,140 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            2                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total            2                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            6                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            6                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         1765                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total         1765                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          237                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          237                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1985                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1985                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          511                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          511                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1985                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          748                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         2733                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1985                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          748                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         1765                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         4498                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     70524171                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     70524171                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     17163500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     17163500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    124005500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    124005500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     34486500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     34486500                       # number of ReadSharedReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     51650000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    175655500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    124005500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     51650000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     70524171                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    246179671                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
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+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         2046                       # number of HardPFReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          236                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::total        13284                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     66908651                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     66908651                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     17421000                       # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    632417000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    129587000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    129587000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    632417000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    147008000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    779425000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    632417000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    147008000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     66908651                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    846333651                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027405                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027405                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.036097                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.036097                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.007893                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.007893                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.036097                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.010192                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.021289                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.036097                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.010192                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027315                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027315                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.167079                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.167079                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.028227                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.028227                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.167079                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028119                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.087605                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167079                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028119                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.035037                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39957.037394                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72419.831224                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72419.831224                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62471.284635                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62471.284635                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67488.258317                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67488.258317                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62471.284635                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69050.802139                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64272.045371                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62471.284635                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69050.802139                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54730.918408                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.103555                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       255732                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       127373                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10503                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          649                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          649                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        119730                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        64866                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        51985                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq         2111                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         8648                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         8648                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        54990                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        64740                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       156105                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       217502                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            373607                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3519360                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8848256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           12367616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                        2111                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       257843                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.084059                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.277477                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests       255535                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       127274                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10474                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        11941                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3419                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         8522                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp        119639                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty        64840                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        51941                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        11001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq         2383                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         8640                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         8640                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        54914                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        64726                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       155926                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       217414                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            373340                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6464768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9219072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           15683840                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       13384                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       141664                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.218517                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.539520                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             236169     91.59%     91.59% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              21674      8.41%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             119230     84.16%     84.16% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              13912      9.82%     93.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2               8522      6.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         257843                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      192732000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      82511447                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total         141664                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      255022500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      82377983                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     110086990                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     110053990                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3612                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               237                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              237                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3612                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7698                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7698                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       246336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  246336                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              12107                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               236                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              236                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         12108                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        24687                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  24687                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       789952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  789952                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3849                       # Request fanout histogram
+system.membus.snoop_fanout::samples             12344                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3849    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   12344    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3849                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             5019167                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               12344                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            15598659                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20293808                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           66476550                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index fda8a8b37..5cd25481d 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.079190                       # Number of seconds simulated
-sim_ticks                                 79190347500                       # Number of ticks simulated
-final_tick                                79190347500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.079230                       # Number of seconds simulated
+sim_ticks                                 79229645000                       # Number of ticks simulated
+final_tick                                79229645000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91850                       # Simulator instruction rate (inst/s)
-host_op_rate                                   153949                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55073733                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 350132                       # Number of bytes of host memory used
-host_seconds                                  1437.90                       # Real time elapsed on the host
+host_inst_rate                                  90742                       # Simulator instruction rate (inst/s)
+host_op_rate                                   152092                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54436376                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 350016                       # Number of bytes of host memory used
+host_seconds                                  1455.45                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            220800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            220992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            124928                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               345920                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       220800                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          220800                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3450                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1955                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst       220992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          220992                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3453                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1952                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  5405                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2788219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1579991                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4368209                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2788219                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2788219                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2788219                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1579991                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4368209                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              2789259                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1576784                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4366043                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2789259                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2789259                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2789259                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1576784                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4366043                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          5405                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        5405                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -40,23 +40,23 @@ system.physmem.bytesReadSys                    345920                       # To
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            296                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 299                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 345                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 461                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            261                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 295                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 347                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 460                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 350                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 340                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 325                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 403                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 384                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 342                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 341                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 328                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 402                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 383                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 339                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 281                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                239                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                240                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                284                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                217                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                467                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                385                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                283                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                468                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                388                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                282                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     79190259000                       # Total gap between requests
+system.physmem.totGap                     79229612500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       898                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       174                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4295                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       899                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       178                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1097                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      314.107566                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     184.474477                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     326.278271                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            419     38.20%     38.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          241     21.97%     60.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           97      8.84%     69.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           63      5.74%     74.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           63      5.74%     80.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           54      4.92%     85.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           22      2.01%     87.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           17      1.55%     88.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          121     11.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1097                       # Bytes accessed per row activation
-system.physmem.totQLat                       39419500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 140763250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1099                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      313.361237                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     181.828976                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.670559                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            436     39.67%     39.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          230     20.93%     60.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           99      9.01%     69.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           58      5.28%     74.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           55      5.00%     79.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           56      5.10%     84.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           23      2.09%     87.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           18      1.64%     88.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          124     11.28%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1099                       # Bytes accessed per row activation
+system.physmem.totQLat                       41940250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 143284000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     27025000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7293.15                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7759.53                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26043.15                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26509.53                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           4.37                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        4.37                       # Average system read bandwidth in MiByte/s
@@ -214,285 +214,285 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4299                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4297                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.54                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.50                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14651296.76                       # Average gap between requests
-system.physmem.pageHitRate                      79.54                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    4883760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2664750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  22565400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     14658577.71                       # Average gap between requests
+system.physmem.pageHitRate                      79.50                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    4906440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2677125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  22526400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5172055200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2473079805                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            45342485250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              53017734165                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.530615                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    75427842500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2644200000                       # Time in different power states
+system.physmem_0.refreshEnergy             5174598000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2444474070                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            45390936750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              53040118785                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.484152                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    75508317500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2645500000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1114667500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1071550000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3402000                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1856250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  19305000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3386880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1848000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  19312800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5172055200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2272318965                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            45518583000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              52987520415                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.149179                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    75723788000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2644200000                       # Time in different power states
+system.physmem_1.refreshEnergy             5174598000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2297025045                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            45520269750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              53016440475                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.185395                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    75726888000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2645500000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       820354000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       855243500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                20589195                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20589195                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1327817                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12690862                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                12013274                       # Number of BTB hits
+system.cpu.branchPred.lookups                20592907                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          20592907                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1327799                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             12698364                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                12013605                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.660820                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1440361                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              16897                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.607502                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1441126                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              16761                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        158380696                       # number of cpu cycles simulated
+system.cpu.numCycles                        158459291                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           25245702                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      227408017                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    20589195                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           13453635                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     131309354                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3192879                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                         16                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 1952                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         21042                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           25251668                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      227436303                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    20592907                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13454731                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     131379126                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3193881                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                          1                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 2041                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         21671                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
 system.cpu.fetch.IcacheWaitRetryStallCycles           47                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  24254364                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                267325                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          158174565                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.377629                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.324169                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  24259483                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                266288                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          158251507                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.376692                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.323734                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 95855369     60.60%     60.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4772394      3.02%     63.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3794325      2.40%     66.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4370382      2.76%     68.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4226374      2.67%     71.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4818979      3.05%     74.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4692035      2.97%     77.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3702011      2.34%     79.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 31942696     20.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 95931722     60.62%     60.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4757646      3.01%     63.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3806394      2.41%     66.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4363208      2.76%     68.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4227713      2.67%     71.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4814821      3.04%     74.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4714702      2.98%     77.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3700525      2.34%     79.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 31934776     20.18%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            158174565                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.129998                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.435832                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 15399565                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              96291119                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  23261573                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              21625869                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1596439                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              336537122                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                1596439                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 23302832                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                31798352                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          30486                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  35975056                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              65471400                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              328175182                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1530                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               57810134                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7763747                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 166308                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           380366291                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             909731361                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        600445935                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           4186121                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            158251507                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.129957                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.435298                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15405673                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              96363491                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  23242332                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              21643071                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1596940                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              336546765                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                1596940                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 23300664                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                31883477                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          30445                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35976653                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              65463328                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              328193711                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1319                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               57856617                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7708627                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 165863                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           380358715                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             909771649                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        600461611                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           4182617                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                120936841                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1921                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1898                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 121141633                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             82738842                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            29779777                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          59550134                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         20391789                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  317761802                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                4069                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 259358612                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             72184                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        96402487                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    196983368                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2824                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     158174565                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.639699                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.523293                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                120929265                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2085                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2059                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 121166066                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             82747977                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            29791267                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          59612118                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         20405352                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  317780620                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4165                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 259339471                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             71881                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        96421401                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    197095861                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           2920                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     158251507                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.638780                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.522654                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            40029224     25.31%     25.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            47620381     30.11%     55.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            33114320     20.94%     76.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17999452     11.38%     87.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            10926984      6.91%     94.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4757371      3.01%     97.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2459469      1.55%     99.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              879282      0.56%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              388082      0.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            40084558     25.33%     25.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            47634072     30.10%     55.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            33122012     20.93%     76.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18013851     11.38%     87.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            10936157      6.91%     94.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4740478      3.00%     97.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2457312      1.55%     99.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              875604      0.55%     99.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              387463      0.24%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       158174565                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       158251507                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  231613      7.32%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2544922     80.40%     87.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                388680     12.28%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  234483      7.38%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2555698     80.47%     87.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                385880     12.15%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1213055      0.47%      0.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             161788642     62.38%     62.85% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               789415      0.30%     63.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7038152      2.71%     65.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1187589      0.46%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             64884960     25.02%     91.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            22456799      8.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1212784      0.47%      0.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             161792342     62.39%     62.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               789140      0.30%     63.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7038106      2.71%     65.87% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1186493      0.46%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             64866325     25.01%     91.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            22454281      8.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              259358612                       # Type of FU issued
-system.cpu.iq.rate                           1.637565                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3165215                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012204                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          675270057                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         410763185                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    253622616                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             4859131                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            3700913                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2341090                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              258863930                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2446842                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18717155                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              259339471                       # Type of FU issued
+system.cpu.iq.rate                           1.636632                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3176061                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012247                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          675323210                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         410805836                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    253605894                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             4855181                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            3696441                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2340510                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              258858304                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2444444                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18689568                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     26089255                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        12841                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       302099                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      9264060                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     26098390                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        12338                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       302582                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      9275550                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        50731                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            43                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        50123                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            39                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1596439                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                12482349                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                492760                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           317765871                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             91851                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              82738842                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             29779777                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1874                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 386744                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 63788                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         302099                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         551455                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       825732                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1377187                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             257295592                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              64068122                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2063020                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1596940                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                12493200                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                494306                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           317784785                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             94743                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              82747977                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             29791267                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1931                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 389039                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 63652                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         302582                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         551479                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       825731                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1377210                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             257282682                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              64058012                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2056789                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     86346654                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14327856                       # Number of branches executed
-system.cpu.iew.exec_stores                   22278532                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.624539                       # Inst execution rate
-system.cpu.iew.wb_sent                      256649039                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     255963706                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 204348842                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 369627181                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     86333641                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14326229                       # Number of branches executed
+system.cpu.iew.exec_stores                   22275629                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.623652                       # Inst execution rate
+system.cpu.iew.wb_sent                      256637538                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     255946404                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 204333247                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 369622334                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.616129                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.552851                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.615219                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.552816                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        96410316                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        96429188                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1329636                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    145035845                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.526267                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.955883                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1329692                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    145106129                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.525527                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.953873                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     45546155     31.40%     31.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57399506     39.58%     70.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     14176238      9.77%     80.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11993202      8.27%     89.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4061532      2.80%     91.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2861406      1.97%     93.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       912773      0.63%     94.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1078264      0.74%     95.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      7006769      4.83%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     45566766     31.40%     31.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     57414676     39.57%     70.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     14193363      9.78%     80.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12012309      8.28%     89.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4072580      2.81%     91.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2869750      1.98%     93.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       928162      0.64%     94.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1071171      0.74%     95.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6977352      4.81%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    145035845                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    145106129                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -538,339 +538,345 @@ system.cpu.commit.op_class_0::MemWrite       20515717      9.27%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               7006769                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    455802776                       # The number of ROB reads
-system.cpu.rob.rob_writes                   648723400                       # The number of ROB writes
-system.cpu.timesIdled                            2658                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          206131                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6977352                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    455921349                       # The number of ROB reads
+system.cpu.rob.rob_writes                   648768029                       # The number of ROB writes
+system.cpu.timesIdled                            2647                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          207784                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.199207                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.199207                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.833884                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.833884                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                448507967                       # number of integer regfile reads
-system.cpu.int_regfile_writes               232568909                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3215393                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  1999198                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 102530516                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 59523273                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               132435302                       # number of misc regfile reads
+system.cpu.cpi                               1.199802                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.199802                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.833471                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.833471                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                448461429                       # number of integer regfile reads
+system.cpu.int_regfile_writes               232562681                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3213153                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  1998427                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 102530427                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 59507422                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               132428508                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements                52                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1432.092422                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            65736813                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2001                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          32851.980510                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                51                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1429.692139                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            65755137                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1993                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          32993.044155                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1432.092422                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.349632                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.349632                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1949                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          500                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1429.692139                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.349046                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.349046                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1942                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1397                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.475830                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         131480483                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        131480483                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     45222500                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        45222500                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20513893                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20513893                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      65736393                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         65736393                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     65736393                       # number of overall hits
-system.cpu.dcache.overall_hits::total        65736393                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1010                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1010                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1838                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1838                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2848                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2848                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2848                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2848                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     65396000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     65396000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    129164500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    129164500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    194560500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    194560500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    194560500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    194560500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     45223510                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     45223510                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1395                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.474121                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         131517093                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        131517093                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     45240855                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        45240855                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20513928                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20513928                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      65754783                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         65754783                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     65754783                       # number of overall hits
+system.cpu.dcache.overall_hits::total        65754783                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          964                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           964                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1803                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1803                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2767                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2767                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2767                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2767                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     65032500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     65032500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    127862500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    127862500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    192895000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    192895000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    192895000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    192895000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     45241819                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     45241819                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     65739241                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     65739241                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     65739241                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     65739241                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000090                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000090                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 68314.782303                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 68314.782303                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          697                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     65757550                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     65757550                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     65757550                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     65757550                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000021                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000088                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000088                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000042                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000042                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67461.099585                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67461.099585                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70916.528009                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70916.528009                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 69712.685219                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69712.685219                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 69712.685219                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69712.685219                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          656                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets           70                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 7                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    87.125000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    93.714286                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets           70                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           10                       # number of writebacks
 system.cpu.dcache.writebacks::total                10                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          549                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          549                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          511                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          511                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          551                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          551                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          551                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          551                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          461                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          461                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1836                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1836                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2297                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2297                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2297                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2297                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36137000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36137000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    127182500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    127182500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    163319500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    163319500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    163319500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    163319500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data          513                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          513                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          513                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          513                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          453                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          453                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1801                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1801                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2254                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2254                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2254                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2254                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36207500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36207500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    125915500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    125915500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    162123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    162123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    162123000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    162123000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000035                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000035                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000034                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000034                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79928.256071                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79928.256071                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69914.214325                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69914.214325                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71926.796806                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71926.796806                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71926.796806                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71926.796806                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              4970                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1639.175035                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24244955                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6947                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3489.989204                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4974                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1637.723048                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            24250086                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6949                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3489.723126                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1639.175035                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.800378                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.800378                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1977                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          870                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          793                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.965332                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          48515969                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         48515969                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24244955                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24244955                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      24244955                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         24244955                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     24244955                       # number of overall hits
-system.cpu.icache.overall_hits::total        24244955                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         9408                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          9408                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         9408                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           9408                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         9408                       # number of overall misses
-system.cpu.icache.overall_misses::total          9408                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    407324999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    407324999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    407324999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    407324999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    407324999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    407324999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     24254363                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     24254363                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     24254363                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     24254363                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     24254363                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     24254363                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000388                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000388                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000388                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000388                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000388                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000388                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43295.599384                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 43295.599384                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 43295.599384                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 43295.599384                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 43295.599384                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 43295.599384                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          788                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1637.723048                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.799669                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.799669                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1975                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          187                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          867                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           20                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          792                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.964355                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          48526174                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         48526174                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     24250086                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        24250086                       # number of ReadReq hits
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+system.cpu.icache.overall_hits::total        24250086                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         9396                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          9396                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         9396                       # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::cpu.inst         9396                       # number of overall misses
+system.cpu.icache.overall_misses::total          9396                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    410761999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    410761999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    410761999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    410761999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    410761999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    410761999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     24259482                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     24259482                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total     24259482                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     24259482                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     24259482                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000387                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000387                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000387                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000387                       # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::total     0.000387                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43716.687846                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 43716.687846                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 43716.687846                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 43716.687846                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 43716.687846                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 43716.687846                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          900                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    65.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    69.230769                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2164                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2164                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2164                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2164                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2164                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2164                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7244                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7244                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7244                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7244                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7244                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7244                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    309481499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    309481499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    309481499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    309481499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    309481499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    309481499                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000299                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000299                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000299                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42722.459829                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42722.459829                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42722.459829                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 42722.459829                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42722.459829                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 42722.459829                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         4974                       # number of writebacks
+system.cpu.icache.writebacks::total              4974                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2184                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2184                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2184                       # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::cpu.inst         2184                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2184                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7212                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         7212                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         7212                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         7212                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         7212                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         7212                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312005999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    312005999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312005999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    312005999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312005999                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    312005999                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000297                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000297                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000297                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000297                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000297                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000297                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43262.063089                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43262.063089                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43262.063089                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 43262.063089                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43262.063089                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 43262.063089                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2588.929088                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               8413                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3873                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.172218                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2583.684571                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               8457                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3872                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.184143                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     1.256976                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2282.894376                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   304.777736                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000038                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069668                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.009301                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.079008                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3873                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          182                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          989                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           39                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2616                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.118195                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           118429                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          118429                       # Number of data accesses
-system.cpu.l2cache.Writeback_hits::writebacks           10                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           10                       # number of Writeback hits
+system.cpu.l2cache.tags.occ_blocks::writebacks     1.785192                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2278.815860                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   303.083519                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000054                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069544                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2610                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.118164                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           118500                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          118500                       # Number of data accesses
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 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.996104                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.996104                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76710.741688                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76084.720681                       # average overall miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.333768                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76376.375217                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76376.375217                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84020.334928                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84020.334928                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76839.139344                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76543.470218                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76376.375217                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76839.139344                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76543.470218                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -879,128 +885,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1534                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1534                       # number of ReadExReq MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::total         5406                       # number of overall MSHR misses
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 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
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 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996104                       # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.913232                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.496904                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.977011                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.604292                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.496904                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.977011                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.604292                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21677.364865                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21677.364865                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64960.234681                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64960.234681                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65732.975949                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65732.975949                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73089.073634                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.497050                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.497050                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.922737                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.922737                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.497050                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.979428                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.604563                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.497050                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.979428                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.604563                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21729.885057                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21729.885057                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64882.333768                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64882.333768                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66382.165605                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66382.165605                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74020.334928                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74020.334928                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66382.165605                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66839.139344                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66547.169811                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66382.165605                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66839.139344                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66547.169811                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        14563                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         5344                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests          433                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        14491                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         5309                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests          353                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          7704                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           10                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         4875                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          296                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          296                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          7663                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty           10                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         4883                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           40                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          261                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          261                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1540                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1540                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         7244                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          461                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19022                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4645                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             23667                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       444416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             573120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         299                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        14563                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.061251                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.239799                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         7212                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          453                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19042                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4558                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             23600                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       757120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128192                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             885312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         263                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples         9466                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.067293                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.250543                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              13671     93.87%     93.87% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                892      6.13%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               8829     93.27%     93.27% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                637      6.73%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          14563                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7291500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           9466                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       12229500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      10864500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      10815000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3149999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3120998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3871                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              296                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             296                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3870                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              261                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             261                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1534                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1534                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq          3871                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11402                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11402                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11402                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       345920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total       345920                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  345920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11331                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11331                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  11331                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       345856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total       345856                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  345856                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5701                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5666                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5701    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5666    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5701                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6922500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5666                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6923000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           29231454                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           29158989                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------